1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Support for AltoBeam GB20600 (a.k.a DMB-TH) demodulator 4*4882a593Smuzhiyun * ATBM8830, ATBM8831 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 2009 David T.L. Wong <davidtlwong@gmail.com> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __ATBM8830_PRIV_H 10*4882a593Smuzhiyun #define __ATBM8830_PRIV_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun struct atbm_state { 13*4882a593Smuzhiyun struct i2c_adapter *i2c; 14*4882a593Smuzhiyun /* configuration settings */ 15*4882a593Smuzhiyun const struct atbm8830_config *config; 16*4882a593Smuzhiyun struct dvb_frontend frontend; 17*4882a593Smuzhiyun }; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define REG_CHIP_ID 0x0000 20*4882a593Smuzhiyun #define REG_TUNER_BASEBAND 0x0001 21*4882a593Smuzhiyun #define REG_DEMOD_RUN 0x0004 22*4882a593Smuzhiyun #define REG_DSP_RESET 0x0005 23*4882a593Smuzhiyun #define REG_RAM_RESET 0x0006 24*4882a593Smuzhiyun #define REG_ADC_RESET 0x0007 25*4882a593Smuzhiyun #define REG_TSPORT_RESET 0x0008 26*4882a593Smuzhiyun #define REG_BLKERR_POL 0x000C 27*4882a593Smuzhiyun #define REG_I2C_GATE 0x0103 28*4882a593Smuzhiyun #define REG_TS_SAMPLE_EDGE 0x0301 29*4882a593Smuzhiyun #define REG_TS_PKT_LEN_204 0x0302 30*4882a593Smuzhiyun #define REG_TS_PKT_LEN_AUTO 0x0303 31*4882a593Smuzhiyun #define REG_TS_SERIAL 0x0305 32*4882a593Smuzhiyun #define REG_TS_CLK_FREERUN 0x0306 33*4882a593Smuzhiyun #define REG_TS_VALID_MODE 0x0307 34*4882a593Smuzhiyun #define REG_TS_CLK_MODE 0x030B /* 1 for serial, 0 for parallel */ 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define REG_TS_ERRBIT_USE 0x030C 37*4882a593Smuzhiyun #define REG_LOCK_STATUS 0x030D 38*4882a593Smuzhiyun #define REG_ADC_CONFIG 0x0602 39*4882a593Smuzhiyun #define REG_CARRIER_OFFSET 0x0827 /* 0x0827-0x0829 little endian */ 40*4882a593Smuzhiyun #define REG_DETECTED_PN_MODE 0x082D 41*4882a593Smuzhiyun #define REG_READ_LATCH 0x084D 42*4882a593Smuzhiyun #define REG_IF_FREQ 0x0A00 /* 0x0A00-0x0A02 little endian */ 43*4882a593Smuzhiyun #define REG_OSC_CLK 0x0A03 /* 0x0A03-0x0A05 little endian */ 44*4882a593Smuzhiyun #define REG_BYPASS_CCI 0x0A06 45*4882a593Smuzhiyun #define REG_ANALOG_LUMA_DETECTED 0x0A25 46*4882a593Smuzhiyun #define REG_ANALOG_AUDIO_DETECTED 0x0A26 47*4882a593Smuzhiyun #define REG_ANALOG_CHROMA_DETECTED 0x0A39 48*4882a593Smuzhiyun #define REG_FRAME_ERR_CNT 0x0B04 49*4882a593Smuzhiyun #define REG_USE_EXT_ADC 0x0C00 50*4882a593Smuzhiyun #define REG_SWAP_I_Q 0x0C01 51*4882a593Smuzhiyun #define REG_TPS_MANUAL 0x0D01 52*4882a593Smuzhiyun #define REG_TPS_CONFIG 0x0D02 53*4882a593Smuzhiyun #define REG_BYPASS_DEINTERLEAVER 0x0E00 54*4882a593Smuzhiyun #define REG_AGC_TARGET 0x1003 /* 0x1003-0x1005 little endian */ 55*4882a593Smuzhiyun #define REG_AGC_MIN 0x1020 56*4882a593Smuzhiyun #define REG_AGC_MAX 0x1023 57*4882a593Smuzhiyun #define REG_AGC_LOCK 0x1027 58*4882a593Smuzhiyun #define REG_AGC_PWM_VAL 0x1028 /* 0x1028-0x1029 little endian */ 59*4882a593Smuzhiyun #define REG_AGC_HOLD_LOOP 0x1031 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #endif 62*4882a593Smuzhiyun 63