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/OK3568_Linux_fs/u-boot/arch/arm/mach-rockchip/rv1126/
H A Drv1126.c15 #define FIREWALL_APB_BASE 0xffa60000
16 #define FW_DDR_CON_REG 0x80
18 #define USB_HOST_PRIORITY_REG 0xfe810008
19 #define USB_OTG_PRIORITY_REG 0xfe810088
20 #define DECOM_PRIORITY_REG 0xfe820088
21 #define DMA_PRIORITY_REG 0xfe820108
22 #define MCU_DM_PRIORITY_REG 0xfe820188
23 #define MCU_IM_PRIORITY_REG 0xfe820208
24 #define A7_PRIORITY_REG 0xfe830008
25 #define GMAC_PRIORITY_REG 0xfe840008
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/
H A Dpx30s-dram-default-timing.dtsi12 version = <0x101>;
25 sr_mc_gate_idle = <0>;
26 srpd_lite_idle = <0>;
27 standby_idle = <0>;
51 phy_dq_sr_odten = <0xf>;
52 phy_ca_sr_odten = <0x3>;
53 phy_clk_sr_odten = <0x3>;
55 phy_dq_sr_odtoff = <0xf>;
56 phy_ca_sr_odtoff = <0x3>;
57 phy_clk_sr_odtoff = <0x3>;
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/dce/
H A Ddmub_abm.c58 uint32_t fractional_pwm = (dc->dc->config.disable_fractional_pwm == false) ? 1 : 0; in dmub_abm_enable_fractional_pwm()
74 REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x103); in dmub_abm_init()
75 REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x101); in dmub_abm_init()
76 REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x103); in dmub_abm_init()
77 REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x101); in dmub_abm_init()
78 REG_WRITE(BL1_PWM_BL_UPDATE_SAMPLE_RATE, 0x101); in dmub_abm_init()
80 REG_SET_3(DC_ABM1_HG_MISC_CTRL, 0, in dmub_abm_init()
81 ABM1_HG_NUM_OF_BINS_SEL, 0, in dmub_abm_init()
83 ABM1_HG_BIN_BITWIDTH_SIZE_SEL, 0); in dmub_abm_init()
85 REG_SET_3(DC_ABM1_IPCSC_COEFF_SEL, 0, in dmub_abm_init()
[all …]
H A Ddce_abm.c52 #define MCP_ABM_LEVEL_SET 0x65
53 #define MCP_ABM_PIPE_SET 0x66
54 #define MCP_BL_SET 0x67
61 uint32_t rampingBoundary = 0xFFFF; in dce_abm_set_pipe()
66 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, in dce_abm_set_pipe()
80 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, in dce_abm_set_pipe()
93 unsigned int backlight_8_bit = 0; in dmcu_set_backlight_level()
96 if (backlight_pwm_u16_16 & 0x10000) in dmcu_set_backlight_level()
98 backlight_8_bit = 0xFF; in dmcu_set_backlight_level()
101 backlight_8_bit = (backlight_pwm_u16_16 >> 8) & 0xFF; in dmcu_set_backlight_level()
[all …]
/OK3568_Linux_fs/kernel/drivers/ide/
H A Dmacide.c27 #define IDE_BASE 0x50F1A000 /* Base address of IDE controller */
34 #define IDE_CONTROL 0x38 /* control/altstatus */
46 #define IDE_IFR 0x101 /* (0x101) IDE interrupt flags on Quadra:
48 * Bit 0+1: some interrupt flags
60 if (*ide_ifr & 0x20) in macide_test_irq()
62 return 0; in macide_test_irq()
67 *ide_ifr &= ~0x20; in macide_clear_irq()
75 memset(hw, 0, sizeof(*hw)); in macide_setup_ports()
77 for (i = 0; i < 8; i++) in macide_setup_ports()
115 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); in mac_ide_probe()
[all …]
/OK3568_Linux_fs/kernel/arch/arm/probes/
H A Ddecode-arm.c19 #define sign_extend(x, signbit) ((x) | (0 - ((x) & (1 << (signbit)))))
21 #define branch_displacement(insn) sign_extend(((insn) & 0xffffff) << 2, 25)
72 regs->ARM_pc = iaddr + 8 + disp + ((insn >> 23) & 0x2); in simulate_blx1()
79 int rm = insn & 0xf; in simulate_blx2bx()
85 regs->ARM_pc = rmv & ~0x1; in simulate_blx2bx()
87 if (rmv & 0x1) in simulate_blx2bx()
94 int rd = (insn >> 12) & 0xf; in simulate_mrs()
95 unsigned long mask = 0xf8ff03df; /* Mask out execution state */ in simulate_mrs()
119 /* PLDI (immediate) 1111 0100 x101 xxxx xxxx xxxx xxxx xxxx */
121 /* PLD (immediate) 1111 0101 x101 xxxx xxxx xxxx xxxx xxxx */
[all …]
/OK3568_Linux_fs/u-boot/drivers/usb/emul/
H A Dsandbox_keyb.c55 .bcdUSB = __constant_cpu_to_le16(0x0100),
57 .bDeviceClass = 0,
58 .bDeviceSubClass = 0,
59 .bDeviceProtocol = 0,
61 .idVendor = __constant_cpu_to_le16(0x1234),
62 .idProduct = __constant_cpu_to_le16(0x5679),
75 .bConfigurationValue = 0,
76 .iConfiguration = 0,
85 .bInterfaceNumber = 0,
86 .bAlternateSetting = 0,
[all …]
/OK3568_Linux_fs/kernel/arch/mips/sgi-ip22/
H A Dip22-mc.c35 …return ((memconfig & SGIMC_MCONFIG_RMASK) + 0x0100) << ((sgimc->systemid & SGIMC_SYSID_MASKREV) >=… in get_bank_size()
41 return bank % 2 ? res & 0xffff : res >> 16; in get_bank_config()
59 for (i = 0; i < 4; i++) { in probe_memory()
90 /* Step 0: Make sure we turn off the watchdog in case it's in sgimc_init()
103 sgimc->cstat = sgimc->gstat = 0; in sgimc_init()
120 tmp &= ~0xf; in sgimc_init()
121 tmp |= 0xd; in sgimc_init()
131 * 31 16 15 8 7 0 in sgimc_init()
136 * for IP22 we get INCREMENT=1, DIVIDER=1 == 0x101 in sgimc_init()
138 sgimc->divider = 0x101; in sgimc_init()
[all …]
/OK3568_Linux_fs/kernel/tools/perf/pmu-events/arch/arm64/ampere/emag/
H A Dclock.json4 "EventCode": "0x11",
10 "EventCode": "0x101",
16 "EventCode": "0x110",
/OK3568_Linux_fs/kernel/drivers/of/unittest-data/
H A Doverlay_bad_add_dup_node.dts19 power_bus = < 0x1 0x2 >;
26 power_bus_emergency = < 0x101 0x102 >;
/OK3568_Linux_fs/u-boot/include/
H A Dmicrel.h3 #define MII_KSZ9021_EXT_COMMON_CTRL 0x100
4 #define MII_KSZ9021_EXT_STRAP_STATUS 0x101
5 #define MII_KSZ9021_EXT_OP_STRAP_OVERRIDE 0x102
6 #define MII_KSZ9021_EXT_OP_STRAP_STATUS 0x103
7 #define MII_KSZ9021_EXT_RGMII_CLOCK_SKEW 0x104
8 #define MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW 0x105
9 #define MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW 0x106
10 #define MII_KSZ9021_EXT_ANALOG_TEST 0x107
12 #define MII_KSZ9031_MOD_REG 0x0000
14 #define MII_KSZ9031_MOD_DATA_NO_POST_INC 0x4000
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/arm/
H A Dcpus.yaml30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
31 the reg property contained in bits 7 down to 0
49 this property is required and must be set to 0.
52 required and matches the CPUID[11:0] register bits.
54 Bits [11:0] in the reg cell must be set to
55 bits [11:0] in CPU ID register.
57 All other bits in the reg cell must be set to 0.
60 required and matches the CPU MPIDR[23:0] register
63 Bits [23:0] in the reg cell must be set to
64 bits [23:0] in MPIDR.
[all …]
H A Dcpu-capacity.txt70 #size-cells = <0>;
101 CPU_SLEEP_0: cpu-sleep-0 {
103 arm,psci-suspend-param = <0x0010000>;
110 CLUSTER_SLEEP_0: cluster-sleep-0 {
112 arm,psci-suspend-param = <0x1010000>;
120 A57_0: cpu@0 {
122 reg = <0x0 0x0>;
126 clocks = <&scpi_dvfs 0>;
133 reg = <0x0 0x1>;
137 clocks = <&scpi_dvfs 0>;
[all …]
H A Dnvidia,tegra194-ccplex.yaml41 #size-cells = <0>;
43 cpu0_0: cpu@0 {
46 reg = <0x0>;
53 reg = <0x001>;
60 reg = <0x100>;
67 reg = <0x101>;
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/
H A Dmulti-inno,mi0283qt.txt11 the panel interface mode (IM[3:0] pins):
13 - absent: IM=x101 3-wire 9-bit data serial interface
17 - rotation: panel rotation in degrees counter clockwise (0,90,180,270)
20 mi0283qt@0{
22 reg = <0>;
25 dc-gpios = <&gpio 25 0>;
/OK3568_Linux_fs/kernel/include/soc/arc/
H A Dtimers.h12 #define ARC_REG_TIMER0_LIMIT 0x23 /* timer 0 limit */
13 #define ARC_REG_TIMER0_CTRL 0x22 /* timer 0 control */
14 #define ARC_REG_TIMER0_CNT 0x21 /* timer 0 count */
15 #define ARC_REG_TIMER1_LIMIT 0x102 /* timer 1 limit */
16 #define ARC_REG_TIMER1_CTRL 0x101 /* timer 1 control */
17 #define ARC_REG_TIMER1_CNT 0x100 /* timer 1 count */
20 #define TIMER_CTRL_IE (1 << 0) /* Interrupt when Count reaches limit */
23 #define ARC_TIMERN_MAX 0xFFFFFFFF
25 #define ARC_REG_TIMERS_BCR 0x75
/OK3568_Linux_fs/kernel/arch/powerpc/include/asm/
H A Dps3gpu.h16 #define L1GPU_CONTEXT_ATTRIBUTE_DISPLAY_SYNC 0x101
17 #define L1GPU_CONTEXT_ATTRIBUTE_DISPLAY_FLIP 0x102
19 #define L1GPU_CONTEXT_ATTRIBUTE_FB_SETUP 0x600
20 #define L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT 0x601
21 #define L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT_SYNC 0x602
22 #define L1GPU_CONTEXT_ATTRIBUTE_FB_CLOSE 0x603
39 head, ddr_offset, 0, 0); in lv1_gpu_display_sync()
47 head, ddr_offset, 0, 0); in lv1_gpu_display_flip()
55 xdr_lpar, xdr_size, ioif_offset, 0); in lv1_gpu_fb_setup()
70 L1GPU_CONTEXT_ATTRIBUTE_FB_CLOSE, 0, in lv1_gpu_fb_close()
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/cpu/
H A Dcpu-topology.txt87 (ie socket/cluster/core/thread) (where N = {0, 1, ...} is the node number; nodes
89 sequential N value, starting from 0).
187 #size-cells = <0>;
276 CPU0: cpu@0 {
279 reg = <0x0 0x0>;
281 cpu-release-addr = <0 0x20000000>;
287 reg = <0x0 0x1>;
289 cpu-release-addr = <0 0x20000000>;
295 reg = <0x0 0x100>;
297 cpu-release-addr = <0 0x20000000>;
[all …]
/OK3568_Linux_fs/kernel/include/media/
H A Dv4l2-controls_rockchip.h22 #define V4L2_CID_USER_RK_BASE (V4L2_CID_USER_BASE + 0x1080)
24 #define RK_V4L2_CID_AUDIO_SAMPLING_RATE (V4L2_CID_USER_RK_BASE + 0x100)
25 #define RK_V4L2_CID_AUDIO_PRESENT (V4L2_CID_USER_RK_BASE + 0x101)
/OK3568_Linux_fs/kernel/drivers/staging/rtl8192e/rtl8192e/
H A Dr8192E_hw.h11 BaseBand_Config_PHY_REG = 0,
15 #define RTL8187_REQT_READ 0xc0
16 #define RTL8187_REQT_WRITE 0x40
17 #define RTL8187_REQ_GET_REGS 0x05
18 #define RTL8187_REQ_SET_REGS 0x05
24 #define BB_ANTATTEN_CHAN14 0x0c
25 #define BB_ANTENNA_B 0x40
33 #define RTL8190_EEPROM_ID 0x8129
34 #define EEPROM_VID 0x02
35 #define EEPROM_DID 0x04
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/marvell/
H A Darmada-ap810-ap0-octa-core.dtsi13 #size-cells = <0>;
16 cpu0: cpu@0 {
19 reg = <0x000>;
25 reg = <0x001>;
31 reg = <0x100>;
37 reg = <0x101>;
43 reg = <0x200>;
49 reg = <0x201>;
55 reg = <0x300>;
61 reg = <0x301>;
/OK3568_Linux_fs/kernel/drivers/media/rc/keymaps/
H A Drc-x96max.c13 { 0x140, KEY_POWER },
22 { 0x118, KEY_VOLUMEUP },
23 { 0x110, KEY_VOLUMEDOWN },
25 { 0x143, KEY_MUTE }, // config
27 { 0x100, KEY_EPG }, // mouse
28 { 0x119, KEY_BACK },
30 { 0x116, KEY_UP },
31 { 0x151, KEY_LEFT },
32 { 0x150, KEY_RIGHT },
33 { 0x11a, KEY_DOWN },
[all …]
/OK3568_Linux_fs/u-boot/arch/arc/include/asm/
H A Darcregs.h19 #define ARC_AUX_IDENTITY 0x04
20 #define ARC_AUX_STATUS32 0x0a
23 #define ARC_AUX_IC_IVIC 0x10
24 #define ARC_AUX_IC_CTRL 0x11
25 #define ARC_AUX_IC_IVIL 0x19
27 #define ARC_AUX_IC_PTAG 0x1E
29 #define ARC_BCR_IC_BUILD 0x77
32 #define ARC_AUX_TIMER0_CNT 0x21 /* Timer 0 count */
33 #define ARC_AUX_TIMER0_CTRL 0x22 /* Timer 0 control */
34 #define ARC_AUX_TIMER0_LIMIT 0x23 /* Timer 0 limit */
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dusb_a9g20-dab-mmx.dtsi21 i2c-gpio@0 {
69 #size-cells = <0>;
74 linux,code = <0x100>;
80 linux,code = <0x101>;
86 linux,code = <0x102>;
92 linux,code = <0x103>;
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/broadcom/stingray/
H A Dstingray-pcie.dtsi8 reg = <0 0x60400000 0 0x1000>;
11 bus-range = <0x0 0x1>;
16 ranges = <0x83000000 0 0x10000000 0 0x10000000 0 0x20000000>;
20 msi-map = <0x100 &gic_its 0x2000 0x1>, /* PF0 */
21 <0x108 &gic_its 0x2040 0x8>, /* PF0-VF0-7 */
22 <0x101 &gic_its 0x2080 0x1>, /* PF1 */
23 <0x110 &gic_its 0x20c8 0x8>, /* PF1-VF8-15 */
24 <0x102 &gic_its 0x2100 0x1>, /* PF2 */
25 <0x118 &gic_its 0x2150 0x8>, /* PF2-VF16-23 */
26 <0x103 &gic_its 0x2180 0x1>, /* PF3 */
[all …]

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