1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. All rights reserved. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _ASM_ARC_ARCREGS_H 8*4882a593Smuzhiyun #define _ASM_ARC_ARCREGS_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <asm/cache.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* 13*4882a593Smuzhiyun * ARC architecture has additional address space - auxiliary registers. 14*4882a593Smuzhiyun * These registers are mostly used for configuration purposes. 15*4882a593Smuzhiyun * These registers are not memory mapped and special commands are used for 16*4882a593Smuzhiyun * access: "lr"/"sr". 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define ARC_AUX_IDENTITY 0x04 20*4882a593Smuzhiyun #define ARC_AUX_STATUS32 0x0a 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* Instruction cache related auxiliary registers */ 23*4882a593Smuzhiyun #define ARC_AUX_IC_IVIC 0x10 24*4882a593Smuzhiyun #define ARC_AUX_IC_CTRL 0x11 25*4882a593Smuzhiyun #define ARC_AUX_IC_IVIL 0x19 26*4882a593Smuzhiyun #if (CONFIG_ARC_MMU_VER == 3) 27*4882a593Smuzhiyun #define ARC_AUX_IC_PTAG 0x1E 28*4882a593Smuzhiyun #endif 29*4882a593Smuzhiyun #define ARC_BCR_IC_BUILD 0x77 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* Timer related auxiliary registers */ 32*4882a593Smuzhiyun #define ARC_AUX_TIMER0_CNT 0x21 /* Timer 0 count */ 33*4882a593Smuzhiyun #define ARC_AUX_TIMER0_CTRL 0x22 /* Timer 0 control */ 34*4882a593Smuzhiyun #define ARC_AUX_TIMER0_LIMIT 0x23 /* Timer 0 limit */ 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define ARC_AUX_TIMER1_CNT 0x100 /* Timer 1 count */ 37*4882a593Smuzhiyun #define ARC_AUX_TIMER1_CTRL 0x101 /* Timer 1 control */ 38*4882a593Smuzhiyun #define ARC_AUX_TIMER1_LIMIT 0x102 /* Timer 1 limit */ 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define ARC_AUX_INTR_VEC_BASE 0x25 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* Data cache related auxiliary registers */ 43*4882a593Smuzhiyun #define ARC_AUX_DC_IVDC 0x47 44*4882a593Smuzhiyun #define ARC_AUX_DC_CTRL 0x48 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define ARC_AUX_DC_IVDL 0x4A 47*4882a593Smuzhiyun #define ARC_AUX_DC_FLSH 0x4B 48*4882a593Smuzhiyun #define ARC_AUX_DC_FLDL 0x4C 49*4882a593Smuzhiyun #if (CONFIG_ARC_MMU_VER == 3) 50*4882a593Smuzhiyun #define ARC_AUX_DC_PTAG 0x5C 51*4882a593Smuzhiyun #endif 52*4882a593Smuzhiyun #define ARC_BCR_DC_BUILD 0x72 53*4882a593Smuzhiyun #define ARC_BCR_SLC 0xce 54*4882a593Smuzhiyun #define ARC_AUX_SLC_CONFIG 0x901 55*4882a593Smuzhiyun #define ARC_AUX_SLC_CTRL 0x903 56*4882a593Smuzhiyun #define ARC_AUX_SLC_FLUSH 0x904 57*4882a593Smuzhiyun #define ARC_AUX_SLC_INVALIDATE 0x905 58*4882a593Smuzhiyun #define ARC_AUX_SLC_IVDL 0x910 59*4882a593Smuzhiyun #define ARC_AUX_SLC_FLDL 0x912 60*4882a593Smuzhiyun #define ARC_BCR_CLUSTER 0xcf 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* IO coherency related auxiliary registers */ 63*4882a593Smuzhiyun #define ARC_AUX_IO_COH_ENABLE 0x500 64*4882a593Smuzhiyun #define ARC_AUX_IO_COH_PARTIAL 0x501 65*4882a593Smuzhiyun #define ARC_AUX_IO_COH_AP0_BASE 0x508 66*4882a593Smuzhiyun #define ARC_AUX_IO_COH_AP0_SIZE 0x509 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 69*4882a593Smuzhiyun /* Accessors for auxiliary registers */ 70*4882a593Smuzhiyun #define read_aux_reg(reg) __builtin_arc_lr(reg) 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* gcc builtin sr needs reg param to be long immediate */ 73*4882a593Smuzhiyun #define write_aux_reg(reg_immed, val) \ 74*4882a593Smuzhiyun __builtin_arc_sr((unsigned int)val, reg_immed) 75*4882a593Smuzhiyun #endif /* __ASSEMBLY__ */ 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #endif /* _ASM_ARC_ARCREGS_H */ 78