1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2016-17 Synopsys, Inc. (www.synopsys.com) 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __SOC_ARC_TIMERS_H 7*4882a593Smuzhiyun #define __SOC_ARC_TIMERS_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <soc/arc/aux.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* Timer related Aux registers */ 12*4882a593Smuzhiyun #define ARC_REG_TIMER0_LIMIT 0x23 /* timer 0 limit */ 13*4882a593Smuzhiyun #define ARC_REG_TIMER0_CTRL 0x22 /* timer 0 control */ 14*4882a593Smuzhiyun #define ARC_REG_TIMER0_CNT 0x21 /* timer 0 count */ 15*4882a593Smuzhiyun #define ARC_REG_TIMER1_LIMIT 0x102 /* timer 1 limit */ 16*4882a593Smuzhiyun #define ARC_REG_TIMER1_CTRL 0x101 /* timer 1 control */ 17*4882a593Smuzhiyun #define ARC_REG_TIMER1_CNT 0x100 /* timer 1 count */ 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* CTRL reg bits */ 20*4882a593Smuzhiyun #define TIMER_CTRL_IE (1 << 0) /* Interrupt when Count reaches limit */ 21*4882a593Smuzhiyun #define TIMER_CTRL_NH (1 << 1) /* Count only when CPU NOT halted */ 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define ARC_TIMERN_MAX 0xFFFFFFFF 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define ARC_REG_TIMERS_BCR 0x75 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun struct bcr_timer { 28*4882a593Smuzhiyun #ifdef CONFIG_CPU_BIG_ENDIAN 29*4882a593Smuzhiyun unsigned int pad2:15, rtsc:1, pad1:5, rtc:1, t1:1, t0:1, ver:8; 30*4882a593Smuzhiyun #else 31*4882a593Smuzhiyun unsigned int ver:8, t0:1, t1:1, rtc:1, pad1:5, rtsc:1, pad2:15; 32*4882a593Smuzhiyun #endif 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #endif 36