1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun *Copyright(c) 2018 Broadcom 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyunpcie8: pcie@60400000 { 7*4882a593Smuzhiyun compatible = "brcm,iproc-pcie-paxc-v2"; 8*4882a593Smuzhiyun reg = <0 0x60400000 0 0x1000>; 9*4882a593Smuzhiyun linux,pci-domain = <8>; 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun bus-range = <0x0 0x1>; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #address-cells = <3>; 14*4882a593Smuzhiyun #size-cells = <2>; 15*4882a593Smuzhiyun device_type = "pci"; 16*4882a593Smuzhiyun ranges = <0x83000000 0 0x10000000 0 0x10000000 0 0x20000000>; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun dma-coherent; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun msi-map = <0x100 &gic_its 0x2000 0x1>, /* PF0 */ 21*4882a593Smuzhiyun <0x108 &gic_its 0x2040 0x8>, /* PF0-VF0-7 */ 22*4882a593Smuzhiyun <0x101 &gic_its 0x2080 0x1>, /* PF1 */ 23*4882a593Smuzhiyun <0x110 &gic_its 0x20c8 0x8>, /* PF1-VF8-15 */ 24*4882a593Smuzhiyun <0x102 &gic_its 0x2100 0x1>, /* PF2 */ 25*4882a593Smuzhiyun <0x118 &gic_its 0x2150 0x8>, /* PF2-VF16-23 */ 26*4882a593Smuzhiyun <0x103 &gic_its 0x2180 0x1>, /* PF3 */ 27*4882a593Smuzhiyun <0x120 &gic_its 0x21d8 0x8>, /* PF3-VF24-31 */ 28*4882a593Smuzhiyun <0x104 &gic_its 0x2200 0x1>, /* PF4 */ 29*4882a593Smuzhiyun <0x128 &gic_its 0x2260 0x8>, /* PF4-VF32-39 */ 30*4882a593Smuzhiyun <0x105 &gic_its 0x2280 0x1>, /* PF5 */ 31*4882a593Smuzhiyun <0x130 &gic_its 0x22e8 0x8>, /* PF5-VF40-47 */ 32*4882a593Smuzhiyun <0x106 &gic_its 0x2300 0x1>, /* PF6 */ 33*4882a593Smuzhiyun <0x138 &gic_its 0x2370 0x8>, /* PF6-VF48-55 */ 34*4882a593Smuzhiyun <0x107 &gic_its 0x2380 0x1>, /* PF7 */ 35*4882a593Smuzhiyun <0x140 &gic_its 0x23f8 0x8>; /* PF7-VF56-63 */ 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun phys = <&pcie_phy 8>; 38*4882a593Smuzhiyun phy-names = "pcie-phy"; 39*4882a593Smuzhiyun}; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyunpcie-ss { 42*4882a593Smuzhiyun compatible = "simple-bus"; 43*4882a593Smuzhiyun #address-cells = <1>; 44*4882a593Smuzhiyun #size-cells = <1>; 45*4882a593Smuzhiyun ranges = <0x0 0x0 0x40000000 0x800>; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun pcie_phy: phy@0 { 48*4882a593Smuzhiyun compatible = "brcm,sr-pcie-phy"; 49*4882a593Smuzhiyun reg = <0x0 0x200>; 50*4882a593Smuzhiyun brcm,sr-cdru = <&cdru>; 51*4882a593Smuzhiyun brcm,sr-mhb = <&mhb>; 52*4882a593Smuzhiyun #phy-cells = <1>; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun}; 55