15 #define FIREWALL_APB_BASE	0xffa60000
16 #define FW_DDR_CON_REG		0x80
18 #define USB_HOST_PRIORITY_REG	0xfe810008
19 #define USB_OTG_PRIORITY_REG	0xfe810088
20 #define DECOM_PRIORITY_REG	0xfe820088
21 #define DMA_PRIORITY_REG	0xfe820108
22 #define MCU_DM_PRIORITY_REG	0xfe820188
23 #define MCU_IM_PRIORITY_REG	0xfe820208
24 #define A7_PRIORITY_REG		0xfe830008
25 #define GMAC_PRIORITY_REG	0xfe840008
26 #define NPU_PRIORITY_REG	0xfe850008
27 #define EMMC_PRIORITY_REG	0xfe860008
28 #define NANDC_PRIORITY_REG	0xfe860088
29 #define SFC_PRIORITY_REG	0xfe860208
30 #define SDMMC_PRIORITY_REG	0xfe868008
31 #define SDIO_PRIORITY_REG	0xfe86c008
32 #define VEPU_RD0_PRIORITY_REG	0xfe870008
33 #define VEPU_RD1_PRIORITY_REG	0xfe870088
34 #define VEPU_WR_PRIORITY_REG	0xfe870108
35 #define ISPP_M0_PRIORITY_REG	0xfe880008
36 #define ISPP_M1_PRIORITY_REG	0xfe880088
37 #define ISP_PRIORITY_REG	0xfe890008
38 #define CIF_LITE_PRIORITY_REG	0xfe890088
39 #define CIF_PRIORITY_REG	0xfe890108
40 #define IEP_PRIORITY_REG	0xfe8a0008
41 #define RGA_RD_PRIORITY_REG	0xfe8a0088
42 #define RGA_WR_PRIORITY_REG	0xfe8a0108
43 #define VOP_PRIORITY_REG	0xfe8a0188
44 #define VDPU_PRIORITY_REG	0xfe8b0008
45 #define JPEG_PRIORITY_REG	0xfe8c0008
46 #define CRYPTO_PRIORITY_REG	0xfe8d0008
48 #define ISPP_M0_PRIORITY_EX_REG	0xfe880018
49 #define ISPP_M1_PRIORITY_EX_REG	0xfe880098
50 #define ISP_PRIORITY_EX_REG	0xfe890018
51 #define CIF_LT_PRIORITY_EX_REG	0xfe890098
52 #define CIF_PRIORITY_EX_REG	0xfe890118
53 #define VOP_PRIORITY_EX_REG	0xfe8a0198
54 #define VDPU_PRIORITY_EX_REG	0xfe8b0018
56 #define PMU_BASE_ADDR		0xff3e0000
58 #define PMU_BUS_IDLE_SFTCON(n)	(0xc0 + (n) * 4)
59 #define PMU_BUS_IDLE_ACK	(0xd0)
60 #define PMU_BUS_IDLE_ST		(0xd8)
61 #define PMU_NOC_AUTO_CON0	(0xe0)
62 #define PMU_NOC_AUTO_CON1	(0xe4)
63 #define PMU_PWR_DWN_ST		(0x108)
64 #define PMU_PWR_GATE_SFTCON	(0x110)
69 #define CRU_BASE		0xFF490000
70 #define CRU_CLKSEL_CON02	0x108
71 #define CRU_CLKSEL_CON03	0x10c
72 #define CRU_CLKSEL_CON27	0x16c
73 #define CRU_CLKSEL_CON31	0x17c
74 #define CRU_CLKSEL_CON33	0x184
75 #define CRU_CLKSEL_CON40	0x1a0
76 #define CRU_CLKSEL_CON49	0x1c4
77 #define CRU_CLKSEL_CON50	0x1c8
78 #define CRU_CLKSEL_CON51	0x1cc
79 #define CRU_CLKSEL_CON54	0x1d8
80 #define CRU_CLKSEL_CON61	0x1f4
81 #define CRU_CLKSEL_CON63	0x1fc
82 #define CRU_CLKSEL_CON65	0x204
83 #define CRU_CLKSEL_CON67	0x20c
84 #define CRU_CLKSEL_CON68	0x210
85 #define CRU_CLKSEL_CON69	0x214
86 #define CRU_SOFTRST_CON02	0x308
88 #define CRU_PMU_BASE		0xFF480000
89 #define CRU_PMU_GPLL_CON0	0x10
90 #define CRU_PMU_GPLL_CON1	0x14
92 #define GRF_BASE		0xFE000000
93 #define GRF_SOC_CON2		0x008
94 #define PMUGRF_BASE		0xFE020000
95 #define SGRF_BASE		0xFE0A0000
96 #define SGRF_CON_SCR1_BOOT_ADDR	0x0b0
97 #define SGRF_SOC_CON3		0x00c
98 #define CRU_SOFTRST_CON11	0xFF49032C
99 #define PMUGRF_SOC_CON1		0xFE020104
100 #define PMUGRF_RSTFUNC_STATUS	0xFE020230
101 #define PMUGRF_RSTFUNC_CLR	0xFE020234
104 #define GRF_IOFUNC_CON3		0xFF01026C
105 #define GRF1_GPIO0D_P		0xFE010104
106 #define OTP_NS_BASE		0xFF5C0000
107 #define OTP_S_BASE		0xFF5D0000
108 #define OTP_NVM_TRWH		0x28
110 #define PMU_GRF_BASE		0xFE020000
111 #define PMUGRF_GPIO0B_IOMUX_H	0xc
116 	GPIO1A7_GPIO		= 0,
124 	GPIO1A6_GPIO		= 0,
132 	GPIO1A5_GPIO		= 0,
138 	GPIO1A4_SHIFT		= 0,
139 	GPIO1A4_MASK		= GENMASK(2, 0),
140 	GPIO1A4_GPIO		= 0,
147 	GPIO1C3_GPIO		= 0,
152 	GPIO1C2_GPIO		= 0,
157 	GPIO1D5_GPIO		= 0,
162 	GPIO1D4_SHIFT		= 0,
163 	GPIO1D4_MASK		= GENMASK(2, 0),
164 	GPIO1D4_GPIO		= 0,
171 	GPIO1D1_GPIO		= 0,
178 	GPIO1D0_SHIFT		= 0,
179 	GPIO1D0_MASK		= GENMASK(2, 0),
180 	GPIO1D0_GPIO		= 0,
189 	GPIO2A7_GPIO		= 0,
199 	GPIO2A6_GPIO		= 0,
208 	GPIO2A1_GPIO		= 0,
213 	GPIO2A0_SHIFT		= 0,
214 	GPIO2A0_MASK		= GENMASK(2, 0),
215 	GPIO2A0_GPIO		= 0,
222 	GPIO2B1_GPIO		= 0,
230 	GPIO2B0_SHIFT		= 0,
231 	GPIO2B0_MASK		= GENMASK(2, 0),
232 	GPIO2B0_GPIO		= 0,
242 	GPIO3A7_GPIO		= 0,
252 	GPIO3A6_GPIO		= 0,
262 	GPIO3A5_GPIO		= 0,
270 	GPIO3A4_SHIFT		= 0,
271 	GPIO3A4_MASK		= GENMASK(2, 0),
272 	GPIO3A4_GPIO		= 0,
282 	GPIO3A3_GPIO		= 0,
288 	GPIO3A2_GPIO		= 0,
294 	GPIO3A1_GPIO		= 0,
303 	GPIO3A0_SHIFT		= 0,
304 	GPIO3A0_MASK		= GENMASK(2, 0),
305 	GPIO3A0_GPIO		= 0,
316 	GPIO3C7_GPIO		= 0,
323 	GPIO3C6_MASK		= GENMASK(10, 0),
324 	GPIO3C6_GPIO		= 0,
332 	UART2_IO_SEL_M0		= 0,
337 	UART3_IO_SEL_M0		= 0,
343 	UART4_IO_SEL_M0		= 0,
349 	UART5_IO_SEL_M0		= 0,
357 	UART1_IO_SEL_M0		= 0,
362 	GPIO0B7_GPIO		= 0,
369 	GPIO0B6_GPIO		= 0,
377 #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff560000)  in board_debug_uart_init()
386 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff410000)  in board_debug_uart_init()
390     (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)  in board_debug_uart_init()
412 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff570000)  in board_debug_uart_init()
415     (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)  in board_debug_uart_init()
437 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff580000)  in board_debug_uart_init()
440     (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)  in board_debug_uart_init()
473 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff590000)  in board_debug_uart_init()
476     (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)  in board_debug_uart_init()
509 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff5a0000)  in board_debug_uart_init()
512     (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)  in board_debug_uart_init()
565 		return 0;  in arch_cpu_init()
576 	/* set otp tRWH to 0x9 for stable read */  in arch_cpu_init()
577 	writel(0x9, OTP_NS_BASE + OTP_NVM_TRWH);  in arch_cpu_init()
578 	writel(0x9, OTP_S_BASE + OTP_NVM_TRWH);  in arch_cpu_init()
581 	 * Just set region 0 to unsecure.  in arch_cpu_init()
584 	writel(0, FIREWALL_APB_BASE + FW_DDR_CON_REG);  in arch_cpu_init()
588 	writel(0x00300000, GRF_IOFUNC_CON3);  in arch_cpu_init()
591 	writel(0x00ff0055, CRU_BASE + CRU_CLKSEL_CON65);  in arch_cpu_init()
592 	writel(0x00ff0055, CRU_BASE + CRU_CLKSEL_CON67);  in arch_cpu_init()
598 	writel(0xffffffff, PMU_BASE_ADDR + PMU_NOC_AUTO_CON0);  in arch_cpu_init()
599 	writel(0xffffffff, PMU_BASE_ADDR + PMU_NOC_AUTO_CON1);  in arch_cpu_init()
603 	writel(0x00030000, CRU_PMU_BASE);  in arch_cpu_init()
604 	writel(0xffff1063, CRU_PMU_BASE + CRU_PMU_GPLL_CON0);  in arch_cpu_init()
605 	writel(0xffff1442, CRU_PMU_BASE + CRU_PMU_GPLL_CON1);  in arch_cpu_init()
606 	writel(0x00030001, CRU_PMU_BASE);  in arch_cpu_init()
609 	writel(0x00ff0003, CRU_BASE + CRU_CLKSEL_CON02);  in arch_cpu_init()
610 	writel(0x00ff0005, CRU_BASE + CRU_CLKSEL_CON03);  in arch_cpu_init()
611 	writel(0xffff8383, CRU_BASE + CRU_CLKSEL_CON27);  in arch_cpu_init()
612 	writel(0x00ff0083, CRU_BASE + CRU_CLKSEL_CON31);  in arch_cpu_init()
613 	writel(0x00ff0083, CRU_BASE + CRU_CLKSEL_CON33);  in arch_cpu_init()
614 	writel(0xffff4385, CRU_BASE + CRU_CLKSEL_CON40);  in arch_cpu_init()
615 	writel(0x00ff0043, CRU_BASE + CRU_CLKSEL_CON49);  in arch_cpu_init()
616 	writel(0x00ff0003, CRU_BASE + CRU_CLKSEL_CON50);  in arch_cpu_init()
617 	writel(0x00ff0003, CRU_BASE + CRU_CLKSEL_CON51);  in arch_cpu_init()
618 	writel(0xff000300, CRU_BASE + CRU_CLKSEL_CON54);  in arch_cpu_init()
619 	writel(0xff008900, CRU_BASE + CRU_CLKSEL_CON61);  in arch_cpu_init()
620 	writel(0x00ff0089, CRU_BASE + CRU_CLKSEL_CON63);  in arch_cpu_init()
621 	writel(0x00ff0045, CRU_BASE + CRU_CLKSEL_CON68);  in arch_cpu_init()
622 	writel(0x00ff0043, CRU_BASE + CRU_CLKSEL_CON69);  in arch_cpu_init()
626 	writel(0xffff0000, PMU_BASE_ADDR + PMU_PWR_GATE_SFTCON);  in arch_cpu_init()
634 	writel(0xffff0000, PMU_BASE_ADDR + PMU_BUS_IDLE_SFTCON(0));  in arch_cpu_init()
635 	writel(0xffff0000, PMU_BASE_ADDR + PMU_BUS_IDLE_SFTCON(1));  in arch_cpu_init()
655 		printf("PMU_PWR_DOWN_ST: 0x%08x\n", pd_st);  in arch_cpu_init()
656 		printf("PMU_BUS_IDLE_ST: 0x%08x\n", idle_st);  in arch_cpu_init()
667 	writel(0x303, USB_HOST_PRIORITY_REG);  in arch_cpu_init()
668 	writel(0x303, USB_OTG_PRIORITY_REG);  in arch_cpu_init()
669 	writel(0x101, DECOM_PRIORITY_REG);  in arch_cpu_init()
670 	writel(0x303, DMA_PRIORITY_REG);  in arch_cpu_init()
671 	writel(0x101, MCU_DM_PRIORITY_REG);  in arch_cpu_init()
672 	writel(0x101, MCU_IM_PRIORITY_REG);  in arch_cpu_init()
673 	writel(0x101, A7_PRIORITY_REG);  in arch_cpu_init()
674 	writel(0x303, GMAC_PRIORITY_REG);  in arch_cpu_init()
675 	writel(0x101, NPU_PRIORITY_REG);  in arch_cpu_init()
676 	writel(0x303, EMMC_PRIORITY_REG);  in arch_cpu_init()
677 	writel(0x303, NANDC_PRIORITY_REG);  in arch_cpu_init()
678 	writel(0x303, SFC_PRIORITY_REG);  in arch_cpu_init()
679 	writel(0x303, SDMMC_PRIORITY_REG);  in arch_cpu_init()
680 	writel(0x303, SDIO_PRIORITY_REG);  in arch_cpu_init()
681 	writel(0x101, VEPU_RD0_PRIORITY_REG);  in arch_cpu_init()
682 	writel(0x101, VEPU_RD1_PRIORITY_REG);  in arch_cpu_init()
683 	writel(0x101, VEPU_WR_PRIORITY_REG);  in arch_cpu_init()
684 	writel(0x101, ISPP_M0_PRIORITY_REG);  in arch_cpu_init()
685 	writel(0x101, ISPP_M1_PRIORITY_REG);  in arch_cpu_init()
686 	writel(0x101, ISP_PRIORITY_REG);  in arch_cpu_init()
687 	writel(0x202, CIF_LITE_PRIORITY_REG);  in arch_cpu_init()
688 	writel(0x202, CIF_PRIORITY_REG);  in arch_cpu_init()
689 	writel(0x101, IEP_PRIORITY_REG);  in arch_cpu_init()
690 	writel(0x101, RGA_RD_PRIORITY_REG);  in arch_cpu_init()
691 	writel(0x101, RGA_WR_PRIORITY_REG);  in arch_cpu_init()
692 	writel(0x202, VOP_PRIORITY_REG);  in arch_cpu_init()
693 	writel(0x101, VDPU_PRIORITY_REG);  in arch_cpu_init()
694 	writel(0x101, JPEG_PRIORITY_REG);  in arch_cpu_init()
695 	writel(0x101, CRYPTO_PRIORITY_REG);  in arch_cpu_init()
697 	writel(0x1, ISP_PRIORITY_EX_REG);  in arch_cpu_init()
704 	writel(0x00770011, PMU_GRF_BASE + PMUGRF_GPIO0B_IOMUX_H);  in arch_cpu_init()
708 	/* Just set region 0 to unsecure */  in arch_cpu_init()
709 	writel(0, FIREWALL_APB_BASE + FW_DDR_CON_REG);  in arch_cpu_init()
712 	writel(((0x1 << 6 | (1 << 8)) << 16) | (0x1 << 6) | (1 << 8), CRU_SOFTRST_CON11);  in arch_cpu_init()
714 	writel(((0x1 << 6 | (1 << 8)) << 16) | (0), CRU_SOFTRST_CON11);  in arch_cpu_init()
717 	writel(0x1 << 7 | 1 << 23, PMUGRF_SOC_CON1);  in arch_cpu_init()
724 	writel(0x0F0F0303, &grf->gpio0d_iomux_h);  in arch_cpu_init()
725 	writel(0xFFFF3333, &grf->gpio1a_iomux_l);  in arch_cpu_init()
729 	writel(0xFFFF2222, &grf->gpio0c_iomux_h);  in arch_cpu_init()
730 	writel(0xFFFF2222, &grf->gpio0d_iomux_l);  in arch_cpu_init()
731 	writel(0xF0F02020, &grf->gpio0d_iomux_h);  in arch_cpu_init()
735 	writel(0xFFFF1111, &grf->gpio0c_iomux_h);  in arch_cpu_init()
736 	writel(0xFFFF1111, &grf->gpio0d_iomux_l);  in arch_cpu_init()
737 	writel(0xF0FF1011, &grf->gpio0d_iomux_h);  in arch_cpu_init()
738 	writel(0xFFFF1111, &grf->gpio1a_iomux_l);  in arch_cpu_init()
744 	writel(((0x3 << 12) << 16) | (0x1 << 12), GRF1_GPIO0D_P);  in arch_cpu_init()
747 	return 0;  in arch_cpu_init()
758 	writel(0x80008000, GRF_BASE + GRF_SOC_CON2);  in spl_fit_standalone_release()
760 	writel(0x04000400, CRU_BASE + CRU_SOFTRST_CON02);  in spl_fit_standalone_release()
764 	writel(0x00ff00bf, SGRF_BASE + SGRF_SOC_CON3);  in spl_fit_standalone_release()
767 	writel(0x04000000, CRU_BASE + CRU_SOFTRST_CON02);  in spl_fit_standalone_release()
769 	return 0;  in spl_fit_standalone_release()