1 /*
2 * Copyright (c) 2019 Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6 #include <common.h>
7 #include <ramdisk.h>
8 #include <asm/io.h>
9 #include <asm/arch/boot_mode.h>
10 #include <asm/arch/hardware.h>
11 #include <asm/arch/grf_rv1126.h>
12
13 DECLARE_GLOBAL_DATA_PTR;
14
15 #define FIREWALL_APB_BASE 0xffa60000
16 #define FW_DDR_CON_REG 0x80
17
18 #define USB_HOST_PRIORITY_REG 0xfe810008
19 #define USB_OTG_PRIORITY_REG 0xfe810088
20 #define DECOM_PRIORITY_REG 0xfe820088
21 #define DMA_PRIORITY_REG 0xfe820108
22 #define MCU_DM_PRIORITY_REG 0xfe820188
23 #define MCU_IM_PRIORITY_REG 0xfe820208
24 #define A7_PRIORITY_REG 0xfe830008
25 #define GMAC_PRIORITY_REG 0xfe840008
26 #define NPU_PRIORITY_REG 0xfe850008
27 #define EMMC_PRIORITY_REG 0xfe860008
28 #define NANDC_PRIORITY_REG 0xfe860088
29 #define SFC_PRIORITY_REG 0xfe860208
30 #define SDMMC_PRIORITY_REG 0xfe868008
31 #define SDIO_PRIORITY_REG 0xfe86c008
32 #define VEPU_RD0_PRIORITY_REG 0xfe870008
33 #define VEPU_RD1_PRIORITY_REG 0xfe870088
34 #define VEPU_WR_PRIORITY_REG 0xfe870108
35 #define ISPP_M0_PRIORITY_REG 0xfe880008
36 #define ISPP_M1_PRIORITY_REG 0xfe880088
37 #define ISP_PRIORITY_REG 0xfe890008
38 #define CIF_LITE_PRIORITY_REG 0xfe890088
39 #define CIF_PRIORITY_REG 0xfe890108
40 #define IEP_PRIORITY_REG 0xfe8a0008
41 #define RGA_RD_PRIORITY_REG 0xfe8a0088
42 #define RGA_WR_PRIORITY_REG 0xfe8a0108
43 #define VOP_PRIORITY_REG 0xfe8a0188
44 #define VDPU_PRIORITY_REG 0xfe8b0008
45 #define JPEG_PRIORITY_REG 0xfe8c0008
46 #define CRYPTO_PRIORITY_REG 0xfe8d0008
47 /* external priority register */
48 #define ISPP_M0_PRIORITY_EX_REG 0xfe880018
49 #define ISPP_M1_PRIORITY_EX_REG 0xfe880098
50 #define ISP_PRIORITY_EX_REG 0xfe890018
51 #define CIF_LT_PRIORITY_EX_REG 0xfe890098
52 #define CIF_PRIORITY_EX_REG 0xfe890118
53 #define VOP_PRIORITY_EX_REG 0xfe8a0198
54 #define VDPU_PRIORITY_EX_REG 0xfe8b0018
55
56 #define PMU_BASE_ADDR 0xff3e0000
57
58 #define PMU_BUS_IDLE_SFTCON(n) (0xc0 + (n) * 4)
59 #define PMU_BUS_IDLE_ACK (0xd0)
60 #define PMU_BUS_IDLE_ST (0xd8)
61 #define PMU_NOC_AUTO_CON0 (0xe0)
62 #define PMU_NOC_AUTO_CON1 (0xe4)
63 #define PMU_PWR_DWN_ST (0x108)
64 #define PMU_PWR_GATE_SFTCON (0x110)
65
66 #define PMU_BUS_IDLE_NPU BIT(18)
67 #define PMU_BUS_IDLE_VEPU BIT(9)
68
69 #define CRU_BASE 0xFF490000
70 #define CRU_CLKSEL_CON02 0x108
71 #define CRU_CLKSEL_CON03 0x10c
72 #define CRU_CLKSEL_CON27 0x16c
73 #define CRU_CLKSEL_CON31 0x17c
74 #define CRU_CLKSEL_CON33 0x184
75 #define CRU_CLKSEL_CON40 0x1a0
76 #define CRU_CLKSEL_CON49 0x1c4
77 #define CRU_CLKSEL_CON50 0x1c8
78 #define CRU_CLKSEL_CON51 0x1cc
79 #define CRU_CLKSEL_CON54 0x1d8
80 #define CRU_CLKSEL_CON61 0x1f4
81 #define CRU_CLKSEL_CON63 0x1fc
82 #define CRU_CLKSEL_CON65 0x204
83 #define CRU_CLKSEL_CON67 0x20c
84 #define CRU_CLKSEL_CON68 0x210
85 #define CRU_CLKSEL_CON69 0x214
86 #define CRU_SOFTRST_CON02 0x308
87
88 #define CRU_PMU_BASE 0xFF480000
89 #define CRU_PMU_GPLL_CON0 0x10
90 #define CRU_PMU_GPLL_CON1 0x14
91
92 #define GRF_BASE 0xFE000000
93 #define GRF_SOC_CON2 0x008
94 #define PMUGRF_BASE 0xFE020000
95 #define SGRF_BASE 0xFE0A0000
96 #define SGRF_CON_SCR1_BOOT_ADDR 0x0b0
97 #define SGRF_SOC_CON3 0x00c
98 #define CRU_SOFTRST_CON11 0xFF49032C
99 #define PMUGRF_SOC_CON1 0xFE020104
100 #define PMUGRF_RSTFUNC_STATUS 0xFE020230
101 #define PMUGRF_RSTFUNC_CLR 0xFE020234
102 #define WDT_RESET_SRC BIT(1)
103 #define WDT_RESET_SRC_CLR BIT(1)
104 #define GRF_IOFUNC_CON3 0xFF01026C
105 #define GRF1_GPIO0D_P 0xFE010104
106 #define OTP_NS_BASE 0xFF5C0000
107 #define OTP_S_BASE 0xFF5D0000
108 #define OTP_NVM_TRWH 0x28
109
110 #define PMU_GRF_BASE 0xFE020000
111 #define PMUGRF_GPIO0B_IOMUX_H 0xc
112
113 enum {
114 GPIO1A7_SHIFT = 12,
115 GPIO1A7_MASK = GENMASK(14, 12),
116 GPIO1A7_GPIO = 0,
117 GPIO1A7_SDMMC0_D3,
118 GPIO1A7_UART3_TX_M1,
119 GPIO1A7_A7_JTAG_TMS_M0,
120 GPIO1A7_RISCV_JTAG_TMS,
121
122 GPIO1A6_SHIFT = 8,
123 GPIO1A6_MASK = GENMASK(10, 8),
124 GPIO1A6_GPIO = 0,
125 GPIO1A6_SDMMC0_D2,
126 GPIO1A6_UART3_RX_M1,
127 GPIO1A6_A7_JTAG_TCK_M0,
128 GPIO1A6_RISCV_JTAG_TCK,
129
130 GPIO1A5_SHIFT = 4,
131 GPIO1A5_MASK = GENMASK(6, 4),
132 GPIO1A5_GPIO = 0,
133 GPIO1A5_SDMMC0_D1,
134 GPIO1A5_TEST_CLK0_OUT,
135 GPIO1A5_UART2_TX_M0,
136 GPIO1A5_RISCV_JTAG_TRSTN,
137
138 GPIO1A4_SHIFT = 0,
139 GPIO1A4_MASK = GENMASK(2, 0),
140 GPIO1A4_GPIO = 0,
141 GPIO1A4_SDMMC0_D0,
142 GPIO1A4_TEST_CLK1_OUT,
143 GPIO1A4_UART2_RX_M0,
144
145 GPIO1C3_SHIFT = 12,
146 GPIO1C3_MASK = GENMASK(14, 12),
147 GPIO1C3_GPIO = 0,
148 GPIO1C3_UART0_TX,
149
150 GPIO1C2_SHIFT = 8,
151 GPIO1C2_MASK = GENMASK(10, 8),
152 GPIO1C2_GPIO = 0,
153 GPIO1C2_UART0_RX,
154
155 GPIO1D5_SHIFT = 4,
156 GPIO1D5_MASK = GENMASK(6, 4),
157 GPIO1D5_GPIO = 0,
158 GPIO1D5_SPI0_CS1N_M1,
159 GPIO1D5_I2S1_MCLK_M1,
160 GPIO1D5_UART4_TX_M2,
161
162 GPIO1D4_SHIFT = 0,
163 GPIO1D4_MASK = GENMASK(2, 0),
164 GPIO1D4_GPIO = 0,
165 GPIO1D4_RESERVED0,
166 GPIO1D4_RESERVED1,
167 GPIO1D4_UART4_RX_M2,
168
169 GPIO1D1_SHIFT = 4,
170 GPIO1D1_MASK = GENMASK(6, 4),
171 GPIO1D1_GPIO = 0,
172 GPIO1D1_RESERVED0,
173 GPIO1D1_SDMMC1_PWR,
174 GPIO1D1_RESERVED1,
175 GPIO1D1_I2C5_SDA_M2,
176 GPIO1D1_UART1_RX_M1,
177
178 GPIO1D0_SHIFT = 0,
179 GPIO1D0_MASK = GENMASK(2, 0),
180 GPIO1D0_GPIO = 0,
181 GPIO1D0_I2S2_MCLK_M0,
182 GPIO1D0_SDMMC1_DET,
183 GPIO1D0_SPI1_CS1N_M1,
184 GPIO1D0_I2C5_SCL_M2,
185 GPIO1D0_UART1_TX_M1,
186
187 GPIO2A7_SHIFT = 12,
188 GPIO2A7_MASK = GENMASK(14, 12),
189 GPIO2A7_GPIO = 0,
190 GPIO2A7_LCDC_D3,
191 GPIO2A7_I2S2_SDO_M1,
192 GPIO2A7_RESERVED,
193 GPIO2A7_UART4_RX_M1,
194 GPIO2A7_PWM4_M1,
195 GPIO2A7_SPI0_CS0N_M2,
196
197 GPIO2A6_SHIFT = 8,
198 GPIO2A6_MASK = GENMASK(10, 8),
199 GPIO2A6_GPIO = 0,
200 GPIO2A6_LCDC_D2,
201 GPIO2A6_RGMII_COL_M1,
202 GPIO2A6_CIF_D2_M1,
203 GPIO2A6_UART4_TX_M1,
204 GPIO2A6_PWM5_M1,
205
206 GPIO2A1_SHIFT = 4,
207 GPIO2A1_MASK = GENMASK(6, 4),
208 GPIO2A1_GPIO = 0,
209 GPIO2A1_SPI0_CLK_M1,
210 GPIO2A1_I2S1_SDO_M1,
211 GPIO2A1_UART5_RX_M2,
212
213 GPIO2A0_SHIFT = 0,
214 GPIO2A0_MASK = GENMASK(2, 0),
215 GPIO2A0_GPIO = 0,
216 GPIO2A0_SPI0_CS0N_M1,
217 GPIO2A0_I2S1_SDI_M1,
218 GPIO2A0_UART5_TX_M2,
219
220 GPIO2B1_SHIFT = 4,
221 GPIO2B1_MASK = GENMASK(6, 4),
222 GPIO2B1_GPIO = 0,
223 GPIO2B1_LCDC_D5,
224 GPIO2B1_I2S2_SCLK_M1,
225 GPIO2B1_RESERVED,
226 GPIO2B1_UART5_RX_M1,
227 GPIO2B1_PWM2_M1,
228 GPIO2B1_SPI0_MISO_M2,
229
230 GPIO2B0_SHIFT = 0,
231 GPIO2B0_MASK = GENMASK(2, 0),
232 GPIO2B0_GPIO = 0,
233 GPIO2B0_LCDC_D4,
234 GPIO2B0_I2S2_SDI_M1,
235 GPIO2B0_RESERVED,
236 GPIO2B0_UART5_TX_M1,
237 GPIO2B0_PWM3_IR_M1,
238 GPIO2B0_SPI0_MOSI_M2,
239
240 GPIO3A7_SHIFT = 12,
241 GPIO3A7_MASK = GENMASK(14, 12),
242 GPIO3A7_GPIO = 0,
243 GPIO3A7_CIF_D3_M0,
244 GPIO3A7_RGMII_RXD2_M0,
245 GPIO3A7_I2S0_SDI0_M1,
246 GPIO3A7_UART5_RX_M0,
247 GPIO3A7_CAN_TXD_M1,
248 GPIO3A7_PWM11_IR_M0,
249
250 GPIO3A6_SHIFT = 8,
251 GPIO3A6_MASK = GENMASK(10, 8),
252 GPIO3A6_GPIO = 0,
253 GPIO3A6_CIF_D2_M0,
254 GPIO3A6_RGMII_COL_M0,
255 GPIO3A6_I2S0_SDO0_M1,
256 GPIO3A6_UART5_TX_M0,
257 GPIO3A6_CAN_RXD_M1,
258 GPIO3A6_PWM10_M0,
259
260 GPIO3A5_SHIFT = 4,
261 GPIO3A5_MASK = GENMASK(6, 4),
262 GPIO3A5_GPIO = 0,
263 GPIO3A5_CIF_D1_M0,
264 GPIO3A5_RGMII_CRS_M0,
265 GPIO3A5_I2S0_LRCK_TX_M1,
266 GPIO3A5_UART4_RX_M0,
267 GPIO3A5_I2C3_SDA_M0,
268 GPIO3A5_PWM9_M0,
269
270 GPIO3A4_SHIFT = 0,
271 GPIO3A4_MASK = GENMASK(2, 0),
272 GPIO3A4_GPIO = 0,
273 GPIO3A4_CIF_D0_M0,
274 GPIO3A4_RESERVED,
275 GPIO3A4_I2S0_SCLK_TX_M1,
276 GPIO3A4_UART4_TX_M0,
277 GPIO3A4_I2C3_SCL_M0,
278 GPIO3A4_PWM8_M0,
279
280 GPIO3A3_SHIFT = 12,
281 GPIO3A3_MASK = GENMASK(14, 12),
282 GPIO3A3_GPIO = 0,
283 GPIO3A3_UART2_RX_M1,
284 GPIO3A3_A7_JTAG_TMS_M1,
285
286 GPIO3A2_SHIFT = 8,
287 GPIO3A2_MASK = GENMASK(10, 8),
288 GPIO3A2_GPIO = 0,
289 GPIO3A2_UART2_TX_M1,
290 GPIO3A2_A7_JTAG_TCK_M1,
291
292 GPIO3A1_SHIFT = 4,
293 GPIO3A1_MASK = GENMASK(6, 4),
294 GPIO3A1_GPIO = 0,
295 GPIO3A1_RESERVED0,
296 GPIO3A1_RESERVED1,
297 GPIO3A1_CAN_TXD_M0,
298 GPIO3A1_UART3_RX_M2,
299 GPIO3A1_PWM6_M1,
300 GPIO3A1_RESERVED2,
301 GPIO3A1_I2C4_SDA_M0,
302
303 GPIO3A0_SHIFT = 0,
304 GPIO3A0_MASK = GENMASK(2, 0),
305 GPIO3A0_GPIO = 0,
306 GPIO3A0_RESERVED0,
307 GPIO3A0_RESERVED1,
308 GPIO3A0_CAN_RXD_M0,
309 GPIO3A0_UART3_TX_M2,
310 GPIO3A0_PWM7_IR_M1,
311 GPIO3A0_SPI1_CS1N_M2,
312 GPIO3A0_I2C4_SCL_M0,
313
314 GPIO3C7_SHIFT = 12,
315 GPIO3C7_MASK = GENMASK(14, 12),
316 GPIO3C7_GPIO = 0,
317 GPIO3C7_CIF_HSYNC_M0,
318 GPIO3C7_RGMII_RXCLK_M0,
319 GPIO3C7_RESERVED,
320 GPIO3C7_UART3_RX_M0,
321
322 GPIO3C6_SHIFT = 8,
323 GPIO3C6_MASK = GENMASK(10, 0),
324 GPIO3C6_GPIO = 0,
325 GPIO3C6_CIF_CLKOUT_M0,
326 GPIO3C6_RGMII_TXCLK_M0,
327 GPIO3C6_RESERVED,
328 GPIO3C6_UART3_TX_M0,
329
330 UART2_IO_SEL_SHIFT = 8,
331 UART2_IO_SEL_MASK = GENMASK(8, 8),
332 UART2_IO_SEL_M0 = 0,
333 UART2_IO_SEL_M1,
334
335 UART3_IO_SEL_SHIFT = 10,
336 UART3_IO_SEL_MASK = GENMASK(11, 10),
337 UART3_IO_SEL_M0 = 0,
338 UART3_IO_SEL_M1,
339 UART3_IO_SEL_M2,
340
341 UART4_IO_SEL_SHIFT = 12,
342 UART4_IO_SEL_MASK = GENMASK(13, 12),
343 UART4_IO_SEL_M0 = 0,
344 UART4_IO_SEL_M1,
345 UART4_IO_SEL_M2,
346
347 UART5_IO_SEL_SHIFT = 14,
348 UART5_IO_SEL_MASK = GENMASK(15, 14),
349 UART5_IO_SEL_M0 = 0,
350 UART5_IO_SEL_M1,
351 UART5_IO_SEL_M2,
352 };
353
354 enum {
355 UART1_IO_SEL_SHIFT = 2,
356 UART1_IO_SEL_MASK = GENMASK(2, 2),
357 UART1_IO_SEL_M0 = 0,
358 UART1_IO_SEL_M1,
359
360 GPIO0B7_SHIFT = 12,
361 GPIO0B7_MASK = GENMASK(14, 12),
362 GPIO0B7_GPIO = 0,
363 GPIO0B7_RESERVED,
364 GPIO0B7_UART1_RX_M0,
365 GPIO0B7_PWM1_M0,
366
367 GPIO0B6_SHIFT = 8,
368 GPIO0B6_MASK = GENMASK(10, 8),
369 GPIO0B6_GPIO = 0,
370 GPIO0B6_RESERVED,
371 GPIO0B6_UART1_TX_M0,
372 GPIO0B6_PWM0_M0,
373 };
374
board_debug_uart_init(void)375 void board_debug_uart_init(void)
376 {
377 #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff560000)
378 static struct rv1126_grf * const grf = (void *)GRF_BASE;
379
380 /* UART0 Switch iomux */
381 rk_clrsetreg(&grf->gpio1c_iomux_l,
382 GPIO1C3_MASK | GPIO1C2_MASK,
383 GPIO1C3_UART0_TX << GPIO1C3_SHIFT |
384 GPIO1C2_UART0_RX << GPIO1C2_SHIFT);
385
386 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff410000)
387 static struct rv1126_pmugrf * const pmugrf = (void *)PMUGRF_BASE;
388 static struct rv1126_grf * const grf = (void *)GRF_BASE;
389 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
390 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
391 /* UART1 M0 */
392 rk_clrsetreg(&pmugrf->soc_con[6], UART1_IO_SEL_MASK,
393 UART1_IO_SEL_M0 << UART1_IO_SEL_SHIFT);
394
395 /* Switch iomux */
396 rk_clrsetreg(&pmugrf->gpio0b_iomux_h,
397 GPIO0B7_MASK | GPIO0B6_MASK,
398 GPIO0B7_UART1_RX_M0 << GPIO0B7_SHIFT |
399 GPIO0B6_UART1_TX_M0 << GPIO0B6_SHIFT);
400 #else
401 /* UART1 M1 */
402 rk_clrsetreg(&pmugrf->soc_con[6], UART1_IO_SEL_MASK,
403 UART1_IO_SEL_M1 << UART1_IO_SEL_SHIFT);
404
405 /* Switch iomux */
406 rk_clrsetreg(&grf->gpio1d_iomux_l,
407 GPIO1D1_MASK | GPIO1D0_MASK,
408 GPIO1D1_UART1_RX_M1 << GPIO1D1_SHIFT |
409 GPIO1D0_UART1_TX_M1 << GPIO1D0_SHIFT);
410 #endif
411
412 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff570000)
413 static struct rv1126_grf * const grf = (void *)GRF_BASE;
414 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
415 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
416 /* Enable early UART2 channel m0 on the rv1126 */
417 rk_clrsetreg(&grf->iofunc_con2, UART2_IO_SEL_MASK,
418 UART2_IO_SEL_M0 << UART2_IO_SEL_SHIFT);
419
420 /* Switch iomux */
421 rk_clrsetreg(&grf->gpio1a_iomux_h,
422 GPIO1A5_MASK | GPIO1A4_MASK,
423 GPIO1A5_UART2_TX_M0 << GPIO1A5_SHIFT |
424 GPIO1A4_UART2_RX_M0 << GPIO1A4_SHIFT);
425 #else
426 /* Enable early UART2 channel m1 on the rv1126 */
427 rk_clrsetreg(&grf->iofunc_con2, UART2_IO_SEL_MASK,
428 UART2_IO_SEL_M1 << UART2_IO_SEL_SHIFT);
429
430 /* Switch iomux */
431 rk_clrsetreg(&grf->gpio3a_iomux_l,
432 GPIO3A3_MASK | GPIO3A2_MASK,
433 GPIO3A3_UART2_RX_M1 << GPIO3A3_SHIFT |
434 GPIO3A2_UART2_TX_M1 << GPIO3A2_SHIFT);
435 #endif
436
437 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff580000)
438 static struct rv1126_grf * const grf = (void *)GRF_BASE;
439 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
440 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
441 /* UART3 m0*/
442 rk_clrsetreg(&grf->iofunc_con2, UART3_IO_SEL_MASK,
443 UART3_IO_SEL_M0 << UART3_IO_SEL_SHIFT);
444
445 /* Switch iomux */
446 rk_clrsetreg(&grf->gpio3c_iomux_h,
447 GPIO3C7_MASK | GPIO3C6_MASK,
448 GPIO3C7_UART3_RX_M0 << GPIO3C7_SHIFT |
449 GPIO3C6_UART3_TX_M0 << GPIO3C6_SHIFT);
450 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
451 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
452 /* UART3 m1*/
453 rk_clrsetreg(&grf->iofunc_con2, UART3_IO_SEL_MASK,
454 UART3_IO_SEL_M1 << UART3_IO_SEL_SHIFT);
455
456 /* Switch iomux */
457 rk_clrsetreg(&grf->gpio1a_iomux_h,
458 GPIO1A7_MASK | GPIO1A6_MASK,
459 GPIO1A7_UART3_TX_M1 << GPIO1A7_SHIFT |
460 GPIO1A6_UART3_RX_M1 << GPIO1A6_SHIFT);
461 #else
462 /* UART3 m2*/
463 rk_clrsetreg(&grf->iofunc_con2, UART3_IO_SEL_MASK,
464 UART3_IO_SEL_M2 << UART3_IO_SEL_SHIFT);
465
466 /* Switch iomux */
467 rk_clrsetreg(&grf->gpio3a_iomux_l,
468 GPIO3A1_MASK | GPIO3A0_MASK,
469 GPIO3A1_UART3_RX_M2 << GPIO3A1_SHIFT |
470 GPIO3A0_UART3_TX_M2 << GPIO3A0_SHIFT);
471 #endif
472
473 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff590000)
474 static struct rv1126_grf * const grf = (void *)GRF_BASE;
475 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
476 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
477 /* UART4 m0*/
478 rk_clrsetreg(&grf->iofunc_con2, UART4_IO_SEL_MASK,
479 UART4_IO_SEL_M0 << UART4_IO_SEL_SHIFT);
480
481 /* Switch iomux */
482 rk_clrsetreg(&grf->gpio3a_iomux_h,
483 GPIO3A5_MASK | GPIO3A4_MASK,
484 GPIO3A5_UART4_RX_M0 << GPIO3A5_SHIFT |
485 GPIO3A4_UART4_TX_M0 << GPIO3A4_SHIFT);
486 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
487 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
488 /* UART4 m1*/
489 rk_clrsetreg(&grf->iofunc_con2, UART4_IO_SEL_MASK,
490 UART4_IO_SEL_M1 << UART4_IO_SEL_SHIFT);
491
492 /* Switch iomux */
493 rk_clrsetreg(&grf->gpio2a_iomux_h,
494 GPIO2A7_MASK | GPIO2A6_MASK,
495 GPIO2A7_UART4_RX_M1 << GPIO2A7_SHIFT |
496 GPIO2A6_UART4_TX_M1 << GPIO2A6_SHIFT);
497 #else
498 /* UART4 m2*/
499 rk_clrsetreg(&grf->iofunc_con2, UART4_IO_SEL_MASK,
500 UART4_IO_SEL_M2 << UART4_IO_SEL_SHIFT);
501
502 /* Switch iomux */
503 rk_clrsetreg(&grf->gpio1d_iomux_h,
504 GPIO1D5_MASK | GPIO1D4_MASK,
505 GPIO1D5_UART4_TX_M2 << GPIO1D5_SHIFT |
506 GPIO1D4_UART4_RX_M2 << GPIO1D4_SHIFT);
507 #endif
508
509 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff5a0000)
510 static struct rv1126_grf * const grf = (void *)GRF_BASE;
511 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
512 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
513 /* UART5 m0*/
514 rk_clrsetreg(&grf->iofunc_con2, UART5_IO_SEL_MASK,
515 UART5_IO_SEL_M0 << UART5_IO_SEL_SHIFT);
516
517 /* Switch iomux */
518 rk_clrsetreg(&grf->gpio3a_iomux_h,
519 GPIO3A7_MASK | GPIO3A6_MASK,
520 GPIO3A7_UART5_RX_M0 << GPIO3A7_SHIFT |
521 GPIO3A6_UART5_TX_M0 << GPIO3A6_SHIFT);
522 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
523 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
524 /* UART5 m1*/
525 rk_clrsetreg(&grf->iofunc_con2, UART5_IO_SEL_MASK,
526 UART5_IO_SEL_M1 << UART5_IO_SEL_SHIFT);
527
528 /* Switch iomux */
529 rk_clrsetreg(&grf->gpio2b_iomux_l,
530 GPIO2B1_MASK | GPIO2B0_MASK,
531 GPIO2B1_UART5_RX_M1 << GPIO2B1_SHIFT |
532 GPIO2B0_UART5_TX_M1 << GPIO2B0_SHIFT);
533 #else
534 /* UART5 m2*/
535 rk_clrsetreg(&grf->iofunc_con2, UART5_IO_SEL_MASK,
536 UART5_IO_SEL_M2 << UART5_IO_SEL_SHIFT);
537
538 /* Switch iomux */
539 rk_clrsetreg(&grf->gpio2a_iomux_l,
540 GPIO2A1_MASK | GPIO2A0_MASK,
541 GPIO2A1_UART5_RX_M2 << GPIO2A1_SHIFT |
542 GPIO2A0_UART5_TX_M2 << GPIO2A0_SHIFT);
543 #endif
544 #endif /* CONFIG_DEBUG_UART_BASE && CONFIG_DEBUG_UART_BASE == ... */
545 }
546
547 #ifndef CONFIG_TPL_BUILD
arch_cpu_init(void)548 int arch_cpu_init(void)
549 {
550 /*
551 * CONFIG_DM_RAMDISK: for ramboot that without SPL.
552 */
553 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_DM_RAMDISK)
554 u32 pd_st, idle_st;
555 int delay;
556
557 /*
558 * Don't rely on CONFIG_DM_RAMDISK since it can be a default
559 * configuration after disk/part_rkram.c was introduced.
560 *
561 * This is compatible code.
562 */
563 #ifndef CONFIG_SPL_BUILD
564 if (!dm_ramdisk_is_enabled())
565 return 0;
566 #endif
567
568 /* write BOOT_WATCHDOG to boot mode register, if reset by wdt */
569 if (readl(PMUGRF_RSTFUNC_STATUS) & WDT_RESET_SRC) {
570 writel(BOOT_WATCHDOG, CONFIG_ROCKCHIP_BOOT_MODE_REG);
571 /* clear flag for reset by wdt trigger */
572 writel(WDT_RESET_SRC_CLR, PMUGRF_RSTFUNC_CLR);
573 }
574
575 #ifdef CONFIG_SPL_BUILD
576 /* set otp tRWH to 0x9 for stable read */
577 writel(0x9, OTP_NS_BASE + OTP_NVM_TRWH);
578 writel(0x9, OTP_S_BASE + OTP_NVM_TRWH);
579
580 /*
581 * Just set region 0 to unsecure.
582 * (Note: only secure-world can access this register)
583 */
584 writel(0, FIREWALL_APB_BASE + FW_DDR_CON_REG);
585 #endif
586
587 /* disable force jtag mux route to both group0 and group1 */
588 writel(0x00300000, GRF_IOFUNC_CON3);
589
590 /* make npu aclk and sclk less then 300MHz when reset */
591 writel(0x00ff0055, CRU_BASE + CRU_CLKSEL_CON65);
592 writel(0x00ff0055, CRU_BASE + CRU_CLKSEL_CON67);
593
594 /*
595 * When perform idle operation, corresponding clock can
596 * be opened or gated automatically.
597 */
598 writel(0xffffffff, PMU_BASE_ADDR + PMU_NOC_AUTO_CON0);
599 writel(0xffffffff, PMU_BASE_ADDR + PMU_NOC_AUTO_CON1);
600
601 #ifdef CONFIG_SPL_KERNEL_BOOT
602 /* Adjust the parameters of GPLL's VCO for reduce power*/
603 writel(0x00030000, CRU_PMU_BASE);
604 writel(0xffff1063, CRU_PMU_BASE + CRU_PMU_GPLL_CON0);
605 writel(0xffff1442, CRU_PMU_BASE + CRU_PMU_GPLL_CON1);
606 writel(0x00030001, CRU_PMU_BASE);
607
608 /* mux clocks to none-cpll */
609 writel(0x00ff0003, CRU_BASE + CRU_CLKSEL_CON02);
610 writel(0x00ff0005, CRU_BASE + CRU_CLKSEL_CON03);
611 writel(0xffff8383, CRU_BASE + CRU_CLKSEL_CON27);
612 writel(0x00ff0083, CRU_BASE + CRU_CLKSEL_CON31);
613 writel(0x00ff0083, CRU_BASE + CRU_CLKSEL_CON33);
614 writel(0xffff4385, CRU_BASE + CRU_CLKSEL_CON40);
615 writel(0x00ff0043, CRU_BASE + CRU_CLKSEL_CON49);
616 writel(0x00ff0003, CRU_BASE + CRU_CLKSEL_CON50);
617 writel(0x00ff0003, CRU_BASE + CRU_CLKSEL_CON51);
618 writel(0xff000300, CRU_BASE + CRU_CLKSEL_CON54);
619 writel(0xff008900, CRU_BASE + CRU_CLKSEL_CON61);
620 writel(0x00ff0089, CRU_BASE + CRU_CLKSEL_CON63);
621 writel(0x00ff0045, CRU_BASE + CRU_CLKSEL_CON68);
622 writel(0x00ff0043, CRU_BASE + CRU_CLKSEL_CON69);
623
624 #endif
625 /* enable all pd */
626 writel(0xffff0000, PMU_BASE_ADDR + PMU_PWR_GATE_SFTCON);
627 delay = 1000;
628 do {
629 udelay(1);
630 delay--;
631 } while (delay && readl(PMU_BASE_ADDR + PMU_PWR_DWN_ST));
632
633 /* release all idle request */
634 writel(0xffff0000, PMU_BASE_ADDR + PMU_BUS_IDLE_SFTCON(0));
635 writel(0xffff0000, PMU_BASE_ADDR + PMU_BUS_IDLE_SFTCON(1));
636
637 delay = 1000;
638 /* wait ack status */
639 do {
640 udelay(1);
641 delay--;
642 } while (delay && readl(PMU_BASE_ADDR + PMU_BUS_IDLE_ACK));
643
644 delay = 1000;
645 /* wait idle status */
646 do {
647 udelay(1);
648 delay--;
649 } while (delay && readl(PMU_BASE_ADDR + PMU_BUS_IDLE_ST));
650
651 pd_st = readl(PMU_BASE_ADDR + PMU_PWR_DWN_ST);
652 idle_st = readl(PMU_BASE_ADDR + PMU_BUS_IDLE_ST);
653
654 if (pd_st || idle_st) {
655 printf("PMU_PWR_DOWN_ST: 0x%08x\n", pd_st);
656 printf("PMU_BUS_IDLE_ST: 0x%08x\n", idle_st);
657
658 if (idle_st & PMU_BUS_IDLE_NPU)
659 printf("Failed to enable PD_NPU, please check VDD_NPU is supplied\n");
660
661 if (idle_st & PMU_BUS_IDLE_VEPU)
662 printf("Failed to enable PD_VEPU, please check VDD_VEPU is supplied\n");
663
664 hang();
665 }
666
667 writel(0x303, USB_HOST_PRIORITY_REG);
668 writel(0x303, USB_OTG_PRIORITY_REG);
669 writel(0x101, DECOM_PRIORITY_REG);
670 writel(0x303, DMA_PRIORITY_REG);
671 writel(0x101, MCU_DM_PRIORITY_REG);
672 writel(0x101, MCU_IM_PRIORITY_REG);
673 writel(0x101, A7_PRIORITY_REG);
674 writel(0x303, GMAC_PRIORITY_REG);
675 writel(0x101, NPU_PRIORITY_REG);
676 writel(0x303, EMMC_PRIORITY_REG);
677 writel(0x303, NANDC_PRIORITY_REG);
678 writel(0x303, SFC_PRIORITY_REG);
679 writel(0x303, SDMMC_PRIORITY_REG);
680 writel(0x303, SDIO_PRIORITY_REG);
681 writel(0x101, VEPU_RD0_PRIORITY_REG);
682 writel(0x101, VEPU_RD1_PRIORITY_REG);
683 writel(0x101, VEPU_WR_PRIORITY_REG);
684 writel(0x101, ISPP_M0_PRIORITY_REG);
685 writel(0x101, ISPP_M1_PRIORITY_REG);
686 writel(0x101, ISP_PRIORITY_REG);
687 writel(0x202, CIF_LITE_PRIORITY_REG);
688 writel(0x202, CIF_PRIORITY_REG);
689 writel(0x101, IEP_PRIORITY_REG);
690 writel(0x101, RGA_RD_PRIORITY_REG);
691 writel(0x101, RGA_WR_PRIORITY_REG);
692 writel(0x202, VOP_PRIORITY_REG);
693 writel(0x101, VDPU_PRIORITY_REG);
694 writel(0x101, JPEG_PRIORITY_REG);
695 writel(0x101, CRYPTO_PRIORITY_REG);
696 /* enable dynamic priority */
697 writel(0x1, ISP_PRIORITY_EX_REG);
698
699 /*
700 * Init the i2c0 iomux and use it to control electronic voltmeter
701 * to detect voltage.
702 */
703 #if defined(CONFIG_SPL_KERNEL_BOOT) && defined(CONFIG_SPL_DM_FUEL_GAUGE)
704 writel(0x00770011, PMU_GRF_BASE + PMUGRF_GPIO0B_IOMUX_H);
705 #endif
706
707 #elif defined(CONFIG_SUPPORT_USBPLUG)
708 /* Just set region 0 to unsecure */
709 writel(0, FIREWALL_APB_BASE + FW_DDR_CON_REG);
710
711 /* reset usbphy_otg usbphypor_otg */
712 writel(((0x1 << 6 | (1 << 8)) << 16) | (0x1 << 6) | (1 << 8), CRU_SOFTRST_CON11);
713 udelay(50);
714 writel(((0x1 << 6 | (1 << 8)) << 16) | (0), CRU_SOFTRST_CON11);
715
716 /* hold pmugrf's io reset */
717 writel(0x1 << 7 | 1 << 23, PMUGRF_SOC_CON1);
718
719 #else /* U-Boot */
720 /* uboot: config iomux for sd boot upgrade firmware */
721 #if defined(CONFIG_ROCKCHIP_SFC_IOMUX)
722 static struct rv1126_grf * const grf = (void *)GRF_BASE;
723
724 writel(0x0F0F0303, &grf->gpio0d_iomux_h);
725 writel(0xFFFF3333, &grf->gpio1a_iomux_l);
726 #elif defined(CONFIG_ROCKCHIP_EMMC_IOMUX)
727 static struct rv1126_grf * const grf = (void *)GRF_BASE;
728
729 writel(0xFFFF2222, &grf->gpio0c_iomux_h);
730 writel(0xFFFF2222, &grf->gpio0d_iomux_l);
731 writel(0xF0F02020, &grf->gpio0d_iomux_h);
732 #elif defined(CONFIG_ROCKCHIP_NAND_IOMUX)
733 static struct rv1126_grf * const grf = (void *)GRF_BASE;
734
735 writel(0xFFFF1111, &grf->gpio0c_iomux_h);
736 writel(0xFFFF1111, &grf->gpio0d_iomux_l);
737 writel(0xF0FF1011, &grf->gpio0d_iomux_h);
738 writel(0xFFFF1111, &grf->gpio1a_iomux_l);
739 #endif
740
741 #endif
742 #if defined(CONFIG_ROCKCHIP_SFC)
743 /* GPIO0_D6 pull down in default, pull up it for SPI Flash */
744 writel(((0x3 << 12) << 16) | (0x1 << 12), GRF1_GPIO0D_P);
745 #endif
746
747 return 0;
748 }
749 #endif
750
751 #ifdef CONFIG_SPL_BUILD
spl_fit_standalone_release(char * id,uintptr_t entry_point)752 int spl_fit_standalone_release(char *id, uintptr_t entry_point)
753 {
754 /*
755 * Fix mcu does not work probabilistically through reset the
756 * mcu debug module. If use the jtag debug, reset it.
757 */
758 writel(0x80008000, GRF_BASE + GRF_SOC_CON2);
759 /* Reset the scr1 */
760 writel(0x04000400, CRU_BASE + CRU_SOFTRST_CON02);
761 udelay(100);
762 /* set the scr1 addr */
763 writel(entry_point, SGRF_BASE + SGRF_CON_SCR1_BOOT_ADDR);
764 writel(0x00ff00bf, SGRF_BASE + SGRF_SOC_CON3);
765 udelay(10);
766 /* release the scr1 */
767 writel(0x04000000, CRU_BASE + CRU_SOFTRST_CON02);
768
769 return 0;
770 }
771 #endif
772