1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rockchip-ddr.h> 7#include <dt-bindings/memory/px30-dram.h> 8 9/ { 10 ddr3_params: ddr3-params { 11 /* version information */ 12 version = <0x101>; 13 expanded_version = <IGNORE_THIS>; 14 reserved = <IGNORE_THIS>; 15 /* freq info, freq_0 is final frequency, unit: MHz */ 16 freq_0 = <666>; 17 freq_1 = <194>; 18 freq_2 = <328>; 19 freq_3 = <666>; 20 freq_4 = <IGNORE_THIS>; 21 freq_5 = <IGNORE_THIS>; 22 /* power save setting */ 23 pd_idle = <13>; 24 sr_idle = <93>; 25 sr_mc_gate_idle = <0>; 26 srpd_lite_idle = <0>; 27 standby_idle = <0>; 28 pd_dis_freq = <1066>; 29 sr_dis_freq = <800>; 30 dram_dll_dis_freq = <300>; 31 phy_dll_dis_freq = <IGNORE_THIS>; 32 /* drv when odt on */ 33 phy_dq_drv_odten = <33>; 34 phy_ca_drv_odten = <33>; 35 phy_clk_drv_odten = <33>; 36 dram_dq_drv_odten = <34>; 37 /* drv when odt off */ 38 phy_dq_drv_odtoff = <33>; 39 phy_ca_drv_odtoff = <33>; 40 phy_clk_drv_odtoff = <33>; 41 dram_dq_drv_odtoff = <34>; 42 /* odt info */ 43 dram_odt = <120>; 44 phy_odt = <133>; 45 phy_odt_puup_en = <1>; 46 phy_odt_pudn_en = <1>; 47 /* odt enable freq */ 48 dram_dq_odt_en_freq = <333>; 49 phy_odt_en_freq = <333>; 50 /* slew rate when odt enable */ 51 phy_dq_sr_odten = <0xf>; 52 phy_ca_sr_odten = <0x3>; 53 phy_clk_sr_odten = <0x3>; 54 /* slew rate when odt disable */ 55 phy_dq_sr_odtoff = <0xf>; 56 phy_ca_sr_odtoff = <0x3>; 57 phy_clk_sr_odtoff = <0x3>; 58 /* ssmod setting*/ 59 ssmod_downspread = <0>; 60 ssmod_div = <0>; 61 ssmod_spread = <0>; 62 /* 2T mode */ 63 mode_2t = <IGNORE_THIS>; 64 /* speed bin */ 65 speed_bin = <DDR3_DEFAULT>; 66 /* dram extended temperature support */ 67 dram_ext_temp = <0>; 68 /* byte map */ 69 byte_map = <((0x2 << 6) | (0x3 << 4) | (0x0 << 2) | (0x1 << 0))>; 70 /* dq map */ 71 dq_map_cs0_dq_l = <0>; 72 dq_map_cs0_dq_h = <0>; 73 dq_map_cs1_dq_l = <0>; 74 dq_map_cs1_dq_h = <0>; 75 }; 76 77 ddr4_params: ddr4-params { 78 /* version information */ 79 version = <0x101>; 80 expanded_version = <IGNORE_THIS>; 81 reserved = <IGNORE_THIS>; 82 /* freq info, freq_0 is final frequency, unit: MHz */ 83 freq_0 = <666>; 84 freq_1 = <194>; 85 freq_2 = <328>; 86 freq_3 = <666>; 87 freq_4 = <IGNORE_THIS>; 88 freq_5 = <IGNORE_THIS>; 89 /* power save setting */ 90 pd_idle = <13>; 91 sr_idle = <93>; 92 sr_mc_gate_idle = <0>; 93 srpd_lite_idle = <0>; 94 standby_idle = <0>; 95 pd_dis_freq = <1066>; 96 sr_dis_freq = <800>; 97 dram_dll_dis_freq = <500>; 98 phy_dll_dis_freq = <IGNORE_THIS>; 99 /* drv when odt on */ 100 phy_dq_drv_odten = <33>; 101 phy_ca_drv_odten = <33>; 102 phy_clk_drv_odten = <33>; 103 dram_dq_drv_odten = <34>; 104 /* drv when odt off */ 105 phy_dq_drv_odtoff = <33>; 106 phy_ca_drv_odtoff = <33>; 107 phy_clk_drv_odtoff = <33>; 108 dram_dq_drv_odtoff = <34>; 109 /* odt info */ 110 dram_odt = <120>; 111 phy_odt = <121>; 112 phy_odt_puup_en = <1>; 113 phy_odt_pudn_en = <1>; 114 /* odt enable freq */ 115 dram_dq_odt_en_freq = <500>; 116 phy_odt_en_freq = <500>; 117 /* slew rate when odt enable */ 118 phy_dq_sr_odten = <0xe>; 119 phy_ca_sr_odten = <0x1>; 120 phy_clk_sr_odten = <0x1>; 121 /* slew rate when odt disable */ 122 phy_dq_sr_odtoff = <0xe>; 123 phy_ca_sr_odtoff = <0x1>; 124 phy_clk_sr_odtoff = <0x1>; 125 /* ssmod setting*/ 126 ssmod_downspread = <0>; 127 ssmod_div = <0>; 128 ssmod_spread = <0>; 129 /* 2T mode */ 130 mode_2t = <IGNORE_THIS>; 131 /* speed bin */ 132 speed_bin = <DDR4_DEFAULT>; 133 /* dram extended temperature support */ 134 dram_ext_temp = <0>; 135 /* byte map */ 136 byte_map = <((0x2 << 6) | (0x3 << 4) | (0x0 << 2) | (0x1 << 0))>; 137 /* dq map */ 138 dq_map_cs0_dq_l = <(((3 << 0 | 0 << 2 | 3 << 4 | 1 << 6) << 0) | \ 139 ((2 << 0 | 0 << 2 | 2 << 4 | 1 << 6) << 8) | \ 140 ((3 << 0 | 2 << 2 | 1 << 4 | 2 << 6) << 16) | \ 141 ((3 << 0 | 0 << 2 | 1 << 4 | 0 << 6) << 24))>; 142 dq_map_cs0_dq_h = <(((2 << 0 | 0 << 2 | 0 << 4 | 1 << 6) << 0) | \ 143 ((3 << 0 | 3 << 2 | 2 << 4 | 1 << 6) << 8) | \ 144 ((1 << 0 | 3 << 2 | 2 << 4 | 0 << 6) << 16) | \ 145 ((3 << 0 | 1 << 2 | 2 << 4 | 0 << 6) << 24))>; 146 dq_map_cs1_dq_l = <(((2 << 0 | 1 << 2 | 2 << 4 | 0 << 6) << 0) | \ 147 ((3 << 0 | 1 << 2 | 3 << 4 | 0 << 6) << 8) | \ 148 ((2 << 0 | 3 << 2 | 0 << 4 | 3 << 6) << 16) | \ 149 ((2 << 0 | 1 << 2 | 0 << 4 | 1 << 6) << 24))>; 150 dq_map_cs1_dq_h = <(((3 << 0 | 1 << 2 | 1 << 4 | 0 << 6) << 0) | \ 151 ((2 << 0 | 2 << 2 | 3 << 4 | 0 << 6) << 8) | \ 152 ((0 << 0 | 2 << 2 | 3 << 4 | 1 << 6) << 16) | \ 153 ((2 << 0 | 0 << 2 | 3 << 4 | 1 << 6) << 24))>; 154 }; 155 156 lpddr2_params: lpddr2-params { 157 /* version information */ 158 version = <0x101>; 159 expanded_version = <IGNORE_THIS>; 160 reserved = <IGNORE_THIS>; 161 /* freq info, freq_0 is final frequency, unit: MHz */ 162 freq_0 = <528>; 163 freq_1 = <194>; 164 freq_2 = <328>; 165 freq_3 = <528>; 166 freq_4 = <IGNORE_THIS>; 167 freq_5 = <IGNORE_THIS>; 168 /* power save setting */ 169 pd_idle = <13>; 170 sr_idle = <93>; 171 sr_mc_gate_idle = <0>; 172 srpd_lite_idle = <0>; 173 standby_idle = <0>; 174 pd_dis_freq = <1066>; 175 sr_dis_freq = <800>; 176 dram_dll_dis_freq = <IGNORE_THIS>; 177 phy_dll_dis_freq = <IGNORE_THIS>; 178 /* drv when odt on */ 179 phy_dq_drv_odten = <33>; 180 phy_ca_drv_odten = <33>; 181 phy_clk_drv_odten = <33>; 182 dram_dq_drv_odten = <34>; 183 /* drv when odt off */ 184 phy_dq_drv_odtoff = <33>; 185 phy_ca_drv_odtoff = <33>; 186 phy_clk_drv_odtoff = <33>; 187 dram_dq_drv_odtoff = <34>; 188 /* odt info */ 189 dram_odt = <0>; 190 phy_odt = <0>; 191 phy_odt_puup_en = <0>; 192 phy_odt_pudn_en = <0>; 193 /* odt enable freq */ 194 dram_dq_odt_en_freq = <625>; 195 phy_odt_en_freq = <625>; 196 /* slew rate when odt enable */ 197 phy_dq_sr_odten = <0xe>; 198 phy_ca_sr_odten = <0x1>; 199 phy_clk_sr_odten = <0x1>; 200 /* slew rate when odt disable */ 201 phy_dq_sr_odtoff = <0xe>; 202 phy_ca_sr_odtoff = <0x1>; 203 phy_clk_sr_odtoff = <0x1>; 204 /* ssmod setting*/ 205 ssmod_downspread = <0>; 206 ssmod_div = <0>; 207 ssmod_spread = <0>; 208 /* 2T mode */ 209 mode_2t = <IGNORE_THIS>; 210 /* speed bin */ 211 speed_bin = <IGNORE_THIS>; 212 /* dram extended temperature support */ 213 dram_ext_temp = <0>; 214 /* byte map */ 215 byte_map = <((0x3 << 6) | (0x2 << 4) | (0x1 << 2) | (0x0 << 0))>; 216 /* dq map */ 217 dq_map_cs0_dq_l = <0>; 218 dq_map_cs0_dq_h = <0>; 219 dq_map_cs1_dq_l = <0>; 220 dq_map_cs1_dq_h = <0>; 221 }; 222 223 lpddr3_params: lpddr3-params { 224 /* version information */ 225 version = <0x101>; 226 expanded_version = <IGNORE_THIS>; 227 reserved = <IGNORE_THIS>; 228 /* freq info, freq_0 is final frequency, unit: MHz */ 229 freq_0 = <666>; 230 freq_1 = <194>; 231 freq_2 = <328>; 232 freq_3 = <666>; 233 freq_4 = <IGNORE_THIS>; 234 freq_5 = <IGNORE_THIS>; 235 /* power save setting */ 236 pd_idle = <13>; 237 sr_idle = <93>; 238 sr_mc_gate_idle = <0>; 239 srpd_lite_idle = <0>; 240 standby_idle = <0>; 241 pd_dis_freq = <1066>; 242 sr_dis_freq = <800>; 243 dram_dll_dis_freq = <IGNORE_THIS>; 244 phy_dll_dis_freq = <IGNORE_THIS>; 245 /* drv when odt on */ 246 phy_dq_drv_odten = <33>; 247 phy_ca_drv_odten = <33>; 248 phy_clk_drv_odten = <33>; 249 dram_dq_drv_odten = <34>; 250 /* drv when odt off */ 251 phy_dq_drv_odtoff = <33>; 252 phy_ca_drv_odtoff = <33>; 253 phy_clk_drv_odtoff = <33>; 254 dram_dq_drv_odtoff = <34>; 255 /* odt info */ 256 dram_odt = <240>; 257 phy_odt = <121>; 258 phy_odt_puup_en = <1>; 259 phy_odt_pudn_en = <1>; 260 /* odt enable freq */ 261 dram_dq_odt_en_freq = <333>; 262 phy_odt_en_freq = <333>; 263 /* slew rate when odt enable */ 264 phy_dq_sr_odten = <0x0>; 265 phy_ca_sr_odten = <0x0>; 266 phy_clk_sr_odten = <0x0>; 267 /* slew rate when odt disable */ 268 phy_dq_sr_odtoff = <0x0>; 269 phy_ca_sr_odtoff = <0x0>; 270 phy_clk_sr_odtoff = <0x0>; 271 /* ssmod setting*/ 272 ssmod_downspread = <0>; 273 ssmod_div = <0>; 274 ssmod_spread = <0>; 275 /* 2T mode */ 276 mode_2t = <IGNORE_THIS>; 277 /* speed bin */ 278 speed_bin = <IGNORE_THIS>; 279 /* dram extended temperature support */ 280 dram_ext_temp = <0>; 281 /* byte map */ 282 byte_map = <((0x3 << 6) | (0x2 << 4) | (0x1 << 2) | (0x0 << 0))>; 283 /* dq map */ 284 dq_map_cs0_dq_l = <0>; 285 dq_map_cs0_dq_h = <0>; 286 dq_map_cs1_dq_l = <0>; 287 dq_map_cs1_dq_h = <0>; 288 }; 289 290 lpddr4_params: lpddr4-params { 291 /* version information */ 292 version = <0x101>; 293 expanded_version = <IGNORE_THIS>; 294 reserved = <IGNORE_THIS>; 295 /* freq info, freq_0 is final frequency, unit: MHz */ 296 freq_0 = <666>; 297 freq_1 = <194>; 298 freq_2 = <328>; 299 freq_3 = <666>; 300 freq_4 = <IGNORE_THIS>; 301 freq_5 = <IGNORE_THIS>; 302 /* power save setting */ 303 pd_idle = <13>; 304 sr_idle = <93>; 305 sr_mc_gate_idle = <0>; 306 srpd_lite_idle = <0>; 307 standby_idle = <0>; 308 pd_dis_freq = <1066>; 309 sr_dis_freq = <800>; 310 dram_dll_dis_freq = <IGNORE_THIS>; 311 phy_dll_dis_freq = <IGNORE_THIS>; 312 /* drv when odt on */ 313 phy_dq_drv_odten = <44>; 314 phy_ca_drv_odten = <38>; 315 phy_clk_drv_odten = <47>; 316 dram_dq_drv_odten = <40>; 317 /* drv when odt off */ 318 phy_dq_drv_odtoff = <44>; 319 phy_ca_drv_odtoff = <38>; 320 phy_clk_drv_odtoff = <47>; 321 dram_dq_drv_odtoff = <40>; 322 /* odt info */ 323 dram_odt = <60>; 324 phy_odt = <80>; 325 phy_odt_puup_en = <IGNORE_THIS>; 326 phy_odt_pudn_en = <IGNORE_THIS>; 327 /* odt enable freq */ 328 dram_dq_odt_en_freq = <800>; 329 phy_odt_en_freq = <800>; 330 /* slew rate when odt enable */ 331 phy_dq_sr_odten = <0x7>; 332 phy_ca_sr_odten = <0x1>; 333 phy_clk_sr_odten = <0x1>; 334 /* slew rate when odt disable */ 335 phy_dq_sr_odtoff = <0x7>; 336 phy_ca_sr_odtoff = <0x1>; 337 phy_clk_sr_odtoff = <0x1>; 338 /* ssmod setting*/ 339 ssmod_downspread = <0>; 340 ssmod_div = <0>; 341 ssmod_spread = <0>; 342 /* 2T mode */ 343 mode_2t = <IGNORE_THIS>; 344 /* speed bin */ 345 speed_bin = <IGNORE_THIS>; 346 /* dram extended temperature support */ 347 dram_ext_temp = <0>; 348 /* byte map */ 349 byte_map = <((0x3 << 6) | (0x2 << 4) | (0x1 << 2) | (0x0 << 0))>; 350 /* dq map */ 351 dq_map_cs0_dq_l = <0>; 352 dq_map_cs0_dq_h = <0>; 353 dq_map_cs1_dq_l = <0>; 354 dq_map_cs1_dq_h = <0>; 355 /* lp4 odt info */ 356 lp4_ca_odt = <120>; 357 lp4_drv_pu_cal_odten = <LP4_VDDQ_2_5>; 358 lp4_drv_pu_cal_odtoff = <LP4_VDDQ_2_5>; 359 phy_lp4_drv_pulldown_en_odten = <0>; 360 phy_lp4_drv_pulldown_en_odtoff = <0>; 361 /* lp4 odt enable freq */ 362 lp4_ca_odt_en_freq = <800>; 363 /* lp4 cs drv info and ca odt info */ 364 phy_lp4_cs_drv_odten = <0>; 365 phy_lp4_cs_drv_odtoff = <0>; 366 lp4_odte_ck_en = <1>; 367 lp4_odte_cs_en = <1>; 368 lp4_odtd_ca_en = <0>; 369 /* lp4 vref info when odt enable */ 370 phy_lp4_dq_vref_odten = <200>; 371 lp4_dq_vref_odten = <276>; 372 lp4_ca_vref_odten = <380>; 373 /* lp4 vref info when odt disable */ 374 phy_lp4_dq_vref_odtoff = <420>; 375 lp4_dq_vref_odtoff = <420>; 376 lp4_ca_vref_odtoff = <420>; 377 }; 378}; 379 380