1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * PS3 GPU declarations.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright 2009 Sony Corporation
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #ifndef _ASM_POWERPC_PS3GPU_H
9*4882a593Smuzhiyun #define _ASM_POWERPC_PS3GPU_H
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/mutex.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <asm/lv1call.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #define L1GPU_CONTEXT_ATTRIBUTE_DISPLAY_SYNC 0x101
17*4882a593Smuzhiyun #define L1GPU_CONTEXT_ATTRIBUTE_DISPLAY_FLIP 0x102
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #define L1GPU_CONTEXT_ATTRIBUTE_FB_SETUP 0x600
20*4882a593Smuzhiyun #define L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT 0x601
21*4882a593Smuzhiyun #define L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT_SYNC 0x602
22*4882a593Smuzhiyun #define L1GPU_CONTEXT_ATTRIBUTE_FB_CLOSE 0x603
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #define L1GPU_FB_BLIT_WAIT_FOR_COMPLETION (1ULL << 32)
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #define L1GPU_DISPLAY_SYNC_HSYNC 1
27*4882a593Smuzhiyun #define L1GPU_DISPLAY_SYNC_VSYNC 2
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun /* mutex synchronizing GPU accesses and video mode changes */
31*4882a593Smuzhiyun extern struct mutex ps3_gpu_mutex;
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun
lv1_gpu_display_sync(u64 context_handle,u64 head,u64 ddr_offset)34*4882a593Smuzhiyun static inline int lv1_gpu_display_sync(u64 context_handle, u64 head,
35*4882a593Smuzhiyun u64 ddr_offset)
36*4882a593Smuzhiyun {
37*4882a593Smuzhiyun return lv1_gpu_context_attribute(context_handle,
38*4882a593Smuzhiyun L1GPU_CONTEXT_ATTRIBUTE_DISPLAY_SYNC,
39*4882a593Smuzhiyun head, ddr_offset, 0, 0);
40*4882a593Smuzhiyun }
41*4882a593Smuzhiyun
lv1_gpu_display_flip(u64 context_handle,u64 head,u64 ddr_offset)42*4882a593Smuzhiyun static inline int lv1_gpu_display_flip(u64 context_handle, u64 head,
43*4882a593Smuzhiyun u64 ddr_offset)
44*4882a593Smuzhiyun {
45*4882a593Smuzhiyun return lv1_gpu_context_attribute(context_handle,
46*4882a593Smuzhiyun L1GPU_CONTEXT_ATTRIBUTE_DISPLAY_FLIP,
47*4882a593Smuzhiyun head, ddr_offset, 0, 0);
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun
lv1_gpu_fb_setup(u64 context_handle,u64 xdr_lpar,u64 xdr_size,u64 ioif_offset)50*4882a593Smuzhiyun static inline int lv1_gpu_fb_setup(u64 context_handle, u64 xdr_lpar,
51*4882a593Smuzhiyun u64 xdr_size, u64 ioif_offset)
52*4882a593Smuzhiyun {
53*4882a593Smuzhiyun return lv1_gpu_context_attribute(context_handle,
54*4882a593Smuzhiyun L1GPU_CONTEXT_ATTRIBUTE_FB_SETUP,
55*4882a593Smuzhiyun xdr_lpar, xdr_size, ioif_offset, 0);
56*4882a593Smuzhiyun }
57*4882a593Smuzhiyun
lv1_gpu_fb_blit(u64 context_handle,u64 ddr_offset,u64 ioif_offset,u64 sync_width,u64 pitch)58*4882a593Smuzhiyun static inline int lv1_gpu_fb_blit(u64 context_handle, u64 ddr_offset,
59*4882a593Smuzhiyun u64 ioif_offset, u64 sync_width, u64 pitch)
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun return lv1_gpu_context_attribute(context_handle,
62*4882a593Smuzhiyun L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT,
63*4882a593Smuzhiyun ddr_offset, ioif_offset, sync_width,
64*4882a593Smuzhiyun pitch);
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun
lv1_gpu_fb_close(u64 context_handle)67*4882a593Smuzhiyun static inline int lv1_gpu_fb_close(u64 context_handle)
68*4882a593Smuzhiyun {
69*4882a593Smuzhiyun return lv1_gpu_context_attribute(context_handle,
70*4882a593Smuzhiyun L1GPU_CONTEXT_ATTRIBUTE_FB_CLOSE, 0,
71*4882a593Smuzhiyun 0, 0, 0);
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun #endif /* _ASM_POWERPC_PS3GPU_H */
75