Home
last modified time | relevance | path

Searched +full:0 +full:x00400000 (Results 1 – 25 of 1017) sorted by relevance

12345678910>>...41

/OK3568_Linux_fs/kernel/drivers/gpu/drm/etnaviv/
H A Dcommon.xml.h7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
43 #define PIPE_ID_PIPE_3D 0x00000000
44 #define PIPE_ID_PIPE_2D 0x00000001
45 #define SYNC_RECIPIENT_FE 0x00000001
46 #define SYNC_RECIPIENT_RA 0x00000005
47 #define SYNC_RECIPIENT_PE 0x00000007
48 #define SYNC_RECIPIENT_DE 0x0000000b
49 #define SYNC_RECIPIENT_BLT 0x00000010
50 #define ENDIAN_MODE_NO_SWAP 0x00000000
[all …]
/OK3568_Linux_fs/u-boot/include/configs/
H A Drk3328_common.h18 #define CONFIG_SYS_TEXT_BASE 0x00200000
19 #define CONFIG_SYS_INIT_SP_ADDR 0x00400000
20 #define CONFIG_SYS_LOAD_ADDR 0x00800800
21 #define CONFIG_SPL_STACK 0x00400000
22 #define CONFIG_SPL_TEXT_BASE 0x00000000
23 #define CONFIG_SPL_MAX_SIZE 0x40000
24 #define CONFIG_SPL_BSS_START_ADDR 0x00400000
25 #define CONFIG_SPL_BSS_MAX_SIZE 0x2000
28 #define GICD_BASE 0xFF811000
29 #define GICC_BASE 0xFF812000
[all …]
H A Drk3399_common.h20 #define CONFIG_SYS_TEXT_BASE 0x00200000
21 #define CONFIG_SYS_INIT_SP_ADDR 0x00400000
22 #define CONFIG_SYS_LOAD_ADDR 0x00800800
23 #define CONFIG_SPL_STACK 0x00400000
24 #define CONFIG_SPL_TEXT_BASE 0x00000000
25 #define CONFIG_SPL_MAX_SIZE 0x40000
26 #define CONFIG_SPL_BSS_START_ADDR 0x00400000
27 #define CONFIG_SPL_BSS_MAX_SIZE 0x2000
30 #define GICD_BASE 0xFEE00000
31 #define GICR_BASE 0xFEF00000
[all …]
H A DMPC8560ADS.h25 * default CCARBAR is at 0xff700000
28 #define CONFIG_SYS_TEXT_BASE 0xfff80000
63 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
64 #define CONFIG_SYS_MEMTEST_END 0x00400000
66 #define CONFIG_SYS_CCSRBAR 0xe0000000
74 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
76 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
83 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
87 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
88 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002
[all …]
H A Dpx30_common.h20 #define CONFIG_SYS_TEXT_BASE 0x00200000
21 #define CONFIG_SYS_INIT_SP_ADDR 0x00400000
22 #define CONFIG_SYS_LOAD_ADDR 0x00800800
23 #define CONFIG_SPL_STACK 0x00400000
24 #define CONFIG_SPL_TEXT_BASE 0x00000000
25 #define CONFIG_SPL_MAX_SIZE 0x40000
26 #define CONFIG_SPL_BSS_START_ADDR 0x2000000
27 #define CONFIG_SPL_BSS_MAX_SIZE 0x2000
32 #define GICD_BASE 0xff131000
33 #define GICC_BASE 0xff132000
[all …]
/OK3568_Linux_fs/kernel/arch/sh/include/mach-se/mach/
H A Dse7343.h16 /* Area 0 */
17 #define PA_ROM 0x00000000 /* EPROM */
18 #define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte(Actually 2MB) */
19 #define PA_FROM 0x00400000 /* Flash ROM */
20 #define PA_FROM_SIZE 0x00400000 /* Flash size 4M byte */
21 #define PA_SRAM 0x00800000 /* SRAM */
22 #define PA_FROM_SIZE 0x00400000 /* SRAM size 4M byte */
24 #define PA_EXT1 0x04000000
25 #define PA_EXT1_SIZE 0x04000000
27 #define PA_EXT2 0x08000000
[all …]
/OK3568_Linux_fs/kernel/arch/powerpc/boot/dts/fsl/
H A Dp1024rdb.dtsi36 nor@0,0 {
40 reg = <0x0 0x0 0x1000000>;
44 partition@0 {
47 reg = <0x0 0x00040000>;
54 reg = <0x00040000 0x00040000>;
60 reg = <0x00080000 0x00380000>;
66 reg = <0x00400000 0x00b00000>;
74 reg = <0x00f00000 0x00100000>;
80 nand@1,0 {
85 reg = <0x1 0x0 0x40000>;
[all …]
H A Dp2020rdb-pc.dtsi36 nor@0,0 {
40 reg = <0x0 0x0 0x1000000>;
44 partition@0 {
47 reg = <0x0 0x00040000>;
54 reg = <0x00040000 0x00040000>;
60 reg = <0x00080000 0x00380000>;
66 reg = <0x00400000 0x00b00000>;
74 reg = <0x00f00000 0x00100000>;
80 nand@1,0 {
85 reg = <0x1 0x0 0x40000>;
[all …]
H A Dp1020rdb-pc.dtsi36 nor@0,0 {
40 reg = <0x0 0x0 0x1000000>;
44 partition@0 {
47 reg = <0x0 0x00040000>;
54 reg = <0x00040000 0x00040000>;
60 reg = <0x00080000 0x00380000>;
66 reg = <0x00400000 0x00b00000>;
74 reg = <0x00f00000 0x00100000>;
80 nand@1,0 {
85 reg = <0x1 0x0 0x40000>;
[all …]
H A Dp1020rdb.dtsi36 nor@0,0 {
40 reg = <0x0 0x0 0x1000000>;
44 partition@0 {
47 reg = <0x0 0x00040000>;
54 reg = <0x00040000 0x00040000>;
61 reg = <0x00080000 0x00380000>;
68 reg = <0x00400000 0x00b00000>;
76 reg = <0x00f00000 0x00100000>;
82 nand@1,0 {
87 reg = <0x1 0x0 0x40000>;
[all …]
H A Dp2020rdb.dts29 reg = <0 0xffe05000 0 0x1000>;
32 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
33 0x1 0x0 0x0 0xffa00000 0x00040000
34 0x2 0x0 0x0 0xffb00000 0x00020000>;
36 nor@0,0 {
40 reg = <0x0 0x0 0x1000000>;
44 partition@0 {
47 reg = <0x0 0x00040000>;
54 reg = <0x00040000 0x00040000>;
61 reg = <0x00080000 0x00380000>;
[all …]
H A Dp1021rdb-pc.dtsi36 nor@0,0 {
40 reg = <0x0 0x0 0x1000000>;
44 partition@0 {
47 reg = <0x0 0x00040000>;
54 reg = <0x00040000 0x00040000>;
60 reg = <0x00080000 0x00380000>;
66 reg = <0x00400000 0x00ac0000>;
73 reg = <0x00ec0000 0x00040000>;
82 reg = <0x00f00000 0x00100000>;
87 nand@1,0 {
[all …]
H A Dgef_sbc310.dts25 reg = <0x0 0x40000000>; // set by uboot
29 reg = <0xfef05000 0x1000>;
31 ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
32 1 0 0xe0000000 0x08000000 // Paged Flash 0
33 2 0 0xe8000000 0x08000000 // Paged Flash 1
34 3 0 0xfc100000 0x00020000 // NVRAM
35 4 0 0xfc000000 0x00010000>; // FPGA
37 /* flash@0,0 is a mirror of part of the memory in flash@1,0
38 flash@0,0 {
40 reg = <0x0 0x0 0x01000000>;
[all …]
H A Dp1025rdb.dtsi36 nor@0,0 {
40 reg = <0x0 0x0 0x1000000>;
44 partition@0 {
47 reg = <0x0 0x00040000>;
54 reg = <0x00040000 0x00040000>;
60 reg = <0x00080000 0x00380000>;
66 reg = <0x00400000 0x00b00000>;
74 reg = <0x00f00000 0x00100000>;
80 nand@1,0 {
85 reg = <0x1 0x0 0x40000>;
[all …]
/OK3568_Linux_fs/u-boot/include/
H A Dfsl_esdhc.h24 #define SYSCTL 0x0002e02c
25 #define SYSCTL_INITA 0x08000000
26 #define SYSCTL_TIMEOUT_MASK 0x000f0000
27 #define SYSCTL_CLOCK_MASK 0x0000fff0
29 #define SYSCTL_CKEN 0x00000008
30 #define SYSCTL_PEREN 0x00000004
31 #define SYSCTL_HCKEN 0x00000002
32 #define SYSCTL_IPGEN 0x00000001
34 #define SYSCTL_RSTA 0x01000000
35 #define SYSCTL_RSTC 0x02000000
[all …]
H A Dmpc83xx.h24 #define EXC_OFF_SYS_RESET 0x0100
32 #define CONFIG_DEFAULT_IMMR 0xFF400000
35 #define IMMRBAR 0x0000
36 #define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base addr. mask */
43 #define LBLAWBAR0 0x0020
44 #define LBLAWAR0 0x0024
45 #define LBLAWBAR1 0x0028
46 #define LBLAWAR1 0x002C
47 #define LBLAWBAR2 0x0030
48 #define LBLAWAR2 0x0034
[all …]
H A Dfsl_dspi.h17 u32 mcr; /* 0x00 */
18 u32 resv0; /* 0x04 */
19 u32 tcr; /* 0x08 */
20 u32 ctar[8]; /* 0x0C - 0x28 */
21 u32 sr; /* 0x2C */
22 u32 irsr; /* 0x30 */
23 u32 tfr; /* 0x34 - PUSHR */
24 u32 rfr; /* 0x38 - POPR */
26 u32 tfdr[4]; /* 0x3C */
27 u8 resv2[0x30]; /* 0x40 */
[all …]
/OK3568_Linux_fs/kernel/drivers/net/usb/
H A Dsmsc75xx.h12 #define TX_CMD_A_LSO (0x08000000)
13 #define TX_CMD_A_IPE (0x04000000)
14 #define TX_CMD_A_TPE (0x02000000)
15 #define TX_CMD_A_IVTG (0x01000000)
16 #define TX_CMD_A_RVTG (0x00800000)
17 #define TX_CMD_A_FCS (0x00400000)
18 #define TX_CMD_A_LEN (0x000FFFFF)
20 #define TX_CMD_B_MSS (0x3FFF0000)
23 #define TX_CMD_B_VTAG (0x0000FFFF)
26 #define RX_CMD_A_ICE (0x80000000)
[all …]
H A Dlan78xx.h9 #define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0
10 #define USB_VENDOR_REQUEST_READ_REGISTER 0xA1
11 #define USB_VENDOR_REQUEST_GET_STATS 0xA2
32 #define TX_CMD_A_IGE_ (0x20000000)
33 #define TX_CMD_A_ICE_ (0x10000000)
34 #define TX_CMD_A_LSO_ (0x08000000)
35 #define TX_CMD_A_IPE_ (0x04000000)
36 #define TX_CMD_A_TPE_ (0x02000000)
37 #define TX_CMD_A_IVTG_ (0x01000000)
38 #define TX_CMD_A_RVTG_ (0x00800000)
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dmstar-v7.dtsi17 #size-cells = <0>;
19 cpu0: cpu@0 {
22 reg = <0x0>;
53 ranges = <0x16001000 0x16001000 0x00007000>,
54 <0x1f000000 0x1f000000 0x00400000>,
55 <0xa0000000 0xa0000000 0x20000>;
59 reg = <0x16001000 0x1000>,
60 <0x16002000 0x2000>,
61 <0x16004000 0x2000>,
62 <0x16006000 0x2000>;
[all …]
/OK3568_Linux_fs/kernel/arch/mips/include/asm/mach-db1x00/
H A Dbcsr.h23 #define DB1000_BCSR_PHYS_ADDR 0x0E000000
24 #define DB1000_BCSR_HEXLED_OFS 0x01000000
26 #define DB1550_BCSR_PHYS_ADDR 0x0F000000
27 #define DB1550_BCSR_HEXLED_OFS 0x00400000
29 #define PB1550_BCSR_PHYS_ADDR 0x0F000000
30 #define PB1550_BCSR_HEXLED_OFS 0x00800000
32 #define DB1200_BCSR_PHYS_ADDR 0x19800000
33 #define DB1200_BCSR_HEXLED_OFS 0x00400000
35 #define PB1200_BCSR_PHYS_ADDR 0x0D800000
36 #define PB1200_BCSR_HEXLED_OFS 0x00400000
[all …]
/OK3568_Linux_fs/u-boot/arch/xtensa/dts/
H A Dxtfpga-flash-16m.dtsi7 reg = <0x08000000 0x01000000>;
10 partition@0x0 {
12 reg = <0x00000000 0x00400000>;
14 partition@0x400000 {
16 reg = <0x00400000 0x00600000>;
18 partition@0xa00000 {
20 reg = <0x00a00000 0x005e0000>;
22 partition@0xfe0000 {
24 reg = <0x00fe0000 0x00020000>;
/OK3568_Linux_fs/kernel/arch/xtensa/boot/dts/
H A Dxtfpga-flash-16m.dtsi8 reg = <0x08000000 0x01000000>;
11 partition@0 {
13 reg = <0x00000000 0x00400000>;
17 reg = <0x00400000 0x00600000>;
21 reg = <0x00a00000 0x005e0000>;
25 reg = <0x00fe0000 0x00020000>;
/OK3568_Linux_fs/kernel/sound/drivers/vx/
H A Dvx_cmd.h86 #define CODE_OP_PIPE_TIME 0x004e0000
87 #define CODE_OP_START_STREAM 0x00800000
88 #define CODE_OP_PAUSE_STREAM 0x00810000
89 #define CODE_OP_OUT_STREAM_LEVEL 0x00820000
90 #define CODE_OP_UPDATE_R_BUFFERS 0x00840000
91 #define CODE_OP_OUT_STREAM1_LEVEL_CURVE 0x00850000
92 #define CODE_OP_OUT_STREAM2_LEVEL_CURVE 0x00930000
93 #define CODE_OP_OUT_STREAM_FORMAT 0x00860000
94 #define CODE_OP_STREAM_TIME 0x008f0000
95 #define CODE_OP_OUT_STREAM_EXTRAPARAMETER 0x00910000
[all …]
/OK3568_Linux_fs/kernel/arch/powerpc/include/uapi/asm/
H A Dcputable.h6 #define PPC_FEATURE_32 0x80000000
7 #define PPC_FEATURE_64 0x40000000
8 #define PPC_FEATURE_601_INSTR 0x20000000
9 #define PPC_FEATURE_HAS_ALTIVEC 0x10000000
10 #define PPC_FEATURE_HAS_FPU 0x08000000
11 #define PPC_FEATURE_HAS_MMU 0x04000000
12 #define PPC_FEATURE_HAS_4xxMAC 0x02000000
13 #define PPC_FEATURE_UNIFIED_CACHE 0x01000000
14 #define PPC_FEATURE_HAS_SPE 0x00800000
15 #define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
[all …]

12345678910>>...41