1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __ASM_SH_HITACHI_SE7343_H 3*4882a593Smuzhiyun #define __ASM_SH_HITACHI_SE7343_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* 6*4882a593Smuzhiyun * include/asm-sh/se/se7343.h 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp> 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * SH-Mobile SolutionEngine 7343 support 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun #include <linux/sh_intc.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* Box specific addresses. */ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* Area 0 */ 17*4882a593Smuzhiyun #define PA_ROM 0x00000000 /* EPROM */ 18*4882a593Smuzhiyun #define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte(Actually 2MB) */ 19*4882a593Smuzhiyun #define PA_FROM 0x00400000 /* Flash ROM */ 20*4882a593Smuzhiyun #define PA_FROM_SIZE 0x00400000 /* Flash size 4M byte */ 21*4882a593Smuzhiyun #define PA_SRAM 0x00800000 /* SRAM */ 22*4882a593Smuzhiyun #define PA_FROM_SIZE 0x00400000 /* SRAM size 4M byte */ 23*4882a593Smuzhiyun /* Area 1 */ 24*4882a593Smuzhiyun #define PA_EXT1 0x04000000 25*4882a593Smuzhiyun #define PA_EXT1_SIZE 0x04000000 26*4882a593Smuzhiyun /* Area 2 */ 27*4882a593Smuzhiyun #define PA_EXT2 0x08000000 28*4882a593Smuzhiyun #define PA_EXT2_SIZE 0x04000000 29*4882a593Smuzhiyun /* Area 3 */ 30*4882a593Smuzhiyun #define PA_SDRAM 0x0c000000 31*4882a593Smuzhiyun #define PA_SDRAM_SIZE 0x04000000 32*4882a593Smuzhiyun /* Area 4 */ 33*4882a593Smuzhiyun #define PA_PCIC 0x10000000 /* MR-SHPC-01 PCMCIA */ 34*4882a593Smuzhiyun #define PA_MRSHPC 0xb03fffe0 /* MR-SHPC-01 PCMCIA controller */ 35*4882a593Smuzhiyun #define PA_MRSHPC_MW1 0xb0400000 /* MR-SHPC-01 memory window base */ 36*4882a593Smuzhiyun #define PA_MRSHPC_MW2 0xb0500000 /* MR-SHPC-01 attribute window base */ 37*4882a593Smuzhiyun #define PA_MRSHPC_IO 0xb0600000 /* MR-SHPC-01 I/O window base */ 38*4882a593Smuzhiyun #define MRSHPC_OPTION (PA_MRSHPC + 6) 39*4882a593Smuzhiyun #define MRSHPC_CSR (PA_MRSHPC + 8) 40*4882a593Smuzhiyun #define MRSHPC_ISR (PA_MRSHPC + 10) 41*4882a593Smuzhiyun #define MRSHPC_ICR (PA_MRSHPC + 12) 42*4882a593Smuzhiyun #define MRSHPC_CPWCR (PA_MRSHPC + 14) 43*4882a593Smuzhiyun #define MRSHPC_MW0CR1 (PA_MRSHPC + 16) 44*4882a593Smuzhiyun #define MRSHPC_MW1CR1 (PA_MRSHPC + 18) 45*4882a593Smuzhiyun #define MRSHPC_IOWCR1 (PA_MRSHPC + 20) 46*4882a593Smuzhiyun #define MRSHPC_MW0CR2 (PA_MRSHPC + 22) 47*4882a593Smuzhiyun #define MRSHPC_MW1CR2 (PA_MRSHPC + 24) 48*4882a593Smuzhiyun #define MRSHPC_IOWCR2 (PA_MRSHPC + 26) 49*4882a593Smuzhiyun #define MRSHPC_CDCR (PA_MRSHPC + 28) 50*4882a593Smuzhiyun #define MRSHPC_PCIC_INFO (PA_MRSHPC + 30) 51*4882a593Smuzhiyun #define PA_LED 0xb0C00000 /* LED */ 52*4882a593Smuzhiyun #define LED_SHIFT 0 53*4882a593Smuzhiyun #define PA_DIPSW 0xb0900000 /* Dip switch 31 */ 54*4882a593Smuzhiyun /* Area 5 */ 55*4882a593Smuzhiyun #define PA_EXT5 0x14000000 56*4882a593Smuzhiyun #define PA_EXT5_SIZE 0x04000000 57*4882a593Smuzhiyun /* Area 6 */ 58*4882a593Smuzhiyun #define PA_LCD1 0xb8000000 59*4882a593Smuzhiyun #define PA_LCD2 0xb8800000 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define PORT_PACR 0xA4050100 62*4882a593Smuzhiyun #define PORT_PBCR 0xA4050102 63*4882a593Smuzhiyun #define PORT_PCCR 0xA4050104 64*4882a593Smuzhiyun #define PORT_PDCR 0xA4050106 65*4882a593Smuzhiyun #define PORT_PECR 0xA4050108 66*4882a593Smuzhiyun #define PORT_PFCR 0xA405010A 67*4882a593Smuzhiyun #define PORT_PGCR 0xA405010C 68*4882a593Smuzhiyun #define PORT_PHCR 0xA405010E 69*4882a593Smuzhiyun #define PORT_PJCR 0xA4050110 70*4882a593Smuzhiyun #define PORT_PKCR 0xA4050112 71*4882a593Smuzhiyun #define PORT_PLCR 0xA4050114 72*4882a593Smuzhiyun #define PORT_PMCR 0xA4050116 73*4882a593Smuzhiyun #define PORT_PNCR 0xA4050118 74*4882a593Smuzhiyun #define PORT_PQCR 0xA405011A 75*4882a593Smuzhiyun #define PORT_PRCR 0xA405011C 76*4882a593Smuzhiyun #define PORT_PSCR 0xA405011E 77*4882a593Smuzhiyun #define PORT_PTCR 0xA4050140 78*4882a593Smuzhiyun #define PORT_PUCR 0xA4050142 79*4882a593Smuzhiyun #define PORT_PVCR 0xA4050144 80*4882a593Smuzhiyun #define PORT_PWCR 0xA4050146 81*4882a593Smuzhiyun #define PORT_PYCR 0xA4050148 82*4882a593Smuzhiyun #define PORT_PZCR 0xA405014A 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun #define PORT_PSELA 0xA405014C 85*4882a593Smuzhiyun #define PORT_PSELB 0xA405014E 86*4882a593Smuzhiyun #define PORT_PSELC 0xA4050150 87*4882a593Smuzhiyun #define PORT_PSELD 0xA4050152 88*4882a593Smuzhiyun #define PORT_PSELE 0xA4050154 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #define PORT_HIZCRA 0xA4050156 91*4882a593Smuzhiyun #define PORT_HIZCRB 0xA4050158 92*4882a593Smuzhiyun #define PORT_HIZCRC 0xA405015C 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun #define PORT_DRVCR 0xA4050180 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun #define PORT_PADR 0xA4050120 97*4882a593Smuzhiyun #define PORT_PBDR 0xA4050122 98*4882a593Smuzhiyun #define PORT_PCDR 0xA4050124 99*4882a593Smuzhiyun #define PORT_PDDR 0xA4050126 100*4882a593Smuzhiyun #define PORT_PEDR 0xA4050128 101*4882a593Smuzhiyun #define PORT_PFDR 0xA405012A 102*4882a593Smuzhiyun #define PORT_PGDR 0xA405012C 103*4882a593Smuzhiyun #define PORT_PHDR 0xA405012E 104*4882a593Smuzhiyun #define PORT_PJDR 0xA4050130 105*4882a593Smuzhiyun #define PORT_PKDR 0xA4050132 106*4882a593Smuzhiyun #define PORT_PLDR 0xA4050134 107*4882a593Smuzhiyun #define PORT_PMDR 0xA4050136 108*4882a593Smuzhiyun #define PORT_PNDR 0xA4050138 109*4882a593Smuzhiyun #define PORT_PQDR 0xA405013A 110*4882a593Smuzhiyun #define PORT_PRDR 0xA405013C 111*4882a593Smuzhiyun #define PORT_PTDR 0xA4050160 112*4882a593Smuzhiyun #define PORT_PUDR 0xA4050162 113*4882a593Smuzhiyun #define PORT_PVDR 0xA4050164 114*4882a593Smuzhiyun #define PORT_PWDR 0xA4050166 115*4882a593Smuzhiyun #define PORT_PYDR 0xA4050168 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun #define FPGA_IN 0xb1400000 118*4882a593Smuzhiyun #define FPGA_OUT 0xb1400002 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun #define IRQ0_IRQ evt2irq(0x600) 121*4882a593Smuzhiyun #define IRQ1_IRQ evt2irq(0x620) 122*4882a593Smuzhiyun #define IRQ4_IRQ evt2irq(0x680) 123*4882a593Smuzhiyun #define IRQ5_IRQ evt2irq(0x6a0) 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun #define SE7343_FPGA_IRQ_MRSHPC0 0 126*4882a593Smuzhiyun #define SE7343_FPGA_IRQ_MRSHPC1 1 127*4882a593Smuzhiyun #define SE7343_FPGA_IRQ_MRSHPC2 2 128*4882a593Smuzhiyun #define SE7343_FPGA_IRQ_MRSHPC3 3 129*4882a593Smuzhiyun #define SE7343_FPGA_IRQ_SMC 6 /* EXT_IRQ2 */ 130*4882a593Smuzhiyun #define SE7343_FPGA_IRQ_USB 8 131*4882a593Smuzhiyun #define SE7343_FPGA_IRQ_UARTA 10 132*4882a593Smuzhiyun #define SE7343_FPGA_IRQ_UARTB 11 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun #define SE7343_FPGA_IRQ_NR 12 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun struct irq_domain; 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun /* arch/sh/boards/se/7343/irq.c */ 139*4882a593Smuzhiyun extern struct irq_domain *se7343_irq_domain; 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun void init_7343se_IRQ(void); 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun #endif /* __ASM_SH_HITACHI_SE7343_H */ 144