1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2017 Rockchip Electronics Co., Ltd 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __CONFIG_PX30_COMMON_H 8*4882a593Smuzhiyun #define __CONFIG_PX30_COMMON_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include "rockchip-common.h" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_LEN (32 << 20) 13*4882a593Smuzhiyun #define CONFIG_SYS_CBSIZE 1024 14*4882a593Smuzhiyun #define CONFIG_SKIP_LOWLEVEL_INIT 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define CONFIG_SPL_FRAMEWORK 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define CONFIG_SYS_NS16550_MEM32 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x00200000 21*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR 0x00400000 22*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR 0x00800800 23*4882a593Smuzhiyun #define CONFIG_SPL_STACK 0x00400000 24*4882a593Smuzhiyun #define CONFIG_SPL_TEXT_BASE 0x00000000 25*4882a593Smuzhiyun #define CONFIG_SPL_MAX_SIZE 0x40000 26*4882a593Smuzhiyun #define CONFIG_SPL_BSS_START_ADDR 0x2000000 27*4882a593Smuzhiyun #define CONFIG_SPL_BSS_MAX_SIZE 0x2000 28*4882a593Smuzhiyun #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define COUNTER_FREQUENCY 24000000 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define GICD_BASE 0xff131000 33*4882a593Smuzhiyun #define GICC_BASE 0xff132000 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* MMC/SD IP block */ 38*4882a593Smuzhiyun #define CONFIG_BOUNCE_BUFFER 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE 0 41*4882a593Smuzhiyun #define SDRAM_MAX_SIZE 0xff000000 42*4882a593Smuzhiyun #define SDRAM_BANK_SIZE (2UL << 30) 43*4882a593Smuzhiyun #ifdef CONFIG_DM_DVFS 44*4882a593Smuzhiyun #define CONFIG_PREBOOT "dvfs repeat" 45*4882a593Smuzhiyun #else 46*4882a593Smuzhiyun #define CONFIG_PREBOOT 47*4882a593Smuzhiyun #endif 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* Nand */ 50*4882a593Smuzhiyun #define CONFIG_SYS_MAX_NAND_DEVICE 1 51*4882a593Smuzhiyun #define CONFIG_SYS_NAND_ONFI_DETECTION 52*4882a593Smuzhiyun #ifndef CONFIG_SPL_BUILD 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* usb mass storage */ 55*4882a593Smuzhiyun #define CONFIG_USB_FUNCTION_MASS_STORAGE 56*4882a593Smuzhiyun #define CONFIG_ROCKUSB_G_DNL_PID 0x330d 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #ifdef CONFIG_ARM64 59*4882a593Smuzhiyun #define ENV_MEM_LAYOUT_SETTINGS \ 60*4882a593Smuzhiyun "scriptaddr=0x00500000\0" \ 61*4882a593Smuzhiyun "pxefile_addr_r=0x00600000\0" \ 62*4882a593Smuzhiyun "fdt_addr_r=0x08300000\0" \ 63*4882a593Smuzhiyun "kernel_addr_r=0x00280000\0" \ 64*4882a593Smuzhiyun "kernel_addr_c=0x03e80000\0" \ 65*4882a593Smuzhiyun "ramdisk_addr_r=0x0a200000\0" 66*4882a593Smuzhiyun #else 67*4882a593Smuzhiyun #define ENV_MEM_LAYOUT_SETTINGS \ 68*4882a593Smuzhiyun "scriptaddr=0x00000000\0" \ 69*4882a593Smuzhiyun "pxefile_addr_r=0x00100000\0" \ 70*4882a593Smuzhiyun "fdt_addr_r=0x08300000\0" \ 71*4882a593Smuzhiyun "kernel_addr_r=0x02008000\0" \ 72*4882a593Smuzhiyun "ramdisk_addr_r=0x0a200000\0" 73*4882a593Smuzhiyun #endif 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #include <config_distro_bootcmd.h> 76*4882a593Smuzhiyun #define CONFIG_EXTRA_ENV_SETTINGS \ 77*4882a593Smuzhiyun ENV_MEM_LAYOUT_SETTINGS \ 78*4882a593Smuzhiyun "partitions=" PARTS_DEFAULT \ 79*4882a593Smuzhiyun ROCKCHIP_DEVICE_SETTINGS \ 80*4882a593Smuzhiyun RKIMG_DET_BOOTDEV \ 81*4882a593Smuzhiyun BOOTENV 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun #endif 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* rockchip ohci host driver */ 86*4882a593Smuzhiyun #define CONFIG_USB_OHCI_NEW 87*4882a593Smuzhiyun #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun #endif 90