Lines Matching +full:0 +full:x00400000
25 * default CCARBAR is at 0xff700000
28 #define CONFIG_SYS_TEXT_BASE 0xfff80000
63 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
64 #define CONFIG_SYS_MEMTEST_END 0x00400000
66 #define CONFIG_SYS_CCSRBAR 0xe0000000
74 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
76 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
83 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
87 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
88 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002
89 #define CONFIG_SYS_DDR_TIMING_1 0x37344321
90 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
91 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
92 #define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
93 #define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
98 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
101 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
102 #define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */
104 #define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
131 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
134 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
140 * 0 4 8 12 16 20 24 28
147 #define CONFIG_SYS_BR2_PRELIM 0xf0001861
153 * 64MB mask for AM, OR2[0:7] = 1111 1100
159 * 0 4 8 12 16 20 24 28
163 #define CONFIG_SYS_OR2_PRELIM 0xfc006901
165 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
166 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
167 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
168 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
192 #define CONFIG_SYS_BR4_PRELIM 0xf8000801
193 #define CONFIG_SYS_OR4_PRELIM 0xffffe1f1
194 #define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
197 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
198 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
220 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
221 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
222 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
225 #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */
226 #define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */
227 #define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000
228 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
232 * Memory space is mapped 1-1, but I/O space must start from 0.
234 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
235 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
236 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
237 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
238 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
239 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
240 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
241 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
248 #define PCI_ENET0_IOADDR 0xe0000000
249 #define PCI_ENET0_MEMADDR 0xe0000000
250 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
254 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
267 #define TSEC1_PHY_ADDR 0
269 #define TSEC1_PHYIDX 0
270 #define TSEC2_PHYIDX 0
274 /* Options are: TSEC[0-1] */
293 #define CONFIG_SYS_CPMFCR_RAMTYPE 0
295 #define FETH2_RST 0x01
298 #define FETH3_RST 0x80
315 #define MDIO_ACTIVE (iop->pdir |= 0x00400000)
316 #define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
317 #define MDIO_READ ((iop->pdat & 0x00400000) != 0)
319 #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
320 else iop->pdat &= ~0x00400000
322 #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
323 else iop->pdat &= ~0x00200000
333 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
334 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
335 #define CONFIG_ENV_SIZE 0x2000
337 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
338 #define CONFIG_ENV_SIZE 0x2000
360 #define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
399 "netdev=eth0\0" \
400 "consoledev=ttyCPM\0" \
401 "ramdiskaddr=1000000\0" \
402 "ramdiskfile=your.ramdisk.u-boot\0" \
403 "fdtaddr=400000\0" \
404 "fdtfile=mpc8560ads.dtb\0"