Home
last modified time | relevance | path

Searched +full:0 +full:x001 (Results 1 – 25 of 383) sorted by relevance

12345678910>>...16

/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dimx25-pinfunc.h16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000
24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000
25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000
26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000
28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000
[all …]
H A Dimx1-pinfunc.h15 * function: 0 - Primary function
18 * direction: 0 - Input
20 * gpio_oconf: 0 - A_IN
24 * gpio_iconfa/b: 0 - GPIO_IN
26 * 2 - 0
29 * 'pin' is an integer between 0 and 0xbf. i.MX1 has 4 ports with 32 configurable
31 * number on the specific port (between 0 and 31).
34 #define MX1_PAD_A24__A24 0x00 0x004
35 #define MX1_PAD_A24__GPIO1_0 0x00 0x032
36 #define MX1_PAD_A24__SPI2_CLK 0x00 0x006
[all …]
H A Dimx27-pinfunc.h15 * function: 0 - Primary function
18 * direction: 0 - Input
20 * gpio_oconf: 0 - A_IN
24 * gpio_iconfa/b: 0 - GPIO_IN
26 * 2 - 0
29 * 'pin' is an integer between 0 and 0xbf. imx27 has 6 ports with 32 configurable
31 * number on the specific port (between 0 and 31).
34 #define MX27_PAD_USBH2_CLK__USBH2_CLK 0x00 0x000
35 #define MX27_PAD_USBH2_CLK__GPIO1_0 0x00 0x032
36 #define MX27_PAD_USBH2_DIR__USBH2_DIR 0x01 0x000
[all …]
/OK3568_Linux_fs/kernel/sound/pci/oxygen/
H A Dwm8776.h14 #define WM8776_HPLVOL 0x00
15 #define WM8776_HPRVOL 0x01
16 #define WM8776_HPMASTER 0x02
17 #define WM8776_DACLVOL 0x03
18 #define WM8776_DACRVOL 0x04
19 #define WM8776_DACMASTER 0x05
20 #define WM8776_PHASESWAP 0x06
21 #define WM8776_DACCTRL1 0x07
22 #define WM8776_DACMUTE 0x08
23 #define WM8776_DACCTRL2 0x09
[all …]
H A Dwm8785.h5 #define WM8785_R0 0
11 #define WM8785_MCR_MASK 0x007
12 #define WM8785_MCR_SLAVE 0x000
13 #define WM8785_MCR_MASTER_128 0x001
14 #define WM8785_MCR_MASTER_192 0x002
15 #define WM8785_MCR_MASTER_256 0x003
16 #define WM8785_MCR_MASTER_384 0x004
17 #define WM8785_MCR_MASTER_512 0x005
18 #define WM8785_MCR_MASTER_768 0x006
19 #define WM8785_OSR_MASK 0x018
[all …]
H A Dwm8766.h5 #define WM8766_LDA1 0x00
6 #define WM8766_RDA1 0x01
7 #define WM8766_DAC_CTRL 0x02
8 #define WM8766_INT_CTRL 0x03
9 #define WM8766_LDA2 0x04
10 #define WM8766_RDA2 0x05
11 #define WM8766_LDA3 0x06
12 #define WM8766_RDA3 0x07
13 #define WM8766_MASTDA 0x08
14 #define WM8766_DAC_CTRL2 0x09
[all …]
/OK3568_Linux_fs/kernel/include/sound/sof/
H A Dheader.h23 * 0xGCCCNNNN where
34 #define SOF_GLB_TYPE_MASK (0xf << SOF_GLB_TYPE_SHIFT)
39 #define SOF_CMD_TYPE_MASK (0xfff << SOF_CMD_TYPE_SHIFT)
43 #define SOF_IPC_GLB_REPLY SOF_GLB_TYPE(0x1U)
44 #define SOF_IPC_GLB_COMPOUND SOF_GLB_TYPE(0x2U)
45 #define SOF_IPC_GLB_TPLG_MSG SOF_GLB_TYPE(0x3U)
46 #define SOF_IPC_GLB_PM_MSG SOF_GLB_TYPE(0x4U)
47 #define SOF_IPC_GLB_COMP_MSG SOF_GLB_TYPE(0x5U)
48 #define SOF_IPC_GLB_STREAM_MSG SOF_GLB_TYPE(0x6U)
49 #define SOF_IPC_FW_READY SOF_GLB_TYPE(0x7U)
[all …]
/OK3568_Linux_fs/kernel/sound/soc/codecs/
H A Dssm2602.h33 #define SSM2602_LINVOL 0x00
34 #define SSM2602_RINVOL 0x01
35 #define SSM2602_LOUT1V 0x02
36 #define SSM2602_ROUT1V 0x03
37 #define SSM2602_APANA 0x04
38 #define SSM2602_APDIGI 0x05
39 #define SSM2602_PWR 0x06
40 #define SSM2602_IFACE 0x07
41 #define SSM2602_SRATE 0x08
42 #define SSM2602_ACTIVE 0x09
[all …]
H A Dwcd9335.h8 * In slimbus mode the reg base starts from 0x800.
9 * In i2s/i2c mode the reg base is 0x0.
12 #define WCD9335_REG_OFFSET(r) (r & 0xFF)
13 #define WCD9335_PAGE_OFFSET(r) ((r >> 8) & 0xFF)
15 /* Page-0 Registers */
16 #define WCD9335_PAGE0_PAGE_REGISTER WCD9335_REG(0x00, 0x000)
17 #define WCD9335_CODEC_RPM_CLK_GATE WCD9335_REG(0x00, 0x002)
18 #define WCD9335_CODEC_RPM_CLK_GATE_MCLK_GATE_MASK GENMASK(1, 0)
19 #define WCD9335_CODEC_RPM_CLK_MCLK_CFG WCD9335_REG(0x00, 0x003)
20 #define WCD9335_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ BIT(0)
[all …]
/OK3568_Linux_fs/kernel/drivers/media/dvb-frontends/
H A Dsp887x.c38 } while (0)
42 struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = len }; in i2c_writebytes()
51 return 0; in i2c_writebytes()
56 u8 b0 [] = { reg >> 8 , reg & 0xff, data >> 8, data & 0xff }; in sp887x_writereg()
57 struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 4 }; in sp887x_writereg()
64 if (!(reg == 0xf1a && data == 0x000 && in sp887x_writereg()
68 __func__, reg & 0xffff, data & 0xffff, ret); in sp887x_writereg()
73 return 0; in sp887x_writereg()
78 u8 b0 [] = { reg >> 8 , reg & 0xff }; in sp887x_readreg()
81 struct i2c_msg msg[] = {{ .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 2 }, in sp887x_readreg()
[all …]
/OK3568_Linux_fs/kernel/drivers/media/i2c/
H A Dsaa717x.c36 MODULE_PARM_DESC(debug, "Debug level (0-1)");
76 #define TUNER_AUDIO_MONO 0 /* LL */
90 int fw_addr = reg == 0x454 || (reg >= 0x464 && reg <= 0x478) || reg == 0x480 || reg == 0x488; in saa717x_write()
94 msg.flags = 0; in saa717x_write()
96 mm1[0] = (reg >> 8) & 0xff; in saa717x_write()
97 mm1[1] = reg & 0xff; in saa717x_write()
100 mm1[4] = (value >> 16) & 0xff; in saa717x_write()
101 mm1[3] = (value >> 8) & 0xff; in saa717x_write()
102 mm1[2] = value & 0xff; in saa717x_write()
104 mm1[2] = value & 0xff; in saa717x_write()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/rockchip/rk618/
H A Drk618_vif.c21 #define RK618_VIF0_REG0 0x0000
22 #define VIF_ENABLE HIWORD_UPDATE(1, 0, 0)
23 #define VIF_DISABLE HIWORD_UPDATE(0, 0, 0)
24 #define RK618_VIF0_REG1 0x0004
26 #define VIF_FRAME_HST(x) UPDATE(x, 11, 0)
27 #define RK618_VIF0_REG2 0x0008
29 #define VIF_HTOTAL(x) UPDATE(x, 11, 0)
30 #define RK618_VIF0_REG3 0x000c
32 #define VIF_HACT_ST(x) UPDATE(x, 11, 0)
33 #define RK618_VIF0_REG4 0x0010
[all …]
/OK3568_Linux_fs/kernel/arch/m68k/coldfire/
H A Dintc-525x.c28 imr &= ~(0x001 << irq); in intc2_irq_gpio_mask()
30 imr &= ~(0x100 << irq); in intc2_irq_gpio_mask()
41 imr |= (0x001 << irq); in intc2_irq_gpio_unmask()
43 imr |= (0x100 << irq); in intc2_irq_gpio_unmask()
49 u32 imr = 0; in intc2_irq_gpio_ack()
54 imr |= (0x001 << irq); in intc2_irq_gpio_ack()
56 imr |= (0x100 << irq); in intc2_irq_gpio_ack()
64 return 0; in intc2_irq_gpio_set_type()
88 return 0; in mcf_intc2_init()
/OK3568_Linux_fs/kernel/drivers/net/ethernet/seeq/
H A Dsgiseeq.h35 #define SEEQ_RSTAT_OVERF 0x001 /* Overflow */
36 #define SEEQ_RSTAT_CERROR 0x002 /* CRC error */
37 #define SEEQ_RSTAT_DERROR 0x004 /* Dribble error */
38 #define SEEQ_RSTAT_SFRAME 0x008 /* Short frame */
39 #define SEEQ_RSTAT_REOF 0x010 /* Received end of frame */
40 #define SEEQ_RSTAT_FIG 0x020 /* Frame is good */
41 #define SEEQ_RSTAT_TIMEO 0x040 /* Timeout, or late receive */
42 #define SEEQ_RSTAT_WHICH 0x080 /* Which status, 1=old 0=new */
43 #define SEEQ_RSTAT_LITTLE 0x100 /* DMA is done in little endian format */
44 #define SEEQ_RSTAT_SDMA 0x200 /* DMA has started */
[all …]
/OK3568_Linux_fs/u-boot/board/ti/ti816x/
H A Devm.c28 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; in board_init()
32 return 0; in board_init()
46 mac_addr[0] = mac_hi & 0xFF; in board_eth_init()
47 mac_addr[1] = (mac_hi & 0xFF00) >> 8; in board_eth_init()
48 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; in board_eth_init()
49 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; in board_eth_init()
50 mac_addr[4] = mac_lo & 0xFF; in board_eth_init()
51 mac_addr[5] = (mac_lo & 0xFF00) >> 8; in board_eth_init()
64 { OFFSET(pincntl157), PULLDOWN_EN | PULLUDDIS | MODE(0x0) },
65 { OFFSET(pincntl158), PULLDOWN_EN | PULLUDEN | MODE(0x0) },
[all …]
/OK3568_Linux_fs/kernel/arch/mips/include/asm/
H A Dhpet.h9 #define HPET_ID 0x000
10 #define HPET_PERIOD 0x004
11 #define HPET_CFG 0x010
12 #define HPET_STATUS 0x020
13 #define HPET_COUNTER 0x0f0
15 #define HPET_Tn_CFG(n) (0x100 + 0x20 * n)
16 #define HPET_Tn_CMP(n) (0x108 + 0x20 * n)
17 #define HPET_Tn_ROUTE(n) (0x110 + 0x20 * n)
19 #define HPET_T0_IRS 0x001
20 #define HPET_T1_IRS 0x002
[all …]
/OK3568_Linux_fs/kernel/arch/c6x/platforms/
H A Dtimer64.c34 #define TCR_TSTATLO 0x001
35 #define TCR_INVOUTPLO 0x002
36 #define TCR_INVINPLO 0x004
37 #define TCR_CPLO 0x008
38 #define TCR_ENAMODELO_ONCE 0x040
39 #define TCR_ENAMODELO_CONT 0x080
40 #define TCR_ENAMODELO_MASK 0x0c0
41 #define TCR_PWIDLO_MASK 0x030
42 #define TCR_CLKSRCLO 0x100
43 #define TCR_TIENLO 0x200
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-uniphier/dram/
H A Dddrmphy-regs.h16 #define MPHY_RIDR (0x000 << MPHY_SHIFT)
17 #define MPHY_PIR (0x001 << MPHY_SHIFT)
18 #define MPHY_PIR_INIT BIT(0) /* Initialization Trigger */
34 #define MPHY_PGCR0 (0x002 << MPHY_SHIFT)
36 #define MPHY_PGCR1 (0x003 << MPHY_SHIFT)
38 #define MPHY_PGCR2 (0x004 << MPHY_SHIFT)
41 #define MPHY_PGCR3 (0x005 << MPHY_SHIFT)
42 #define MPHY_PGSR0 (0x006 << MPHY_SHIFT)
43 #define MPHY_PGSR0_IDONE BIT(0) /* Initialization Done */
63 #define MPHY_PGSR1 (0x007 << MPHY_SHIFT)
[all …]
H A Dddrphy-regs.h15 #define PHY_RIDR (0x000 << PHY_REG_SHIFT)
16 #define PHY_PIR (0x001 << PHY_REG_SHIFT)
17 #define PHY_PIR_INIT BIT(0) /* Initialization Trigger */
35 #define PHY_PGCR0 (0x002 << PHY_REG_SHIFT)
36 #define PHY_PGCR1 (0x003 << PHY_REG_SHIFT)
38 #define PHY_PGSR0 (0x004 << PHY_REG_SHIFT)
39 #define PHY_PGSR0_IDONE BIT(0) /* Initialization Done */
61 #define PHY_PGSR1 (0x005 << PHY_REG_SHIFT)
63 #define PHY_PLLCR (0x006 << PHY_REG_SHIFT)
64 #define PHY_PTR0 (0x007 << PHY_REG_SHIFT)
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_doorbell.h85 AMDGPU_DOORBELL_KIQ = 0x000,
86 AMDGPU_DOORBELL_HIQ = 0x001,
87 AMDGPU_DOORBELL_DIQ = 0x002,
88 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
89 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
90 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
91 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
92 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
93 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
94 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
[all …]
/OK3568_Linux_fs/kernel/arch/arc/include/asm/
H A Dcache.h20 * ARC700 doesn't cache any access in top 1G (0xc000_0000 to 0xFFFF_FFFF)
24 #define ARC_UNCACHED_ADDR_SPACE 0xc0000000
35 " ld.di %0, [%1] \n" \
44 " st.di %0, [%1] \n" \
75 #define ARC_REG_IC_BCR 0x77 /* Build Config reg */
76 #define ARC_REG_IC_IVIC 0x10
77 #define ARC_REG_IC_CTRL 0x11
78 #define ARC_REG_IC_IVIR 0x16
79 #define ARC_REG_IC_ENDR 0x17
80 #define ARC_REG_IC_IVIL 0x19
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/broadcom/b43/
H A Dphy_ht.h8 #define B43_PHY_HT_BBCFG 0x001 /* BB config */
9 #define B43_PHY_HT_BBCFG_RSTCCA 0x4000 /* Reset CCA */
10 #define B43_PHY_HT_BBCFG_RSTRX 0x8000 /* Reset RX */
11 #define B43_PHY_HT_BANDCTL 0x009 /* Band control */
12 #define B43_PHY_HT_BANDCTL_5GHZ 0x0001 /* Use the 5GHz band */
13 #define B43_PHY_HT_TABLE_ADDR 0x072 /* Table address */
14 #define B43_PHY_HT_TABLE_DATALO 0x073 /* Table data low */
15 #define B43_PHY_HT_TABLE_DATAHI 0x074 /* Table data high */
16 #define B43_PHY_HT_CLASS_CTL 0x0B0 /* Classifier control */
17 #define B43_PHY_HT_CLASS_CTL_CCK_EN 0x0001 /* CCK enable */
[all …]
/OK3568_Linux_fs/kernel/arch/mips/math-emu/
H A Ddp_sqrt.c13 0, 1204, 3062, 5746, 9193, 13348, 18162, 23592,
41 /* sqrt(0) = 0 */ in ieee754dp_sqrt()
72 scalx = 0; in ieee754dp_sqrt()
81 x = builddp(0, xe + DP_EBIAS, xm & ~DP_HIDDEN_BIT); in ieee754dp_sqrt()
86 yh = (yh >> 1) + 0x1ff80000; in ieee754dp_sqrt()
88 y.bits = ((u64) yh << 32) | (y.bits & 0xffffffff); in ieee754dp_sqrt()
91 /* t=x/y; y=y+t; py[n0]=py[n0]-0x00100006; py[n1]=0; */ in ieee754dp_sqrt()
94 y.bits -= 0x0010000600000000LL; in ieee754dp_sqrt()
95 y.bits &= 0xffffffff00000000LL; in ieee754dp_sqrt()
98 /* t=y*y; z=t; pt[n0]+=0x00100000; t+=z; z=(x-z)*y; */ in ieee754dp_sqrt()
[all …]
/OK3568_Linux_fs/kernel/arch/arm/probes/
H A Ddecode-arm.c19 #define sign_extend(x, signbit) ((x) | (0 - ((x) & (1 << (signbit)))))
21 #define branch_displacement(insn) sign_extend(((insn) & 0xffffff) << 2, 25)
72 regs->ARM_pc = iaddr + 8 + disp + ((insn >> 23) & 0x2); in simulate_blx1()
79 int rm = insn & 0xf; in simulate_blx2bx()
85 regs->ARM_pc = rmv & ~0x1; in simulate_blx2bx()
87 if (rmv & 0x1) in simulate_blx2bx()
94 int rd = (insn >> 12) & 0xf; in simulate_mrs()
95 unsigned long mask = 0xf8ff03df; /* Mask out execution state */ in simulate_mrs()
118 /* memory hint 1111 0100 x001 xxxx xxxx xxxx xxxx xxxx */
120 /* PLDW (immediate) 1111 0101 x001 xxxx xxxx xxxx xxxx xxxx */
[all …]
/OK3568_Linux_fs/kernel/sound/usb/usx2y/
H A Dus122l.c24 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-max */
37 #define US122L_FLAG_US144 BIT(0)
46 .out_cables = 0x001, in us122l_create_usbmidi()
47 .in_cables = 0x001 in us122l_create_usbmidi()
68 .out_cables = 0x001, in us144_create_usbmidi()
69 .in_cables = 0x001 in us144_create_usbmidi()
74 .ifnum = 0, in us144_create_usbmidi()
79 struct usb_interface *iface = usb_ifnum_to_if(dev, 0); in us144_create_usbmidi()
89 ret = usb_control_msg_send(dev, 0, 'I', in pt_info_set()
91 v, 0, NULL, 0, 1000, GFP_NOIO); in pt_info_set()
[all …]

12345678910>>...16