1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * UniPhier DDR MultiPHY registers 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2015-2017 Socionext Inc. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef UNIPHIER_DDRMPHY_REGS_H 10*4882a593Smuzhiyun #define UNIPHIER_DDRMPHY_REGS_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <linux/bitops.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define MPHY_SHIFT 2 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define MPHY_RIDR (0x000 << MPHY_SHIFT) 17*4882a593Smuzhiyun #define MPHY_PIR (0x001 << MPHY_SHIFT) 18*4882a593Smuzhiyun #define MPHY_PIR_INIT BIT(0) /* Initialization Trigger */ 19*4882a593Smuzhiyun #define MPHY_PIR_ZCAL BIT(1) /* Impedance Calibration */ 20*4882a593Smuzhiyun #define MPHY_PIR_PLLINIT BIT(4) /* PLL Initialization */ 21*4882a593Smuzhiyun #define MPHY_PIR_DCAL BIT(5) /* DDL Calibration */ 22*4882a593Smuzhiyun #define MPHY_PIR_PHYRST BIT(6) /* PHY Reset */ 23*4882a593Smuzhiyun #define MPHY_PIR_DRAMRST BIT(7) /* DRAM Reset */ 24*4882a593Smuzhiyun #define MPHY_PIR_DRAMINIT BIT(8) /* DRAM Initialization */ 25*4882a593Smuzhiyun #define MPHY_PIR_WL BIT(9) /* Write Leveling */ 26*4882a593Smuzhiyun #define MPHY_PIR_QSGATE BIT(10) /* Read DQS Gate Training */ 27*4882a593Smuzhiyun #define MPHY_PIR_WLADJ BIT(11) /* Write Leveling Adjust */ 28*4882a593Smuzhiyun #define MPHY_PIR_RDDSKW BIT(12) /* Read Data Bit Deskew */ 29*4882a593Smuzhiyun #define MPHY_PIR_WRDSKW BIT(13) /* Write Data Bit Deskew */ 30*4882a593Smuzhiyun #define MPHY_PIR_RDEYE BIT(14) /* Read Data Eye Training */ 31*4882a593Smuzhiyun #define MPHY_PIR_WREYE BIT(15) /* Write Data Eye Training */ 32*4882a593Smuzhiyun #define MPHY_PIR_ZCALBYP BIT(30) /* Impedance Calib Bypass */ 33*4882a593Smuzhiyun #define MPHY_PIR_INITBYP BIT(31) /* Initialization Bypass */ 34*4882a593Smuzhiyun #define MPHY_PGCR0 (0x002 << MPHY_SHIFT) 35*4882a593Smuzhiyun #define MPHY_PGCR0_PHYFRST BIT(26) /* PHY FIFO Reset */ 36*4882a593Smuzhiyun #define MPHY_PGCR1 (0x003 << MPHY_SHIFT) 37*4882a593Smuzhiyun #define MPHY_PGCR1_INHVT BIT(26) /* VT Calculation Inhibit */ 38*4882a593Smuzhiyun #define MPHY_PGCR2 (0x004 << MPHY_SHIFT) 39*4882a593Smuzhiyun #define MPHY_PGCR2_DUALCHN BIT(28) /* Dual Channel Configuration*/ 40*4882a593Smuzhiyun #define MPHY_PGCR2_ACPDDC BIT(29) /* AC Power-Down with Dual Ch*/ 41*4882a593Smuzhiyun #define MPHY_PGCR3 (0x005 << MPHY_SHIFT) 42*4882a593Smuzhiyun #define MPHY_PGSR0 (0x006 << MPHY_SHIFT) 43*4882a593Smuzhiyun #define MPHY_PGSR0_IDONE BIT(0) /* Initialization Done */ 44*4882a593Smuzhiyun #define MPHY_PGSR0_PLDONE BIT(1) /* PLL Lock Done */ 45*4882a593Smuzhiyun #define MPHY_PGSR0_DCDONE BIT(2) /* DDL Calibration Done */ 46*4882a593Smuzhiyun #define MPHY_PGSR0_ZCDONE BIT(3) /* Impedance Calibration Done */ 47*4882a593Smuzhiyun #define MPHY_PGSR0_DIDONE BIT(4) /* DRAM Initialization Done */ 48*4882a593Smuzhiyun #define MPHY_PGSR0_WLDONE BIT(5) /* Write Leveling Done */ 49*4882a593Smuzhiyun #define MPHY_PGSR0_QSGDONE BIT(6) /* DQS Gate Training Done */ 50*4882a593Smuzhiyun #define MPHY_PGSR0_WLADONE BIT(7) /* Write Leveling Adjust Done */ 51*4882a593Smuzhiyun #define MPHY_PGSR0_RDDONE BIT(8) /* Read Bit Deskew Done */ 52*4882a593Smuzhiyun #define MPHY_PGSR0_WDDONE BIT(9) /* Write Bit Deskew Done */ 53*4882a593Smuzhiyun #define MPHY_PGSR0_REDONE BIT(10) /* Read Eye Training Done */ 54*4882a593Smuzhiyun #define MPHY_PGSR0_WEDONE BIT(11) /* Write Eye Training Done */ 55*4882a593Smuzhiyun #define MPHY_PGSR0_ZCERR BIT(20) /* Impedance Calib Error */ 56*4882a593Smuzhiyun #define MPHY_PGSR0_WLERR BIT(21) /* Write Leveling Error */ 57*4882a593Smuzhiyun #define MPHY_PGSR0_QSGERR BIT(22) /* DQS Gate Training Error */ 58*4882a593Smuzhiyun #define MPHY_PGSR0_WLAERR BIT(23) /* Write Leveling Adj Error */ 59*4882a593Smuzhiyun #define MPHY_PGSR0_RDERR BIT(24) /* Read Bit Deskew Error */ 60*4882a593Smuzhiyun #define MPHY_PGSR0_WDERR BIT(25) /* Write Bit Deskew Error */ 61*4882a593Smuzhiyun #define MPHY_PGSR0_REERR BIT(26) /* Read Eye Training Error */ 62*4882a593Smuzhiyun #define MPHY_PGSR0_WEERR BIT(27) /* Write Eye Training Error */ 63*4882a593Smuzhiyun #define MPHY_PGSR1 (0x007 << MPHY_SHIFT) 64*4882a593Smuzhiyun #define MPHY_PGSR1_VTSTOP BIT(30) /* VT Stop */ 65*4882a593Smuzhiyun #define MPHY_PLLCR (0x008 << MPHY_SHIFT) 66*4882a593Smuzhiyun #define MPHY_PTR0 (0x009 << MPHY_SHIFT) 67*4882a593Smuzhiyun #define MPHY_PTR1 (0x00A << MPHY_SHIFT) 68*4882a593Smuzhiyun #define MPHY_PTR2 (0x00B << MPHY_SHIFT) 69*4882a593Smuzhiyun #define MPHY_PTR3 (0x00C << MPHY_SHIFT) 70*4882a593Smuzhiyun #define MPHY_PTR4 (0x00D << MPHY_SHIFT) 71*4882a593Smuzhiyun #define MPHY_ACMDLR (0x00E << MPHY_SHIFT) 72*4882a593Smuzhiyun #define MPHY_ACLCDLR (0x00F << MPHY_SHIFT) 73*4882a593Smuzhiyun #define MPHY_ACBDLR0 (0x010 << MPHY_SHIFT) 74*4882a593Smuzhiyun #define MPHY_ACBDLR1 (0x011 << MPHY_SHIFT) 75*4882a593Smuzhiyun #define MPHY_ACBDLR2 (0x012 << MPHY_SHIFT) 76*4882a593Smuzhiyun #define MPHY_ACBDLR3 (0x013 << MPHY_SHIFT) 77*4882a593Smuzhiyun #define MPHY_ACBDLR4 (0x014 << MPHY_SHIFT) 78*4882a593Smuzhiyun #define MPHY_ACBDLR5 (0x015 << MPHY_SHIFT) 79*4882a593Smuzhiyun #define MPHY_ACBDLR6 (0x016 << MPHY_SHIFT) 80*4882a593Smuzhiyun #define MPHY_ACBDLR7 (0x017 << MPHY_SHIFT) 81*4882a593Smuzhiyun #define MPHY_ACBDLR8 (0x018 << MPHY_SHIFT) 82*4882a593Smuzhiyun #define MPHY_ACBDLR9 (0x019 << MPHY_SHIFT) 83*4882a593Smuzhiyun #define MPHY_ACIOCR0 (0x01A << MPHY_SHIFT) 84*4882a593Smuzhiyun #define MPHY_ACIOCR1 (0x01B << MPHY_SHIFT) 85*4882a593Smuzhiyun #define MPHY_ACIOCR2 (0x01C << MPHY_SHIFT) 86*4882a593Smuzhiyun #define MPHY_ACIOCR3 (0x01D << MPHY_SHIFT) 87*4882a593Smuzhiyun #define MPHY_ACIOCR4 (0x01E << MPHY_SHIFT) 88*4882a593Smuzhiyun #define MPHY_ACIOCR5 (0x01F << MPHY_SHIFT) 89*4882a593Smuzhiyun #define MPHY_DXCCR (0x020 << MPHY_SHIFT) 90*4882a593Smuzhiyun #define MPHY_DSGCR (0x021 << MPHY_SHIFT) 91*4882a593Smuzhiyun #define MPHY_DCR (0x022 << MPHY_SHIFT) 92*4882a593Smuzhiyun #define MPHY_DTPR0 (0x023 << MPHY_SHIFT) 93*4882a593Smuzhiyun #define MPHY_DTPR1 (0x024 << MPHY_SHIFT) 94*4882a593Smuzhiyun #define MPHY_DTPR2 (0x025 << MPHY_SHIFT) 95*4882a593Smuzhiyun #define MPHY_DTPR3 (0x026 << MPHY_SHIFT) 96*4882a593Smuzhiyun #define MPHY_MR0 (0x027 << MPHY_SHIFT) 97*4882a593Smuzhiyun #define MPHY_MR1 (0x028 << MPHY_SHIFT) 98*4882a593Smuzhiyun #define MPHY_MR2 (0x029 << MPHY_SHIFT) 99*4882a593Smuzhiyun #define MPHY_MR3 (0x02A << MPHY_SHIFT) 100*4882a593Smuzhiyun #define MPHY_ODTCR (0x02B << MPHY_SHIFT) 101*4882a593Smuzhiyun #define MPHY_DTCR (0x02C << MPHY_SHIFT) 102*4882a593Smuzhiyun #define MPHY_DTCR_RANKEN_SHIFT 24 /* Rank Enable */ 103*4882a593Smuzhiyun #define MPHY_DTCR_RANKEN_MASK (0xf << (MPHY_DTCR_RANKEN_SHIFT)) 104*4882a593Smuzhiyun #define MPHY_DTAR0 (0x02D << MPHY_SHIFT) 105*4882a593Smuzhiyun #define MPHY_DTAR1 (0x02E << MPHY_SHIFT) 106*4882a593Smuzhiyun #define MPHY_DTAR2 (0x02F << MPHY_SHIFT) 107*4882a593Smuzhiyun #define MPHY_DTAR3 (0x030 << MPHY_SHIFT) 108*4882a593Smuzhiyun #define MPHY_DTDR0 (0x031 << MPHY_SHIFT) 109*4882a593Smuzhiyun #define MPHY_DTDR1 (0x032 << MPHY_SHIFT) 110*4882a593Smuzhiyun #define MPHY_DTEDR0 (0x033 << MPHY_SHIFT) 111*4882a593Smuzhiyun #define MPHY_DTEDR1 (0x034 << MPHY_SHIFT) 112*4882a593Smuzhiyun #define MPHY_ZQCR (0x090 << MPHY_SHIFT) 113*4882a593Smuzhiyun #define MPHY_ZQCR_AVGEN BIT(16) /* Average Algorithm */ 114*4882a593Smuzhiyun #define MPHY_ZQCR_FORCE_ZCAL_VT_UPDATE BIT(27) /* force VT update */ 115*4882a593Smuzhiyun /* ZQ */ 116*4882a593Smuzhiyun #define MPHY_ZQ_BASE (0x091 << MPHY_SHIFT) 117*4882a593Smuzhiyun #define MPHY_ZQ_STRIDE (0x004 << MPHY_SHIFT) 118*4882a593Smuzhiyun #define MPHY_ZQ_PR (0x000 << MPHY_SHIFT) 119*4882a593Smuzhiyun #define MPHY_ZQ_DR (0x001 << MPHY_SHIFT) 120*4882a593Smuzhiyun #define MPHY_ZQ_SR (0x002 << MPHY_SHIFT) 121*4882a593Smuzhiyun /* DATX8 */ 122*4882a593Smuzhiyun #define MPHY_DX_BASE (0x0A0 << MPHY_SHIFT) 123*4882a593Smuzhiyun #define MPHY_DX_STRIDE (0x020 << MPHY_SHIFT) 124*4882a593Smuzhiyun #define MPHY_DX_GCR0 (0x000 << MPHY_SHIFT) 125*4882a593Smuzhiyun #define MPHY_DX_GCR0_WLRKEN_SHIFT 26 /* Write Level Rank Enable */ 126*4882a593Smuzhiyun #define MPHY_DX_GCR0_WLRKEN_MASK (0xf << (MPHY_DX_GCR0_WLRKEN_SHIFT)) 127*4882a593Smuzhiyun #define MPHY_DX_GCR1 (0x001 << MPHY_SHIFT) 128*4882a593Smuzhiyun #define MPHY_DX_GCR2 (0x002 << MPHY_SHIFT) 129*4882a593Smuzhiyun #define MPHY_DX_GCR3 (0x003 << MPHY_SHIFT) 130*4882a593Smuzhiyun #define MPHY_DX_GSR0 (0x004 << MPHY_SHIFT) 131*4882a593Smuzhiyun #define MPHY_DX_GSR1 (0x005 << MPHY_SHIFT) 132*4882a593Smuzhiyun #define MPHY_DX_GSR2 (0x006 << MPHY_SHIFT) 133*4882a593Smuzhiyun #define MPHY_DX_BDLR0 (0x007 << MPHY_SHIFT) 134*4882a593Smuzhiyun #define MPHY_DX_BDLR1 (0x008 << MPHY_SHIFT) 135*4882a593Smuzhiyun #define MPHY_DX_BDLR2 (0x009 << MPHY_SHIFT) 136*4882a593Smuzhiyun #define MPHY_DX_BDLR3 (0x00A << MPHY_SHIFT) 137*4882a593Smuzhiyun #define MPHY_DX_BDLR4 (0x00B << MPHY_SHIFT) 138*4882a593Smuzhiyun #define MPHY_DX_BDLR5 (0x00C << MPHY_SHIFT) 139*4882a593Smuzhiyun #define MPHY_DX_BDLR6 (0x00D << MPHY_SHIFT) 140*4882a593Smuzhiyun #define MPHY_DX_LCDLR0 (0x00E << MPHY_SHIFT) 141*4882a593Smuzhiyun #define MPHY_DX_LCDLR1 (0x00F << MPHY_SHIFT) 142*4882a593Smuzhiyun #define MPHY_DX_LCDLR2 (0x010 << MPHY_SHIFT) 143*4882a593Smuzhiyun #define MPHY_DX_MDLR (0x011 << MPHY_SHIFT) 144*4882a593Smuzhiyun #define MPHY_DX_GTR (0x012 << MPHY_SHIFT) 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun #endif /* UNIPHIER_DDRMPHY_REGS_H */ 147