1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun #ifndef __WCD9335_H__ 4*4882a593Smuzhiyun #define __WCD9335_H__ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun /* 7*4882a593Smuzhiyun * WCD9335 register base can change according to the mode it works in. 8*4882a593Smuzhiyun * In slimbus mode the reg base starts from 0x800. 9*4882a593Smuzhiyun * In i2s/i2c mode the reg base is 0x0. 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun #define WCD9335_REG(pg, r) ((pg << 8) | (r)) 12*4882a593Smuzhiyun #define WCD9335_REG_OFFSET(r) (r & 0xFF) 13*4882a593Smuzhiyun #define WCD9335_PAGE_OFFSET(r) ((r >> 8) & 0xFF) 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* Page-0 Registers */ 16*4882a593Smuzhiyun #define WCD9335_PAGE0_PAGE_REGISTER WCD9335_REG(0x00, 0x000) 17*4882a593Smuzhiyun #define WCD9335_CODEC_RPM_CLK_GATE WCD9335_REG(0x00, 0x002) 18*4882a593Smuzhiyun #define WCD9335_CODEC_RPM_CLK_GATE_MCLK_GATE_MASK GENMASK(1, 0) 19*4882a593Smuzhiyun #define WCD9335_CODEC_RPM_CLK_MCLK_CFG WCD9335_REG(0x00, 0x003) 20*4882a593Smuzhiyun #define WCD9335_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ BIT(0) 21*4882a593Smuzhiyun #define WCD9335_CODEC_RPM_CLK_MCLK_CFG_12P288MHZ BIT(0) 22*4882a593Smuzhiyun #define WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK GENMASK(1, 0) 23*4882a593Smuzhiyun #define WCD9335_CODEC_RPM_RST_CTL WCD9335_REG(0x00, 0x009) 24*4882a593Smuzhiyun #define WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL WCD9335_REG(0x00, 0x011) 25*4882a593Smuzhiyun #define WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE0 WCD9335_REG(0x00, 0x021) 26*4882a593Smuzhiyun #define WCD9335_CHIP_TIER_CTRL_EFUSE_CTL WCD9335_REG(0x00, 0x025) 27*4882a593Smuzhiyun #define WCD9335_CHIP_TIER_CTRL_EFUSE_SSTATE_MASK GENMASK(4, 1) 28*4882a593Smuzhiyun #define WCD9335_CHIP_TIER_CTRL_EFUSE_EN_MASK BIT(0) 29*4882a593Smuzhiyun #define WCD9335_CHIP_TIER_CTRL_EFUSE_ENABLE BIT(0) 30*4882a593Smuzhiyun #define WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT0 WCD9335_REG(0x00, 0x029) 31*4882a593Smuzhiyun #define WCD9335_CHIP_TIER_CTRL_EFUSE_STATUS WCD9335_REG(0x00, 0x039) 32*4882a593Smuzhiyun #define WCD9335_INTR_CFG WCD9335_REG(0x00, 0x081) 33*4882a593Smuzhiyun #define WCD9335_INTR_CLR_COMMIT WCD9335_REG(0x00, 0x082) 34*4882a593Smuzhiyun #define WCD9335_INTR_PIN1_MASK0 WCD9335_REG(0x00, 0x089) 35*4882a593Smuzhiyun #define WCD9335_INTR_PIN1_MASK1 WCD9335_REG(0x00, 0x08a) 36*4882a593Smuzhiyun #define WCD9335_INTR_PIN1_MASK2 WCD9335_REG(0x00, 0x08b) 37*4882a593Smuzhiyun #define WCD9335_INTR_PIN1_MASK3 WCD9335_REG(0x00, 0x08c) 38*4882a593Smuzhiyun #define WCD9335_INTR_PIN1_STATUS0 WCD9335_REG(0x00, 0x091) 39*4882a593Smuzhiyun #define WCD9335_INTR_PIN1_STATUS1 WCD9335_REG(0x00, 0x092) 40*4882a593Smuzhiyun #define WCD9335_INTR_PIN1_STATUS2 WCD9335_REG(0x00, 0x093) 41*4882a593Smuzhiyun #define WCD9335_INTR_PIN1_STATUS3 WCD9335_REG(0x00, 0x094) 42*4882a593Smuzhiyun #define WCD9335_INTR_PIN1_CLEAR0 WCD9335_REG(0x00, 0x099) 43*4882a593Smuzhiyun #define WCD9335_INTR_PIN1_CLEAR1 WCD9335_REG(0x00, 0x09a) 44*4882a593Smuzhiyun #define WCD9335_INTR_PIN1_CLEAR2 WCD9335_REG(0x00, 0x09b) 45*4882a593Smuzhiyun #define WCD9335_INTR_PIN1_CLEAR3 WCD9335_REG(0x00, 0x09c) 46*4882a593Smuzhiyun #define WCD9335_INTR_PIN2_MASK0 WCD9335_REG(0x00, 0x0a1) 47*4882a593Smuzhiyun #define WCD9335_INTR_PIN2_MASK1 WCD9335_REG(0x00, 0x0a2) 48*4882a593Smuzhiyun #define WCD9335_INTR_PIN2_MASK2 WCD9335_REG(0x00, 0x0a3) 49*4882a593Smuzhiyun #define WCD9335_INTR_PIN2_MASK3 WCD9335_REG(0x00, 0x0a4) 50*4882a593Smuzhiyun #define WCD9335_INTR_PIN2_STATUS0 WCD9335_REG(0x00, 0x0a9) 51*4882a593Smuzhiyun #define WCD9335_INTR_PIN2_STATUS1 WCD9335_REG(0x00, 0x0aa) 52*4882a593Smuzhiyun #define WCD9335_INTR_PIN2_STATUS2 WCD9335_REG(0x00, 0x0ab) 53*4882a593Smuzhiyun #define WCD9335_INTR_PIN2_STATUS3 WCD9335_REG(0x00, 0x0ac) 54*4882a593Smuzhiyun #define WCD9335_INTR_PIN2_CLEAR0 WCD9335_REG(0x00, 0x0b1) 55*4882a593Smuzhiyun #define WCD9335_INTR_PIN2_CLEAR1 WCD9335_REG(0x00, 0x0b2) 56*4882a593Smuzhiyun #define WCD9335_INTR_PIN2_CLEAR2 WCD9335_REG(0x00, 0x0b3) 57*4882a593Smuzhiyun #define WCD9335_INTR_PIN2_CLEAR3 WCD9335_REG(0x00, 0x0b4) 58*4882a593Smuzhiyun #define WCD9335_INTR_LEVEL0 WCD9335_REG(0x00, 0x0e1) 59*4882a593Smuzhiyun #define WCD9335_INTR_LEVEL1 WCD9335_REG(0x00, 0x0e2) 60*4882a593Smuzhiyun #define WCD9335_INTR_LEVEL2 WCD9335_REG(0x00, 0x0e3) 61*4882a593Smuzhiyun #define WCD9335_INTR_LEVEL3 WCD9335_REG(0x00, 0x0e4) 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* Page-1 Registers */ 64*4882a593Smuzhiyun #define WCD9335_CPE_FLL_USER_CTL_0 WCD9335_REG(0x01, 0x001) 65*4882a593Smuzhiyun #define WCD9335_CPE_FLL_USER_CTL_1 WCD9335_REG(0x01, 0x002) 66*4882a593Smuzhiyun #define WCD9335_CPE_FLL_USER_CTL_2 WCD9335_REG(0x01, 0x003) 67*4882a593Smuzhiyun #define WCD9335_CPE_FLL_USER_CTL_3 WCD9335_REG(0x01, 0x004) 68*4882a593Smuzhiyun #define WCD9335_CPE_FLL_USER_CTL_4 WCD9335_REG(0x01, 0x005) 69*4882a593Smuzhiyun #define WCD9335_CPE_FLL_USER_CTL_5 WCD9335_REG(0x01, 0x006) 70*4882a593Smuzhiyun #define WCD9335_CPE_FLL_USER_CTL_6 WCD9335_REG(0x01, 0x007) 71*4882a593Smuzhiyun #define WCD9335_CPE_FLL_USER_CTL_7 WCD9335_REG(0x01, 0x008) 72*4882a593Smuzhiyun #define WCD9335_CPE_FLL_USER_CTL_8 WCD9335_REG(0x01, 0x009) 73*4882a593Smuzhiyun #define WCD9335_CPE_FLL_USER_CTL_9 WCD9335_REG(0x01, 0x00a) 74*4882a593Smuzhiyun #define WCD9335_CPE_FLL_L_VAL_CTL_0 WCD9335_REG(0x01, 0x00b) 75*4882a593Smuzhiyun #define WCD9335_CPE_FLL_L_VAL_CTL_1 WCD9335_REG(0x01, 0x00c) 76*4882a593Smuzhiyun #define WCD9335_CPE_FLL_DSM_FRAC_CTL_0 WCD9335_REG(0x01, 0x00d) 77*4882a593Smuzhiyun #define WCD9335_CPE_FLL_DSM_FRAC_CTL_1 WCD9335_REG(0x01, 0x00e) 78*4882a593Smuzhiyun #define WCD9335_CPE_FLL_CONFIG_CTL_0 WCD9335_REG(0x01, 0x00f) 79*4882a593Smuzhiyun #define WCD9335_CPE_FLL_CONFIG_CTL_1 WCD9335_REG(0x01, 0x010) 80*4882a593Smuzhiyun #define WCD9335_CPE_FLL_CONFIG_CTL_2 WCD9335_REG(0x01, 0x011) 81*4882a593Smuzhiyun #define WCD9335_CPE_FLL_CONFIG_CTL_3 WCD9335_REG(0x01, 0x012) 82*4882a593Smuzhiyun #define WCD9335_CPE_FLL_CONFIG_CTL_4 WCD9335_REG(0x01, 0x013) 83*4882a593Smuzhiyun #define WCD9335_CPE_FLL_TEST_CTL_0 WCD9335_REG(0x01, 0x014) 84*4882a593Smuzhiyun #define WCD9335_CPE_FLL_TEST_CTL_1 WCD9335_REG(0x01, 0x015) 85*4882a593Smuzhiyun #define WCD9335_CPE_FLL_TEST_CTL_2 WCD9335_REG(0x01, 0x016) 86*4882a593Smuzhiyun #define WCD9335_CPE_FLL_TEST_CTL_3 WCD9335_REG(0x01, 0x017) 87*4882a593Smuzhiyun #define WCD9335_CPE_FLL_TEST_CTL_4 WCD9335_REG(0x01, 0x018) 88*4882a593Smuzhiyun #define WCD9335_CPE_FLL_TEST_CTL_5 WCD9335_REG(0x01, 0x019) 89*4882a593Smuzhiyun #define WCD9335_CPE_FLL_TEST_CTL_6 WCD9335_REG(0x01, 0x01a) 90*4882a593Smuzhiyun #define WCD9335_CPE_FLL_TEST_CTL_7 WCD9335_REG(0x01, 0x01b) 91*4882a593Smuzhiyun #define WCD9335_CPE_FLL_FREQ_CTL_0 WCD9335_REG(0x01, 0x01c) 92*4882a593Smuzhiyun #define WCD9335_CPE_FLL_FREQ_CTL_1 WCD9335_REG(0x01, 0x01d) 93*4882a593Smuzhiyun #define WCD9335_CPE_FLL_FREQ_CTL_2 WCD9335_REG(0x01, 0x01e) 94*4882a593Smuzhiyun #define WCD9335_CPE_FLL_FREQ_CTL_3 WCD9335_REG(0x01, 0x01f) 95*4882a593Smuzhiyun #define WCD9335_CPE_FLL_SSC_CTL_0 WCD9335_REG(0x01, 0x020) 96*4882a593Smuzhiyun #define WCD9335_CPE_FLL_SSC_CTL_1 WCD9335_REG(0x01, 0x021) 97*4882a593Smuzhiyun #define WCD9335_CPE_FLL_SSC_CTL_2 WCD9335_REG(0x01, 0x022) 98*4882a593Smuzhiyun #define WCD9335_CPE_FLL_SSC_CTL_3 WCD9335_REG(0x01, 0x023) 99*4882a593Smuzhiyun #define WCD9335_CPE_FLL_FLL_MODE WCD9335_REG(0x01, 0x024) 100*4882a593Smuzhiyun #define WCD9335_CPE_FLL_STATUS_0 WCD9335_REG(0x01, 0x025) 101*4882a593Smuzhiyun #define WCD9335_CPE_FLL_STATUS_1 WCD9335_REG(0x01, 0x026) 102*4882a593Smuzhiyun #define WCD9335_CPE_FLL_STATUS_2 WCD9335_REG(0x01, 0x027) 103*4882a593Smuzhiyun #define WCD9335_CPE_FLL_STATUS_3 WCD9335_REG(0x01, 0x028) 104*4882a593Smuzhiyun #define WCD9335_I2S_FLL_USER_CTL_0 WCD9335_REG(0x01, 0x041) 105*4882a593Smuzhiyun #define WCD9335_I2S_FLL_USER_CTL_1 WCD9335_REG(0x01, 0x042) 106*4882a593Smuzhiyun #define WCD9335_I2S_FLL_USER_CTL_2 WCD9335_REG(0x01, 0x043) 107*4882a593Smuzhiyun #define WCD9335_I2S_FLL_USER_CTL_3 WCD9335_REG(0x01, 0x044) 108*4882a593Smuzhiyun #define WCD9335_I2S_FLL_USER_CTL_4 WCD9335_REG(0x01, 0x045) 109*4882a593Smuzhiyun #define WCD9335_I2S_FLL_USER_CTL_5 WCD9335_REG(0x01, 0x046) 110*4882a593Smuzhiyun #define WCD9335_I2S_FLL_USER_CTL_6 WCD9335_REG(0x01, 0x047) 111*4882a593Smuzhiyun #define WCD9335_I2S_FLL_USER_CTL_7 WCD9335_REG(0x01, 0x048) 112*4882a593Smuzhiyun #define WCD9335_I2S_FLL_USER_CTL_8 WCD9335_REG(0x01, 0x049) 113*4882a593Smuzhiyun #define WCD9335_I2S_FLL_USER_CTL_9 WCD9335_REG(0x01, 0x04a) 114*4882a593Smuzhiyun #define WCD9335_I2S_FLL_L_VAL_CTL_0 WCD9335_REG(0x01, 0x04b) 115*4882a593Smuzhiyun #define WCD9335_I2S_FLL_L_VAL_CTL_1 WCD9335_REG(0x01, 0x04c) 116*4882a593Smuzhiyun #define WCD9335_I2S_FLL_DSM_FRAC_CTL_0 WCD9335_REG(0x01, 0x04d) 117*4882a593Smuzhiyun #define WCD9335_I2S_FLL_DSM_FRAC_CTL_1 WCD9335_REG(0x01, 0x04e) 118*4882a593Smuzhiyun #define WCD9335_I2S_FLL_CONFIG_CTL_0 WCD9335_REG(0x01, 0x04f) 119*4882a593Smuzhiyun #define WCD9335_I2S_FLL_CONFIG_CTL_1 WCD9335_REG(0x01, 0x050) 120*4882a593Smuzhiyun #define WCD9335_I2S_FLL_CONFIG_CTL_2 WCD9335_REG(0x01, 0x051) 121*4882a593Smuzhiyun #define WCD9335_I2S_FLL_CONFIG_CTL_3 WCD9335_REG(0x01, 0x052) 122*4882a593Smuzhiyun #define WCD9335_I2S_FLL_CONFIG_CTL_4 WCD9335_REG(0x01, 0x053) 123*4882a593Smuzhiyun #define WCD9335_I2S_FLL_TEST_CTL_0 WCD9335_REG(0x01, 0x054) 124*4882a593Smuzhiyun #define WCD9335_I2S_FLL_TEST_CTL_1 WCD9335_REG(0x01, 0x055) 125*4882a593Smuzhiyun #define WCD9335_I2S_FLL_TEST_CTL_2 WCD9335_REG(0x01, 0x056) 126*4882a593Smuzhiyun #define WCD9335_I2S_FLL_TEST_CTL_3 WCD9335_REG(0x01, 0x057) 127*4882a593Smuzhiyun #define WCD9335_I2S_FLL_TEST_CTL_4 WCD9335_REG(0x01, 0x058) 128*4882a593Smuzhiyun #define WCD9335_I2S_FLL_TEST_CTL_5 WCD9335_REG(0x01, 0x059) 129*4882a593Smuzhiyun #define WCD9335_I2S_FLL_TEST_CTL_6 WCD9335_REG(0x01, 0x05a) 130*4882a593Smuzhiyun #define WCD9335_I2S_FLL_TEST_CTL_7 WCD9335_REG(0x01, 0x05b) 131*4882a593Smuzhiyun #define WCD9335_I2S_FLL_FREQ_CTL_0 WCD9335_REG(0x01, 0x05c) 132*4882a593Smuzhiyun #define WCD9335_I2S_FLL_FREQ_CTL_1 WCD9335_REG(0x01, 0x05d) 133*4882a593Smuzhiyun #define WCD9335_I2S_FLL_FREQ_CTL_2 WCD9335_REG(0x01, 0x05e) 134*4882a593Smuzhiyun #define WCD9335_I2S_FLL_FREQ_CTL_3 WCD9335_REG(0x01, 0x05f) 135*4882a593Smuzhiyun #define WCD9335_I2S_FLL_SSC_CTL_0 WCD9335_REG(0x01, 0x060) 136*4882a593Smuzhiyun #define WCD9335_I2S_FLL_SSC_CTL_1 WCD9335_REG(0x01, 0x061) 137*4882a593Smuzhiyun #define WCD9335_I2S_FLL_SSC_CTL_2 WCD9335_REG(0x01, 0x062) 138*4882a593Smuzhiyun #define WCD9335_I2S_FLL_SSC_CTL_3 WCD9335_REG(0x01, 0x063) 139*4882a593Smuzhiyun #define WCD9335_I2S_FLL_FLL_MODE WCD9335_REG(0x01, 0x064) 140*4882a593Smuzhiyun #define WCD9335_I2S_FLL_STATUS_0 WCD9335_REG(0x01, 0x065) 141*4882a593Smuzhiyun #define WCD9335_I2S_FLL_STATUS_1 WCD9335_REG(0x01, 0x066) 142*4882a593Smuzhiyun #define WCD9335_I2S_FLL_STATUS_2 WCD9335_REG(0x01, 0x067) 143*4882a593Smuzhiyun #define WCD9335_I2S_FLL_STATUS_3 WCD9335_REG(0x01, 0x068) 144*4882a593Smuzhiyun #define WCD9335_SB_FLL_USER_CTL_0 WCD9335_REG(0x01, 0x081) 145*4882a593Smuzhiyun #define WCD9335_SB_FLL_USER_CTL_1 WCD9335_REG(0x01, 0x082) 146*4882a593Smuzhiyun #define WCD9335_SB_FLL_USER_CTL_2 WCD9335_REG(0x01, 0x083) 147*4882a593Smuzhiyun #define WCD9335_SB_FLL_USER_CTL_3 WCD9335_REG(0x01, 0x084) 148*4882a593Smuzhiyun #define WCD9335_SB_FLL_USER_CTL_4 WCD9335_REG(0x01, 0x085) 149*4882a593Smuzhiyun #define WCD9335_SB_FLL_USER_CTL_5 WCD9335_REG(0x01, 0x086) 150*4882a593Smuzhiyun #define WCD9335_SB_FLL_USER_CTL_6 WCD9335_REG(0x01, 0x087) 151*4882a593Smuzhiyun #define WCD9335_SB_FLL_USER_CTL_7 WCD9335_REG(0x01, 0x088) 152*4882a593Smuzhiyun #define WCD9335_SB_FLL_USER_CTL_8 WCD9335_REG(0x01, 0x089) 153*4882a593Smuzhiyun #define WCD9335_SB_FLL_USER_CTL_9 WCD9335_REG(0x01, 0x08a) 154*4882a593Smuzhiyun #define WCD9335_SB_FLL_L_VAL_CTL_0 WCD9335_REG(0x01, 0x08b) 155*4882a593Smuzhiyun #define WCD9335_SB_FLL_L_VAL_CTL_1 WCD9335_REG(0x01, 0x08c) 156*4882a593Smuzhiyun #define WCD9335_SB_FLL_DSM_FRAC_CTL_0 WCD9335_REG(0x01, 0x08d) 157*4882a593Smuzhiyun #define WCD9335_SB_FLL_DSM_FRAC_CTL_1 WCD9335_REG(0x01, 0x08e) 158*4882a593Smuzhiyun #define WCD9335_SB_FLL_CONFIG_CTL_0 WCD9335_REG(0x01, 0x08f) 159*4882a593Smuzhiyun #define WCD9335_SB_FLL_CONFIG_CTL_1 WCD9335_REG(0x01, 0x090) 160*4882a593Smuzhiyun #define WCD9335_SB_FLL_CONFIG_CTL_2 WCD9335_REG(0x01, 0x091) 161*4882a593Smuzhiyun #define WCD9335_SB_FLL_CONFIG_CTL_3 WCD9335_REG(0x01, 0x092) 162*4882a593Smuzhiyun #define WCD9335_SB_FLL_CONFIG_CTL_4 WCD9335_REG(0x01, 0x093) 163*4882a593Smuzhiyun #define WCD9335_SB_FLL_TEST_CTL_0 WCD9335_REG(0x01, 0x094) 164*4882a593Smuzhiyun #define WCD9335_SB_FLL_TEST_CTL_1 WCD9335_REG(0x01, 0x095) 165*4882a593Smuzhiyun #define WCD9335_SB_FLL_TEST_CTL_2 WCD9335_REG(0x01, 0x096) 166*4882a593Smuzhiyun #define WCD9335_SB_FLL_TEST_CTL_3 WCD9335_REG(0x01, 0x097) 167*4882a593Smuzhiyun #define WCD9335_SB_FLL_TEST_CTL_4 WCD9335_REG(0x01, 0x098) 168*4882a593Smuzhiyun #define WCD9335_SB_FLL_TEST_CTL_5 WCD9335_REG(0x01, 0x099) 169*4882a593Smuzhiyun #define WCD9335_SB_FLL_TEST_CTL_6 WCD9335_REG(0x01, 0x09a) 170*4882a593Smuzhiyun #define WCD9335_SB_FLL_TEST_CTL_7 WCD9335_REG(0x01, 0x09b) 171*4882a593Smuzhiyun #define WCD9335_SB_FLL_FREQ_CTL_0 WCD9335_REG(0x01, 0x09c) 172*4882a593Smuzhiyun #define WCD9335_SB_FLL_FREQ_CTL_1 WCD9335_REG(0x01, 0x09d) 173*4882a593Smuzhiyun #define WCD9335_SB_FLL_FREQ_CTL_2 WCD9335_REG(0x01, 0x09e) 174*4882a593Smuzhiyun #define WCD9335_SB_FLL_FREQ_CTL_3 WCD9335_REG(0x01, 0x09f) 175*4882a593Smuzhiyun #define WCD9335_SB_FLL_SSC_CTL_0 WCD9335_REG(0x01, 0x0a0) 176*4882a593Smuzhiyun #define WCD9335_SB_FLL_SSC_CTL_1 WCD9335_REG(0x01, 0x0a1) 177*4882a593Smuzhiyun #define WCD9335_SB_FLL_SSC_CTL_2 WCD9335_REG(0x01, 0x0a2) 178*4882a593Smuzhiyun #define WCD9335_SB_FLL_SSC_CTL_3 WCD9335_REG(0x01, 0x0a3) 179*4882a593Smuzhiyun #define WCD9335_SB_FLL_FLL_MODE WCD9335_REG(0x01, 0x0a4) 180*4882a593Smuzhiyun #define WCD9335_SB_FLL_STATUS_0 WCD9335_REG(0x01, 0x0a5) 181*4882a593Smuzhiyun #define WCD9335_SB_FLL_STATUS_1 WCD9335_REG(0x01, 0x0a6) 182*4882a593Smuzhiyun #define WCD9335_SB_FLL_STATUS_2 WCD9335_REG(0x01, 0x0a7) 183*4882a593Smuzhiyun #define WCD9335_SB_FLL_STATUS_3 WCD9335_REG(0x01, 0x0a8) 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun /* Page-2 Registers */ 186*4882a593Smuzhiyun #define WCD9335_PAGE2_PAGE_REGISTER WCD9335_REG(0x02, 0x000) 187*4882a593Smuzhiyun #define WCD9335_CPE_SS_DMIC0_CTL WCD9335_REG(0x02, 0x063) 188*4882a593Smuzhiyun #define WCD9335_CPE_SS_DMIC1_CTL WCD9335_REG(0x02, 0x064) 189*4882a593Smuzhiyun #define WCD9335_CPE_SS_DMIC2_CTL WCD9335_REG(0x02, 0x065) 190*4882a593Smuzhiyun #define WCD9335_CPE_SS_DMIC_CFG WCD9335_REG(0x02, 0x066) 191*4882a593Smuzhiyun #define WCD9335_SOC_MAD_AUDIO_CTL_2 WCD9335_REG(0x02, 0x084) 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun /* Page-6 Registers */ 194*4882a593Smuzhiyun #define WCD9335_PAGE6_PAGE_REGISTER WCD9335_REG(0x06, 0x000) 195*4882a593Smuzhiyun #define WCD9335_ANA_BIAS WCD9335_REG(0x06, 0x001) 196*4882a593Smuzhiyun #define WCD9335_ANA_BIAS_EN_MASK BIT(7) 197*4882a593Smuzhiyun #define WCD9335_ANA_BIAS_ENABLE BIT(7) 198*4882a593Smuzhiyun #define WCD9335_ANA_BIAS_DISABLE 0 199*4882a593Smuzhiyun #define WCD9335_ANA_BIAS_PRECHRG_EN_MASK BIT(6) 200*4882a593Smuzhiyun #define WCD9335_ANA_BIAS_PRECHRG_ENABLE BIT(6) 201*4882a593Smuzhiyun #define WCD9335_ANA_BIAS_PRECHRG_DISABLE 0 202*4882a593Smuzhiyun #define WCD9335_ANA_BIAS_PRECHRG_CTL_MODE BIT(5) 203*4882a593Smuzhiyun #define WCD9335_ANA_BIAS_PRECHRG_CTL_MODE_AUTO BIT(5) 204*4882a593Smuzhiyun #define WCD9335_ANA_BIAS_PRECHRG_CTL_MODE_MANUAL 0 205*4882a593Smuzhiyun #define WCD9335_ANA_CLK_TOP WCD9335_REG(0x06, 0x002) 206*4882a593Smuzhiyun #define WCD9335_ANA_CLK_MCLK_EN_MASK BIT(2) 207*4882a593Smuzhiyun #define WCD9335_ANA_CLK_MCLK_ENABLE BIT(2) 208*4882a593Smuzhiyun #define WCD9335_ANA_CLK_MCLK_DISABLE 0 209*4882a593Smuzhiyun #define WCD9335_ANA_CLK_MCLK_SRC_MASK BIT(3) 210*4882a593Smuzhiyun #define WCD9335_ANA_CLK_MCLK_SRC_RCO BIT(3) 211*4882a593Smuzhiyun #define WCD9335_ANA_CLK_MCLK_SRC_EXTERNAL 0 212*4882a593Smuzhiyun #define WCD9335_ANA_CLK_EXT_CLKBUF_EN_MASK BIT(7) 213*4882a593Smuzhiyun #define WCD9335_ANA_CLK_EXT_CLKBUF_ENABLE BIT(7) 214*4882a593Smuzhiyun #define WCD9335_ANA_CLK_EXT_CLKBUF_DISABLE 0 215*4882a593Smuzhiyun #define WCD9335_ANA_RCO WCD9335_REG(0x06, 0x003) 216*4882a593Smuzhiyun #define WCD9335_ANA_RCO_BG_EN_MASK BIT(7) 217*4882a593Smuzhiyun #define WCD9335_ANA_RCO_BG_ENABLE BIT(7) 218*4882a593Smuzhiyun #define WCD9335_ANA_BUCK_VOUT_D WCD9335_REG(0x06, 0x005) 219*4882a593Smuzhiyun #define WCD9335_ANA_BUCK_VOUT_MASK GENMASK(7, 0) 220*4882a593Smuzhiyun #define WCD9335_ANA_BUCK_CTL WCD9335_REG(0x06, 0x006) 221*4882a593Smuzhiyun #define WCD9335_ANA_BUCK_CTL_VOUT_D_IREF_MASK BIT(1) 222*4882a593Smuzhiyun #define WCD9335_ANA_BUCK_CTL_VOUT_D_IREF_EXT BIT(1) 223*4882a593Smuzhiyun #define WCD9335_ANA_BUCK_CTL_VOUT_D_IREF_INT 0 224*4882a593Smuzhiyun #define WCD9335_ANA_BUCK_CTL_VOUT_D_VREF_MASK BIT(2) 225*4882a593Smuzhiyun #define WCD9335_ANA_BUCK_CTL_VOUT_D_VREF_EXT BIT(2) 226*4882a593Smuzhiyun #define WCD9335_ANA_BUCK_CTL_VOUT_D_VREF_INT 0 227*4882a593Smuzhiyun #define WCD9335_ANA_BUCK_CTL_RAMP_START_MASK BIT(7) 228*4882a593Smuzhiyun #define WCD9335_ANA_BUCK_CTL_RAMP_START_ENABLE BIT(7) 229*4882a593Smuzhiyun #define WCD9335_ANA_BUCK_CTL_RAMP_START_DISABLE 0 230*4882a593Smuzhiyun #define WCD9335_ANA_RX_SUPPLIES WCD9335_REG(0x06, 0x008) 231*4882a593Smuzhiyun #define WCD9335_ANA_RX_BIAS_ENABLE_MASK BIT(0) 232*4882a593Smuzhiyun #define WCD9335_ANA_RX_BIAS_ENABLE BIT(0) 233*4882a593Smuzhiyun #define WCD9335_ANA_RX_BIAS_DISABLE 0 234*4882a593Smuzhiyun #define WCD9335_ANA_HPH WCD9335_REG(0x06, 0x009) 235*4882a593Smuzhiyun #define WCD9335_ANA_EAR WCD9335_REG(0x06, 0x00a) 236*4882a593Smuzhiyun #define WCD9335_ANA_LO_1_2 WCD9335_REG(0x06, 0x00b) 237*4882a593Smuzhiyun #define WCD9335_ANA_LO_3_4 WCD9335_REG(0x06, 0x00c) 238*4882a593Smuzhiyun #define WCD9335_ANA_AMIC1 WCD9335_REG(0x06, 0x00e) 239*4882a593Smuzhiyun #define WCD9335_ANA_AMIC2 WCD9335_REG(0x06, 0x00f) 240*4882a593Smuzhiyun #define WCD9335_ANA_AMIC3 WCD9335_REG(0x06, 0x010) 241*4882a593Smuzhiyun #define WCD9335_ANA_AMIC4 WCD9335_REG(0x06, 0x011) 242*4882a593Smuzhiyun #define WCD9335_ANA_AMIC5 WCD9335_REG(0x06, 0x012) 243*4882a593Smuzhiyun #define WCD9335_ANA_AMIC6 WCD9335_REG(0x06, 0x013) 244*4882a593Smuzhiyun #define WCD9335_ANA_MBHC_MECH WCD9335_REG(0x06, 0x014) 245*4882a593Smuzhiyun #define WCD9335_MBHC_L_DET_EN_MASK BIT(7) 246*4882a593Smuzhiyun #define WCD9335_MBHC_L_DET_EN BIT(7) 247*4882a593Smuzhiyun #define WCD9335_MBHC_GND_DET_EN_MASK BIT(6) 248*4882a593Smuzhiyun #define WCD9335_MBHC_MECH_DETECT_TYPE_MASK BIT(5) 249*4882a593Smuzhiyun #define WCD9335_MBHC_MECH_DETECT_TYPE_SHIFT 5 250*4882a593Smuzhiyun #define WCD9335_MBHC_HPHL_PLUG_TYPE_MASK BIT(4) 251*4882a593Smuzhiyun #define WCD9335_MBHC_HPHL_PLUG_TYPE_NO BIT(4) 252*4882a593Smuzhiyun #define WCD9335_MBHC_GND_PLUG_TYPE_MASK BIT(3) 253*4882a593Smuzhiyun #define WCD9335_MBHC_GND_PLUG_TYPE_NO BIT(3) 254*4882a593Smuzhiyun #define WCD9335_MBHC_HSL_PULLUP_COMP_EN BIT(2) 255*4882a593Smuzhiyun #define WCD9335_MBHC_HPHL_100K_TO_GND_EN BIT(0) 256*4882a593Smuzhiyun 257*4882a593Smuzhiyun #define WCD9335_ANA_MBHC_ELECT WCD9335_REG(0x06, 0x015) 258*4882a593Smuzhiyun #define WCD9335_ANA_MBHC_BD_ISRC_CTL_MASK GENMASK(6, 4) 259*4882a593Smuzhiyun #define WCD9335_ANA_MBHC_BD_ISRC_100UA GENMASK(5, 4) 260*4882a593Smuzhiyun #define WCD9335_ANA_MBHC_BD_ISRC_OFF 0 261*4882a593Smuzhiyun #define WCD9335_ANA_MBHC_BIAS_EN_MASK BIT(0) 262*4882a593Smuzhiyun #define WCD9335_ANA_MBHC_BIAS_EN BIT(0) 263*4882a593Smuzhiyun #define WCD9335_ANA_MBHC_ZDET WCD9335_REG(0x06, 0x016) 264*4882a593Smuzhiyun #define WCD9335_ANA_MBHC_RESULT_1 WCD9335_REG(0x06, 0x017) 265*4882a593Smuzhiyun #define WCD9335_ANA_MBHC_RESULT_2 WCD9335_REG(0x06, 0x018) 266*4882a593Smuzhiyun #define WCD9335_ANA_MBHC_RESULT_3 WCD9335_REG(0x06, 0x019) 267*4882a593Smuzhiyun #define WCD9335_MBHC_BTN_RESULT_MASK GENMASK(2, 0) 268*4882a593Smuzhiyun #define WCD9335_ANA_MBHC_BTN0 WCD9335_REG(0x06, 0x01a) 269*4882a593Smuzhiyun #define WCD9335_ANA_MBHC_BTN1 WCD9335_REG(0x06, 0x01b) 270*4882a593Smuzhiyun #define WCD9335_ANA_MBHC_BTN2 WCD9335_REG(0x06, 0x01c) 271*4882a593Smuzhiyun #define WCD9335_ANA_MBHC_BTN3 WCD9335_REG(0x06, 0x01d) 272*4882a593Smuzhiyun #define WCD9335_ANA_MBHC_BTN4 WCD9335_REG(0x06, 0x01e) 273*4882a593Smuzhiyun #define WCD9335_ANA_MBHC_BTN5 WCD9335_REG(0x06, 0x01f) 274*4882a593Smuzhiyun #define WCD9335_ANA_MBHC_BTN6 WCD9335_REG(0x06, 0x020) 275*4882a593Smuzhiyun #define WCD9335_ANA_MBHC_BTN7 WCD9335_REG(0x06, 0x021) 276*4882a593Smuzhiyun #define WCD9335_ANA_MICB1 WCD9335_REG(0x06, 0x022) 277*4882a593Smuzhiyun #define WCD9335_ANA_MICB2 WCD9335_REG(0x06, 0x023) 278*4882a593Smuzhiyun #define WCD9335_ANA_MICB2_ENABLE BIT(6) 279*4882a593Smuzhiyun #define WCD9335_ANA_MICB2_RAMP WCD9335_REG(0x06, 0x024) 280*4882a593Smuzhiyun #define WCD9335_ANA_MICB3 WCD9335_REG(0x06, 0x025) 281*4882a593Smuzhiyun #define WCD9335_ANA_MICB4 WCD9335_REG(0x06, 0x026) 282*4882a593Smuzhiyun #define WCD9335_ANA_VBADC WCD9335_REG(0x06, 0x027) 283*4882a593Smuzhiyun #define WCD9335_BIAS_VBG_FINE_ADJ WCD9335_REG(0x06, 0x029) 284*4882a593Smuzhiyun #define WCD9335_RCO_CTRL_2 WCD9335_REG(0x06, 0x02f) 285*4882a593Smuzhiyun #define WCD9335_SIDO_SIDO_CCL_2 WCD9335_REG(0x06, 0x042) 286*4882a593Smuzhiyun #define WCD9335_SIDO_SIDO_CCL_4 WCD9335_REG(0x06, 0x044) 287*4882a593Smuzhiyun #define WCD9335_SIDO_SIDO_CCL_8 WCD9335_REG(0x06, 0x048) 288*4882a593Smuzhiyun #define WCD9335_SIDO_SIDO_CCL_10 WCD9335_REG(0x06, 0x04a) 289*4882a593Smuzhiyun #define WCD9335_SIDO_SIDO_CCL_10_ICHARG_PWR_SEL_C320FF 0x2 290*4882a593Smuzhiyun /* Comparator 1 and 2 Bias current at 1P0UA with start pulse width of C320FF */ 291*4882a593Smuzhiyun #define WCD9335_SIDO_SIDO_CCL_DEF_VALUE 0x6e 292*4882a593Smuzhiyun #define WCD9335_SIDO_SIDO_TEST_2 WCD9335_REG(0x06, 0x055) 293*4882a593Smuzhiyun #define WCD9335_MBHC_CTL_1 WCD9335_REG(0x06, 0x056) 294*4882a593Smuzhiyun #define WCD9335_MBHC_BTN_DBNC_MASK GENMASK(1, 0) 295*4882a593Smuzhiyun #define WCD9335_MBHC_BTN_DBNC_T_16_MS 0x2 296*4882a593Smuzhiyun #define WCD9335_MBHC_CTL_RCO_EN_MASK BIT(7) 297*4882a593Smuzhiyun #define WCD9335_MBHC_CTL_RCO_EN BIT(7) 298*4882a593Smuzhiyun 299*4882a593Smuzhiyun #define WCD9335_MBHC_CTL_2 WCD9335_REG(0x06, 0x057) 300*4882a593Smuzhiyun #define WCD9335_MBHC_HS_VREF_CTL_MASK GENMASK(1, 0) 301*4882a593Smuzhiyun #define WCD9335_MBHC_HS_VREF_1P5_V 0x1 302*4882a593Smuzhiyun #define WCD9335_MBHC_PLUG_DETECT_CTL WCD9335_REG(0x06, 0x058) 303*4882a593Smuzhiyun #define WCD9335_MBHC_HSDET_PULLUP_CTL_MASK GENMASK(7, 6) 304*4882a593Smuzhiyun #define WCD9335_MBHC_HSDET_PULLUP_CTL_SHIFT 6 305*4882a593Smuzhiyun #define WCD9335_MBHC_HSDET_PULLUP_CTL_1_2P0_UA 0x80 306*4882a593Smuzhiyun #define WCD9335_MBHC_DBNC_TIMER_INSREM_DBNC_T_96_MS 0x6 307*4882a593Smuzhiyun 308*4882a593Smuzhiyun #define WCD9335_MBHC_ZDET_RAMP_CTL WCD9335_REG(0x06, 0x05a) 309*4882a593Smuzhiyun #define WCD9335_VBADC_IBIAS_FE WCD9335_REG(0x06, 0x05e) 310*4882a593Smuzhiyun #define WCD9335_FLYBACK_CTRL_1 WCD9335_REG(0x06, 0x0b1) 311*4882a593Smuzhiyun #define WCD9335_RX_BIAS_HPH_PA WCD9335_REG(0x06, 0x0bb) 312*4882a593Smuzhiyun #define WCD9335_RX_BIAS_HPH_PA_AMP_5_UA_MASK GENMASK(3, 0) 313*4882a593Smuzhiyun #define WCD9335_RX_BIAS_HPH_RDACBUFF_CNP2 WCD9335_REG(0x06, 0x0bc) 314*4882a593Smuzhiyun #define WCD9335_RX_BIAS_HPH_RDAC_LDO WCD9335_REG(0x06, 0x0bd) 315*4882a593Smuzhiyun #define WCD9335_RX_BIAS_FLYB_BUFF WCD9335_REG(0x06, 0x0c7) 316*4882a593Smuzhiyun #define WCD9335_RX_BIAS_FLYB_VPOS_5_UA_MASK GENMASK(3, 0) 317*4882a593Smuzhiyun #define WCD9335_RX_BIAS_FLYB_I_0P0_UA 0 318*4882a593Smuzhiyun #define WCD9335_RX_BIAS_FLYB_VNEG_5_UA_MASK GENMASK(7, 4) 319*4882a593Smuzhiyun #define WCD9335_RX_BIAS_FLYB_MID_RST WCD9335_REG(0x06, 0x0c8) 320*4882a593Smuzhiyun #define WCD9335_HPH_CNP_WG_CTL WCD9335_REG(0x06, 0x0cc) 321*4882a593Smuzhiyun #define WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK GENMASK(2, 0) 322*4882a593Smuzhiyun #define WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500 0x2 323*4882a593Smuzhiyun #define WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000 0x3 324*4882a593Smuzhiyun #define WCD9335_HPH_OCP_CTL WCD9335_REG(0x06, 0x0ce) 325*4882a593Smuzhiyun #define WCD9335_HPH_AUTO_CHOP WCD9335_REG(0x06, 0x0cf) 326*4882a593Smuzhiyun #define WCD9335_HPH_AUTO_CHOP_MASK BIT(5) 327*4882a593Smuzhiyun #define WCD9335_HPH_AUTO_CHOP_FORCE_ENABLE BIT(5) 328*4882a593Smuzhiyun #define WCD9335_HPH_AUTO_CHOP_ENABLE_BY_CMPDR_GAIN 0 329*4882a593Smuzhiyun #define WCD9335_HPH_PA_CTL1 WCD9335_REG(0x06, 0x0d1) 330*4882a593Smuzhiyun #define WCD9335_HPH_PA_GM3_IB_SCALE_MASK GENMASK(3, 1) 331*4882a593Smuzhiyun #define WCD9335_HPH_PA_CTL2 WCD9335_REG(0x06, 0x0d2) 332*4882a593Smuzhiyun #define WCD9335_HPH_PA_CTL2_FORCE_PSRREH_MASK BIT(2) 333*4882a593Smuzhiyun #define WCD9335_HPH_PA_CTL2_FORCE_PSRREH_ENABLE BIT(2) 334*4882a593Smuzhiyun #define WCD9335_HPH_PA_CTL2_FORCE_PSRREH_DISABLE 0 335*4882a593Smuzhiyun #define WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK BIT(3) 336*4882a593Smuzhiyun #define WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE BIT(3) 337*4882a593Smuzhiyun #define WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE 0 338*4882a593Smuzhiyun #define WCD9335_HPH_PA_CTL2_HPH_PSRR_ENH_MASK BIT(5) 339*4882a593Smuzhiyun #define WCD9335_HPH_PA_CTL2_HPH_PSRR_ENABLE BIT(5) 340*4882a593Smuzhiyun #define WCD9335_HPH_PA_CTL2_HPH_PSRR_DISABLE 0 341*4882a593Smuzhiyun #define WCD9335_HPH_L_EN WCD9335_REG(0x06, 0x0d3) 342*4882a593Smuzhiyun #define WCD9335_HPH_CONST_SEL_L_MASK GENMASK(7, 6) 343*4882a593Smuzhiyun #define WCD9335_HPH_CONST_SEL_L_BYPASS 0 344*4882a593Smuzhiyun #define WCD9335_HPH_CONST_SEL_L_LP_PATH 0x40 345*4882a593Smuzhiyun #define WCD9335_HPH_CONST_SEL_L_HQ_PATH 0x80 346*4882a593Smuzhiyun #define WCD9335_HPH_PA_GAIN_MASK GENMASK(4, 0) 347*4882a593Smuzhiyun #define WCD9335_HPH_GAIN_SRC_SEL_MASK BIT(5) 348*4882a593Smuzhiyun #define WCD9335_HPH_GAIN_SRC_SEL_COMPANDER 0 349*4882a593Smuzhiyun #define WCD9335_HPH_GAIN_SRC_SEL_REGISTER BIT(5) 350*4882a593Smuzhiyun #define WCD9335_HPH_L_TEST WCD9335_REG(0x06, 0x0d4) 351*4882a593Smuzhiyun #define WCD9335_HPH_R_EN WCD9335_REG(0x06, 0x0d6) 352*4882a593Smuzhiyun #define WCD9335_HPH_R_TEST WCD9335_REG(0x06, 0x0d7) 353*4882a593Smuzhiyun #define WCD9335_HPH_R_ATEST WCD9335_REG(0x06, 0x0d8) 354*4882a593Smuzhiyun #define WCD9335_HPH_RDAC_LDO_CTL WCD9335_REG(0x06, 0x0db) 355*4882a593Smuzhiyun #define WCD9335_HPH_RDAC_N1P65_LD_OUTCTL_MASK GENMASK(2, 0) 356*4882a593Smuzhiyun #define WCD9335_HPH_RDAC_N1P65_LD_OUTCTL_V_N1P60 0x1 357*4882a593Smuzhiyun #define WCD9335_HPH_RDAC_1P65_LD_OUTCTL_MASK GENMASK(6, 4) 358*4882a593Smuzhiyun #define WCD9335_HPH_RDAC_1P65_LD_OUTCTL_V_N1P60 0x10 359*4882a593Smuzhiyun #define WCD9335_HPH_REFBUFF_LP_CTL WCD9335_REG(0x06, 0x0de) 360*4882a593Smuzhiyun #define WCD9335_HPH_L_DAC_CTL WCD9335_REG(0x06, 0x0df) 361*4882a593Smuzhiyun #define WCD9335_HPH_DAC_LDO_POWERMODE_MASK BIT(0) 362*4882a593Smuzhiyun #define WCD9335_HPH_DAC_LDO_POWERMODE_LOWPOWER 0 363*4882a593Smuzhiyun #define WCD9335_HPH_DAC_LDO_POWERMODE_UHQA BIT(0) 364*4882a593Smuzhiyun #define WCD9335_HPH_DAC_LDO_UHQA_OV_MASK BIT(1) 365*4882a593Smuzhiyun #define WCD9335_HPH_DAC_LDO_UHQA_OV_ENABLE BIT(1) 366*4882a593Smuzhiyun #define WCD9335_HPH_DAC_LDO_UHQA_OV_DISABLE 0 367*4882a593Smuzhiyun 368*4882a593Smuzhiyun #define WCD9335_EAR_CMBUFF WCD9335_REG(0x06, 0x0e2) 369*4882a593Smuzhiyun #define WCD9335_DIFF_LO_LO2_COMPANDER WCD9335_REG(0x06, 0x0ea) 370*4882a593Smuzhiyun #define WCD9335_DIFF_LO_LO1_COMPANDER WCD9335_REG(0x06, 0x0eb) 371*4882a593Smuzhiyun #define WCD9335_DIFF_LO_COM_SWCAP_REFBUF_FREQ WCD9335_REG(0x06, 0x0f1) 372*4882a593Smuzhiyun #define WCD9335_DIFF_LO_COM_PA_FREQ WCD9335_REG(0x06, 0x0f2) 373*4882a593Smuzhiyun #define WCD9335_SE_LO_LO3_GAIN WCD9335_REG(0x06, 0x0f8) 374*4882a593Smuzhiyun #define WCD9335_SE_LO_LO3_CTRL WCD9335_REG(0x06, 0x0f9) 375*4882a593Smuzhiyun #define WCD9335_SE_LO_LO4_GAIN WCD9335_REG(0x06, 0x0fa) 376*4882a593Smuzhiyun 377*4882a593Smuzhiyun /* Page-10 Registers */ 378*4882a593Smuzhiyun #define WCD9335_CDC_TX0_TX_PATH_CTL WCD9335_REG(0x0a, 0x031) 379*4882a593Smuzhiyun #define WCD9335_CDC_TX_PATH_CTL_PCM_RATE_MASK GENMASK(3, 0) 380*4882a593Smuzhiyun #define WCD9335_CDC_TX_PATH_CTL(dec) WCD9335_REG(0xa, (0x31 + dec * 0x10)) 381*4882a593Smuzhiyun #define WCD9335_CDC_TX0_TX_PATH_CFG0 WCD9335_REG(0x0a, 0x032) 382*4882a593Smuzhiyun #define WCD9335_CDC_TX_ADC_AMIC_DMIC_SEL_MASK BIT(7) 383*4882a593Smuzhiyun #define WCD9335_CDC_TX_ADC_DMIC_SEL BIT(7) 384*4882a593Smuzhiyun #define WCD9335_CDC_TX_ADC_AMIC_SEL 0 385*4882a593Smuzhiyun #define WCD9335_CDC_TX0_TX_VOL_CTL WCD9335_REG(0x0a, 0x034) 386*4882a593Smuzhiyun #define WCD9335_CDC_TX0_TX_PATH_SEC2 WCD9335_REG(0x0a, 0x039) 387*4882a593Smuzhiyun #define WCD9335_CDC_TX0_TX_PATH_SEC7 WCD9335_REG(0x0a, 0x03e) 388*4882a593Smuzhiyun #define WCD9335_CDC_TX1_TX_PATH_CTL WCD9335_REG(0x0a, 0x041) 389*4882a593Smuzhiyun #define WCD9335_CDC_TX1_TX_PATH_CFG0 WCD9335_REG(0x0a, 0x042) 390*4882a593Smuzhiyun #define WCD9335_CDC_TX2_TX_PATH_CTL WCD9335_REG(0x0a, 0x051) 391*4882a593Smuzhiyun #define WCD9335_CDC_TX2_TX_PATH_CFG0 WCD9335_REG(0x0a, 0x052) 392*4882a593Smuzhiyun #define WCD9335_CDC_TX2_TX_VOL_CTL WCD9335_REG(0x0a, 0x054) 393*4882a593Smuzhiyun #define WCD9335_CDC_TX3_TX_PATH_CTL WCD9335_REG(0x0a, 0x061) 394*4882a593Smuzhiyun #define WCD9335_CDC_TX3_TX_PATH_CFG0 WCD9335_REG(0x0a, 0x062) 395*4882a593Smuzhiyun #define WCD9335_CDC_TX3_TX_VOL_CTL WCD9335_REG(0x0a, 0x064) 396*4882a593Smuzhiyun #define WCD9335_CDC_TX4_TX_PATH_CTL WCD9335_REG(0x0a, 0x071) 397*4882a593Smuzhiyun #define WCD9335_CDC_TX4_TX_PATH_CFG0 WCD9335_REG(0x0a, 0x072) 398*4882a593Smuzhiyun #define WCD9335_CDC_TX4_TX_VOL_CTL WCD9335_REG(0x0a, 0x074) 399*4882a593Smuzhiyun #define WCD9335_CDC_TX5_TX_PATH_CTL WCD9335_REG(0x0a, 0x081) 400*4882a593Smuzhiyun #define WCD9335_CDC_TX5_TX_PATH_CFG0 WCD9335_REG(0x0a, 0x082) 401*4882a593Smuzhiyun #define WCD9335_CDC_TX5_TX_VOL_CTL WCD9335_REG(0x0a, 0x084) 402*4882a593Smuzhiyun #define WCD9335_CDC_TX6_TX_PATH_CTL WCD9335_REG(0x0a, 0x091) 403*4882a593Smuzhiyun #define WCD9335_CDC_TX6_TX_PATH_CFG0 WCD9335_REG(0x0a, 0x092) 404*4882a593Smuzhiyun #define WCD9335_CDC_TX6_TX_VOL_CTL WCD9335_REG(0x0a, 0x094) 405*4882a593Smuzhiyun #define WCD9335_CDC_TX7_TX_PATH_CTL WCD9335_REG(0x0a, 0x0a1) 406*4882a593Smuzhiyun #define WCD9335_CDC_TX7_TX_PATH_CFG0 WCD9335_REG(0x0a, 0x0a2) 407*4882a593Smuzhiyun #define WCD9335_CDC_TX7_TX_VOL_CTL WCD9335_REG(0x0a, 0x0a4) 408*4882a593Smuzhiyun #define WCD9335_CDC_TX8_TX_PATH_CTL WCD9335_REG(0x0a, 0x0b1) 409*4882a593Smuzhiyun #define WCD9335_CDC_TX8_TX_PATH_CFG0 WCD9335_REG(0x0a, 0x0b2) 410*4882a593Smuzhiyun #define WCD9335_CDC_TX8_TX_VOL_CTL WCD9335_REG(0x0a, 0x0b4) 411*4882a593Smuzhiyun #define WCD9335_CDC_TX9_SPKR_PROT_PATH_CFG0 WCD9335_REG(0x0a, 0x0c3) 412*4882a593Smuzhiyun #define WCD9335_CDC_TX10_SPKR_PROT_PATH_CFG0 WCD9335_REG(0x0a, 0x0c7) 413*4882a593Smuzhiyun #define WCD9335_CDC_TX11_SPKR_PROT_PATH_CFG0 WCD9335_REG(0x0a, 0x0cb) 414*4882a593Smuzhiyun #define WCD9335_CDC_TX12_SPKR_PROT_PATH_CFG0 WCD9335_REG(0x0a, 0x0cf) 415*4882a593Smuzhiyun 416*4882a593Smuzhiyun /* Page-11 Registers */ 417*4882a593Smuzhiyun #define WCD9335_PAGE11_PAGE_REGISTER WCD9335_REG(0x0b, 0x000) 418*4882a593Smuzhiyun #define WCD9335_CDC_COMPANDER1_CTL0 WCD9335_REG(0x0b, 0x001) 419*4882a593Smuzhiyun #define WCD9335_CDC_COMPANDER1_CTL(c) WCD9335_REG(0x0b, (0x001 + c * 0x8)) 420*4882a593Smuzhiyun #define WCD9335_CDC_COMPANDER_CLK_EN_MASK BIT(0) 421*4882a593Smuzhiyun #define WCD9335_CDC_COMPANDER_CLK_ENABLE BIT(0) 422*4882a593Smuzhiyun #define WCD9335_CDC_COMPANDER_CLK_DISABLE 0 423*4882a593Smuzhiyun #define WCD9335_CDC_COMPANDER_SOFT_RST_MASK BIT(1) 424*4882a593Smuzhiyun #define WCD9335_CDC_COMPANDER_SOFT_RST_ENABLE BIT(1) 425*4882a593Smuzhiyun #define WCD9335_CDC_COMPANDER_SOFT_RST_DISABLE 0 426*4882a593Smuzhiyun #define WCD9335_CDC_COMPANDER_HALT_MASK BIT(2) 427*4882a593Smuzhiyun #define WCD9335_CDC_COMPANDER_HALT BIT(2) 428*4882a593Smuzhiyun #define WCD9335_CDC_COMPANDER_NOHALT 0 429*4882a593Smuzhiyun #define WCD9335_CDC_COMPANDER7_CTL3 WCD9335_REG(0x0b, 0x034) 430*4882a593Smuzhiyun #define WCD9335_CDC_COMPANDER7_CTL7 WCD9335_REG(0x0b, 0x038) 431*4882a593Smuzhiyun #define WCD9335_CDC_COMPANDER8_CTL3 WCD9335_REG(0x0b, 0x03c) 432*4882a593Smuzhiyun #define WCD9335_CDC_COMPANDER8_CTL7 WCD9335_REG(0x0b, 0x040) 433*4882a593Smuzhiyun #define WCD9335_CDC_RX0_RX_PATH_CTL WCD9335_REG(0x0b, 0x041) 434*4882a593Smuzhiyun #define WCD9335_CDC_RX_PGA_MUTE_EN_MASK BIT(4) 435*4882a593Smuzhiyun #define WCD9335_CDC_RX_PGA_MUTE_ENABLE BIT(4) 436*4882a593Smuzhiyun #define WCD9335_CDC_RX_PGA_MUTE_DISABLE 0 437*4882a593Smuzhiyun #define WCD9335_CDC_RX_CLK_EN_MASK BIT(5) 438*4882a593Smuzhiyun #define WCD9335_CDC_RX_CLK_ENABLE BIT(5) 439*4882a593Smuzhiyun #define WCD9335_CDC_RX_CLK_DISABLE 0 440*4882a593Smuzhiyun #define WCD9335_CDC_RX_RESET_MASK BIT(6) 441*4882a593Smuzhiyun #define WCD9335_CDC_RX_RESET_ENABLE BIT(6) 442*4882a593Smuzhiyun #define WCD9335_CDC_RX_RESET_DISABLE 0 443*4882a593Smuzhiyun #define WCD9335_CDC_RX_PATH_CTL(rx) WCD9335_REG(0x0b, (0x041 + rx * 0x14)) 444*4882a593Smuzhiyun #define WCD9335_CDC_RX0_RX_PATH_CFG0 WCD9335_REG(0x0b, 0x042) 445*4882a593Smuzhiyun #define WCD9335_CDC_RX0_RX_PATH_CFG1 WCD9335_REG(0x0b, 0x043) 446*4882a593Smuzhiyun #define WCD9335_CDC_RX0_RX_PATH_CFG2 WCD9335_REG(0x0b, 0x044) 447*4882a593Smuzhiyun #define WCD9335_CDC_RX0_RX_VOL_CTL WCD9335_REG(0x0b, 0x045) 448*4882a593Smuzhiyun #define WCD9335_CDC_RX0_RX_PATH_MIX_CTL WCD9335_REG(0x0b, 0x046) 449*4882a593Smuzhiyun #define WCD9335_CDC_MIX_PCM_RATE_MASK GENMASK(3, 0) 450*4882a593Smuzhiyun #define WCD9335_CDC_RX_PATH_MIX_CTL(rx) WCD9335_REG(0x0b, (0x46 + rx * 0x14)) 451*4882a593Smuzhiyun #define WCD9335_CDC_RX0_RX_PATH_MIX_CFG WCD9335_REG(0x0b, 0x047) 452*4882a593Smuzhiyun #define WCD9335_CDC_RX0_RX_VOL_MIX_CTL WCD9335_REG(0x0b, 0x048) 453*4882a593Smuzhiyun #define WCD9335_CDC_RX0_RX_PATH_SEC0 WCD9335_REG(0x0b, 0x049) 454*4882a593Smuzhiyun #define WCD9335_CDC_RX0_RX_PATH_SEC7 WCD9335_REG(0x0b, 0x050) 455*4882a593Smuzhiyun #define WCD9335_CDC_RX0_RX_PATH_MIX_SEC0 WCD9335_REG(0x0b, 0x051) 456*4882a593Smuzhiyun #define WCD9335_CDC_RX1_RX_PATH_CTL WCD9335_REG(0x0b, 0x055) 457*4882a593Smuzhiyun #define WCD9335_CDC_RX1_RX_PATH_CFG0 WCD9335_REG(0x0b, 0x056) 458*4882a593Smuzhiyun #define WCD9335_CDC_RX1_RX_PATH_CFG(c) WCD9335_REG(0x0b, (0x056 + c * 0x14)) 459*4882a593Smuzhiyun #define WCD9335_CDC_RX_PATH_CFG_CMP_EN_MASK BIT(1) 460*4882a593Smuzhiyun #define WCD9335_CDC_RX_PATH_CFG_CMP_ENABLE BIT(1) 461*4882a593Smuzhiyun #define WCD9335_CDC_RX_PATH_CFG_CMP_DISABLE 0 462*4882a593Smuzhiyun #define WCD9335_CDC_RX_PATH_CFG_HD2_EN_MASK BIT(2) 463*4882a593Smuzhiyun #define WCD9335_CDC_RX_PATH_CFG_HD2_ENABLE BIT(2) 464*4882a593Smuzhiyun #define WCD9335_CDC_RX_PATH_CFG_HD2_DISABLE 0 465*4882a593Smuzhiyun #define WCD9335_CDC_RX_PATH_CFG0_DLY_ZN_EN_MASK BIT(3) 466*4882a593Smuzhiyun #define WCD9335_CDC_RX_PATH_CFG0_DLY_ZN_EN BIT(3) 467*4882a593Smuzhiyun #define WCD9335_CDC_RX_PATH_CFG0_DLY_ZN_DISABLE 0 468*4882a593Smuzhiyun #define WCD9335_CDC_RX1_RX_PATH_CFG2 WCD9335_REG(0x0b, 0x058) 469*4882a593Smuzhiyun #define WCD9335_CDC_RX1_RX_VOL_CTL WCD9335_REG(0x0b, 0x059) 470*4882a593Smuzhiyun #define WCD9335_CDC_RX1_RX_PATH_MIX_CTL WCD9335_REG(0x0b, 0x05a) 471*4882a593Smuzhiyun #define WCD9335_CDC_RX1_RX_PATH_MIX_CFG WCD9335_REG(0x0b, 0x05b) 472*4882a593Smuzhiyun #define WCD9335_CDC_RX1_RX_VOL_MIX_CTL WCD9335_REG(0x0b, 0x05c) 473*4882a593Smuzhiyun #define WCD9335_CDC_RX1_RX_PATH_SEC0 WCD9335_REG(0x0b, 0x05d) 474*4882a593Smuzhiyun #define WCD9335_CDC_RX1_RX_PATH_SEC3 WCD9335_REG(0x0b, 0x060) 475*4882a593Smuzhiyun #define WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_MASK GENMASK(1, 0) 476*4882a593Smuzhiyun #define WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_2 0x1 477*4882a593Smuzhiyun #define WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_1 0 478*4882a593Smuzhiyun #define WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_MASK GENMASK(5, 2) 479*4882a593Smuzhiyun #define WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_0P2500 0x10 480*4882a593Smuzhiyun #define WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_0P0000 0 481*4882a593Smuzhiyun #define WCD9335_CDC_RX2_RX_PATH_CTL WCD9335_REG(0x0b, 0x069) 482*4882a593Smuzhiyun #define WCD9335_CDC_RX2_RX_PATH_CFG0 WCD9335_REG(0x0b, 0x06a) 483*4882a593Smuzhiyun #define WCD9335_CDC_RX2_RX_PATH_CFG2 WCD9335_REG(0x0b, 0x06c) 484*4882a593Smuzhiyun #define WCD9335_CDC_RX2_RX_VOL_CTL WCD9335_REG(0x0b, 0x06d) 485*4882a593Smuzhiyun #define WCD9335_CDC_RX2_RX_PATH_MIX_CTL WCD9335_REG(0x0b, 0x06e) 486*4882a593Smuzhiyun #define WCD9335_CDC_RX2_RX_PATH_MIX_CFG WCD9335_REG(0x0b, 0x06f) 487*4882a593Smuzhiyun #define WCD9335_CDC_RX2_RX_VOL_MIX_CTL WCD9335_REG(0x0b, 0x070) 488*4882a593Smuzhiyun #define WCD9335_CDC_RX2_RX_PATH_SEC0 WCD9335_REG(0x0b, 0x071) 489*4882a593Smuzhiyun #define WCD9335_CDC_RX_PATH_DEM_INP_SEL_MASK GENMASK(1, 0) 490*4882a593Smuzhiyun #define WCD9335_CDC_RX2_RX_PATH_SEC3 WCD9335_REG(0x0b, 0x074) 491*4882a593Smuzhiyun #define WCD9335_CDC_RX3_RX_PATH_CTL WCD9335_REG(0x0b, 0x07d) 492*4882a593Smuzhiyun #define WCD9335_CDC_RX3_RX_PATH_CFG0 WCD9335_REG(0x0b, 0x07e) 493*4882a593Smuzhiyun #define WCD9335_CDC_RX3_RX_PATH_CFG2 WCD9335_REG(0x0b, 0x080) 494*4882a593Smuzhiyun #define WCD9335_CDC_RX3_RX_VOL_CTL WCD9335_REG(0x0b, 0x081) 495*4882a593Smuzhiyun #define WCD9335_CDC_RX3_RX_PATH_MIX_CTL WCD9335_REG(0x0b, 0x082) 496*4882a593Smuzhiyun #define WCD9335_CDC_RX3_RX_PATH_MIX_CFG WCD9335_REG(0x0b, 0x083) 497*4882a593Smuzhiyun #define WCD9335_CDC_RX3_RX_VOL_MIX_CTL WCD9335_REG(0x0b, 0x084) 498*4882a593Smuzhiyun #define WCD9335_CDC_RX4_RX_PATH_CTL WCD9335_REG(0x0b, 0x091) 499*4882a593Smuzhiyun #define WCD9335_CDC_RX4_RX_PATH_CFG0 WCD9335_REG(0x0b, 0x092) 500*4882a593Smuzhiyun #define WCD9335_CDC_RX4_RX_PATH_CFG2 WCD9335_REG(0x0b, 0x094) 501*4882a593Smuzhiyun #define WCD9335_CDC_RX4_RX_VOL_CTL WCD9335_REG(0x0b, 0x095) 502*4882a593Smuzhiyun #define WCD9335_CDC_RX4_RX_PATH_MIX_CTL WCD9335_REG(0x0b, 0x096) 503*4882a593Smuzhiyun #define WCD9335_CDC_RX4_RX_PATH_MIX_CFG WCD9335_REG(0x0b, 0x097) 504*4882a593Smuzhiyun #define WCD9335_CDC_RX4_RX_VOL_MIX_CTL WCD9335_REG(0x0b, 0x098) 505*4882a593Smuzhiyun #define WCD9335_CDC_RX5_RX_PATH_CTL WCD9335_REG(0x0b, 0x0a5) 506*4882a593Smuzhiyun #define WCD9335_CDC_RX5_RX_PATH_CFG0 WCD9335_REG(0x0b, 0x0a6) 507*4882a593Smuzhiyun #define WCD9335_CDC_RX5_RX_PATH_CFG2 WCD9335_REG(0x0b, 0x0a8) 508*4882a593Smuzhiyun #define WCD9335_CDC_RX5_RX_VOL_CTL WCD9335_REG(0x0b, 0x0a9) 509*4882a593Smuzhiyun #define WCD9335_CDC_RX5_RX_PATH_MIX_CTL WCD9335_REG(0x0b, 0x0aa) 510*4882a593Smuzhiyun #define WCD9335_CDC_RX5_RX_PATH_MIX_CFG WCD9335_REG(0x0b, 0x0ab) 511*4882a593Smuzhiyun #define WCD9335_CDC_RX5_RX_VOL_MIX_CTL WCD9335_REG(0x0b, 0x0ac) 512*4882a593Smuzhiyun #define WCD9335_CDC_RX6_RX_PATH_CTL WCD9335_REG(0x0b, 0x0b9) 513*4882a593Smuzhiyun #define WCD9335_CDC_RX6_RX_PATH_CFG0 WCD9335_REG(0x0b, 0x0ba) 514*4882a593Smuzhiyun #define WCD9335_CDC_RX6_RX_PATH_CFG2 WCD9335_REG(0x0b, 0x0bc) 515*4882a593Smuzhiyun #define WCD9335_CDC_RX6_RX_VOL_CTL WCD9335_REG(0x0b, 0x0bd) 516*4882a593Smuzhiyun #define WCD9335_CDC_RX6_RX_PATH_MIX_CTL WCD9335_REG(0x0b, 0x0be) 517*4882a593Smuzhiyun #define WCD9335_CDC_RX6_RX_PATH_MIX_CFG WCD9335_REG(0x0b, 0x0bf) 518*4882a593Smuzhiyun #define WCD9335_CDC_RX6_RX_VOL_MIX_CTL WCD9335_REG(0x0b, 0x0c0) 519*4882a593Smuzhiyun #define WCD9335_CDC_RX7_RX_PATH_CTL WCD9335_REG(0x0b, 0x0cd) 520*4882a593Smuzhiyun #define WCD9335_CDC_RX7_RX_PATH_CFG0 WCD9335_REG(0x0b, 0x0ce) 521*4882a593Smuzhiyun #define WCD9335_CDC_RX7_RX_PATH_CFG1 WCD9335_REG(0x0b, 0x0cf) 522*4882a593Smuzhiyun #define WCD9335_CDC_RX7_RX_PATH_CFG2 WCD9335_REG(0x0b, 0x0d0) 523*4882a593Smuzhiyun #define WCD9335_CDC_RX7_RX_VOL_CTL WCD9335_REG(0x0b, 0x0d1) 524*4882a593Smuzhiyun #define WCD9335_CDC_RX7_RX_PATH_MIX_CTL WCD9335_REG(0x0b, 0x0d2) 525*4882a593Smuzhiyun #define WCD9335_CDC_RX7_RX_PATH_MIX_CFG WCD9335_REG(0x0b, 0x0d3) 526*4882a593Smuzhiyun #define WCD9335_CDC_RX7_RX_VOL_MIX_CTL WCD9335_REG(0x0b, 0x0d4) 527*4882a593Smuzhiyun #define WCD9335_CDC_RX8_RX_PATH_CTL WCD9335_REG(0x0b, 0x0e1) 528*4882a593Smuzhiyun #define WCD9335_CDC_RX8_RX_PATH_CFG0 WCD9335_REG(0x0b, 0x0e2) 529*4882a593Smuzhiyun #define WCD9335_CDC_RX8_RX_PATH_CFG1 WCD9335_REG(0x0b, 0x0e3) 530*4882a593Smuzhiyun #define WCD9335_CDC_RX8_RX_PATH_CFG2 WCD9335_REG(0x0b, 0x0e4) 531*4882a593Smuzhiyun #define WCD9335_CDC_RX8_RX_VOL_CTL WCD9335_REG(0x0b, 0x0e5) 532*4882a593Smuzhiyun #define WCD9335_CDC_RX8_RX_PATH_MIX_CTL WCD9335_REG(0x0b, 0x0e6) 533*4882a593Smuzhiyun #define WCD9335_CDC_RX8_RX_PATH_MIX_CFG WCD9335_REG(0x0b, 0x0e7) 534*4882a593Smuzhiyun #define WCD9335_CDC_RX8_RX_VOL_MIX_CTL WCD9335_REG(0x0b, 0x0e8) 535*4882a593Smuzhiyun 536*4882a593Smuzhiyun /* Page-12 Registers */ 537*4882a593Smuzhiyun #define WCD9335_PAGE12_PAGE_REGISTER WCD9335_REG(0x0c, 0x000) 538*4882a593Smuzhiyun #define WCD9335_CDC_CLSH_K2_MSB WCD9335_REG(0x0c, 0x00a) 539*4882a593Smuzhiyun #define WCD9335_CDC_CLSH_K2_LSB WCD9335_REG(0x0c, 0x00b) 540*4882a593Smuzhiyun #define WCD9335_CDC_BOOST0_BOOST_CTL WCD9335_REG(0x0c, 0x01a) 541*4882a593Smuzhiyun #define WCD9335_CDC_BOOST0_BOOST_CFG1 WCD9335_REG(0x0c, 0x01b) 542*4882a593Smuzhiyun #define WCD9335_CDC_BOOST0_BOOST_CFG2 WCD9335_REG(0x0c, 0x01c) 543*4882a593Smuzhiyun #define WCD9335_CDC_BOOST1_BOOST_CTL WCD9335_REG(0x0c, 0x022) 544*4882a593Smuzhiyun #define WCD9335_CDC_BOOST1_BOOST_CFG1 WCD9335_REG(0x0c, 0x023) 545*4882a593Smuzhiyun #define WCD9335_CDC_BOOST1_BOOST_CFG2 WCD9335_REG(0x0c, 0x024) 546*4882a593Smuzhiyun 547*4882a593Smuzhiyun /* Page-13 Registers */ 548*4882a593Smuzhiyun #define WCD9335_PAGE13_PAGE_REGISTER WCD9335_REG(0x0d, 0x000) 549*4882a593Smuzhiyun #define WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG0 WCD9335_REG(0x0d, 0x001) 550*4882a593Smuzhiyun #define WCD9335_CDC_RX_INP_MUX_RX_INT_CFG0(i) WCD9335_REG(0xd, (0x1 + i * 0x2)) 551*4882a593Smuzhiyun #define WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG1 WCD9335_REG(0xd, 0x002) 552*4882a593Smuzhiyun #define WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK GENMASK(3, 0) 553*4882a593Smuzhiyun #define WCD9335_CDC_RX_INP_MUX_RX_INT_CFG1(i) WCD9335_REG(0xd, (0x2 + i * 0x2)) 554*4882a593Smuzhiyun 555*4882a593Smuzhiyun #define WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG0 WCD9335_REG(0x0d, 0x003) 556*4882a593Smuzhiyun #define WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG1 WCD9335_REG(0x0d, 0x004) 557*4882a593Smuzhiyun #define WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG0 WCD9335_REG(0x0d, 0x005) 558*4882a593Smuzhiyun #define WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG1 WCD9335_REG(0x0d, 0x006) 559*4882a593Smuzhiyun #define WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG0 WCD9335_REG(0x0d, 0x007) 560*4882a593Smuzhiyun #define WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG1 WCD9335_REG(0x0d, 0x008) 561*4882a593Smuzhiyun #define WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG0 WCD9335_REG(0x0d, 0x009) 562*4882a593Smuzhiyun #define WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG1 WCD9335_REG(0x0d, 0x00a) 563*4882a593Smuzhiyun #define WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG0 WCD9335_REG(0x0d, 0x00b) 564*4882a593Smuzhiyun #define WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG1 WCD9335_REG(0x0d, 0x00c) 565*4882a593Smuzhiyun #define WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG0 WCD9335_REG(0x0d, 0x00d) 566*4882a593Smuzhiyun #define WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG1 WCD9335_REG(0x0d, 0x00e) 567*4882a593Smuzhiyun #define WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG0 WCD9335_REG(0x0d, 0x00f) 568*4882a593Smuzhiyun #define WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG1 WCD9335_REG(0x0d, 0x010) 569*4882a593Smuzhiyun #define WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG0 WCD9335_REG(0x0d, 0x011) 570*4882a593Smuzhiyun #define WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG1 WCD9335_REG(0x0d, 0x012) 571*4882a593Smuzhiyun #define WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0 WCD9335_REG(0x0d, 0x01d) 572*4882a593Smuzhiyun #define WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1 WCD9335_REG(0x0d, 0x01e) 573*4882a593Smuzhiyun #define WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG0 WCD9335_REG(0x0d, 0x01f) 574*4882a593Smuzhiyun #define WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG1 WCD9335_REG(0x0d, 0x020) 575*4882a593Smuzhiyun #define WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG0 WCD9335_REG(0x0d, 0x021) 576*4882a593Smuzhiyun #define WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG1 WCD9335_REG(0x0d, 0x022) 577*4882a593Smuzhiyun #define WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG0 WCD9335_REG(0x0d, 0x023) 578*4882a593Smuzhiyun #define WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG1 WCD9335_REG(0x0d, 0x024) 579*4882a593Smuzhiyun #define WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0 WCD9335_REG(0x0d, 0x025) 580*4882a593Smuzhiyun #define WCD9335_CDC_TX_INP_MUX_SEL_AMIC 0x1 581*4882a593Smuzhiyun #define WCD9335_CDC_TX_INP_MUX_SEL_DMIC 0 582*4882a593Smuzhiyun #define WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0 WCD9335_REG(0x0d, 0x026) 583*4882a593Smuzhiyun #define WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0 WCD9335_REG(0x0d, 0x027) 584*4882a593Smuzhiyun #define WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0 WCD9335_REG(0x0d, 0x028) 585*4882a593Smuzhiyun #define WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0 WCD9335_REG(0x0d, 0x029) 586*4882a593Smuzhiyun #define WCD9335_CDC_TX_INP_MUX_ADC_MUX10_CFG0 WCD9335_REG(0x0d, 0x02b) 587*4882a593Smuzhiyun #define WCD9335_CDC_TX_INP_MUX_ADC_MUX11_CFG0 WCD9335_REG(0x0d, 0x02c) 588*4882a593Smuzhiyun #define WCD9335_CDC_TX_INP_MUX_ADC_MUX12_CFG0 WCD9335_REG(0x0d, 0x02d) 589*4882a593Smuzhiyun #define WCD9335_CDC_TX_INP_MUX_ADC_MUX13_CFG0 WCD9335_REG(0x0d, 0x02e) 590*4882a593Smuzhiyun #define WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0 WCD9335_REG(0x0d, 0x03a) 591*4882a593Smuzhiyun #define WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1 WCD9335_REG(0x0d, 0x03b) 592*4882a593Smuzhiyun #define WCD9335_CDC_IF_ROUTER_TX_MUX_CFG2 WCD9335_REG(0x0d, 0x03c) 593*4882a593Smuzhiyun #define WCD9335_CDC_IF_ROUTER_TX_MUX_CFG3 WCD9335_REG(0x0d, 0x03d) 594*4882a593Smuzhiyun #define WCD9335_CDC_CLK_RST_CTRL_MCLK_CONTROL WCD9335_REG(0x0d, 0x041) 595*4882a593Smuzhiyun #define WCD9335_CDC_CLK_RST_CTRL_MCLK_EN_MASK BIT(0) 596*4882a593Smuzhiyun #define WCD9335_CDC_CLK_RST_CTRL_MCLK_ENABLE BIT(0) 597*4882a593Smuzhiyun #define WCD9335_CDC_CLK_RST_CTRL_MCLK_DISABLE 0 598*4882a593Smuzhiyun #define WCD9335_CDC_CLK_RST_CTRL_FS_CNT_CONTROL WCD9335_REG(0x0d, 0x042) 599*4882a593Smuzhiyun #define WCD9335_CDC_CLK_RST_CTRL_FS_CNT_EN_MASK BIT(0) 600*4882a593Smuzhiyun #define WCD9335_CDC_CLK_RST_CTRL_FS_CNT_ENABLE BIT(0) 601*4882a593Smuzhiyun #define WCD9335_CDC_CLK_RST_CTRL_FS_CNT_DISABLE 0 602*4882a593Smuzhiyun #define WCD9335_CDC_TOP_TOP_CFG1 WCD9335_REG(0x0d, 0x082) 603*4882a593Smuzhiyun #define WCD9335_MAX_REGISTER 0xffff 604*4882a593Smuzhiyun #define WCD9335_SEL_REGISTER 0x800 605*4882a593Smuzhiyun 606*4882a593Smuzhiyun /* SLIMBUS Slave Registers */ 607*4882a593Smuzhiyun #define WCD9335_SLIM_PGD_PORT_INT_EN0 WCD9335_REG(0, 0x30) 608*4882a593Smuzhiyun #define WCD9335_SLIM_PGD_PORT_INT_STATUS_RX_0 WCD9335_REG(0, 0x34) 609*4882a593Smuzhiyun #define WCD9335_SLIM_PGD_PORT_INT_STATUS_RX_1 WCD9335_REG(0, 0x35) 610*4882a593Smuzhiyun #define WCD9335_SLIM_PGD_PORT_INT_STATUS_TX_0 WCD9335_REG(0, 0x36) 611*4882a593Smuzhiyun #define WCD9335_SLIM_PGD_PORT_INT_STATUS_TX_1 WCD9335_REG(0, 0x37) 612*4882a593Smuzhiyun #define WCD9335_SLIM_PGD_PORT_INT_CLR_RX_0 WCD9335_REG(0, 0x38) 613*4882a593Smuzhiyun #define WCD9335_SLIM_PGD_PORT_INT_CLR_RX_1 WCD9335_REG(0, 0x39) 614*4882a593Smuzhiyun #define WCD9335_SLIM_PGD_PORT_INT_CLR_TX_0 WCD9335_REG(0, 0x3A) 615*4882a593Smuzhiyun #define WCD9335_SLIM_PGD_PORT_INT_CLR_TX_1 WCD9335_REG(0, 0x3B) 616*4882a593Smuzhiyun #define WCD9335_SLIM_PGD_PORT_INT_RX_SOURCE0 WCD9335_REG(0, 0x60) 617*4882a593Smuzhiyun #define WCD9335_SLIM_PGD_PORT_INT_TX_SOURCE0 WCD9335_REG(0, 0x70) 618*4882a593Smuzhiyun #define WCD9335_SLIM_PGD_RX_PORT_CFG(p) WCD9335_REG(0, (0x30 + p)) 619*4882a593Smuzhiyun #define WCD9335_SLIM_PGD_PORT_CFG(p) WCD9335_REG(0, (0x40 + p)) 620*4882a593Smuzhiyun #define WCD9335_SLIM_PGD_TX_PORT_CFG(p) WCD9335_REG(0, (0x50 + p)) 621*4882a593Smuzhiyun #define WCD9335_SLIM_PGD_PORT_INT_SRC(p) WCD9335_REG(0, (0x60 + p)) 622*4882a593Smuzhiyun #define WCD9335_SLIM_PGD_PORT_INT_STATUS(p) WCD9335_REG(0, (0x80 + p)) 623*4882a593Smuzhiyun #define WCD9335_SLIM_PGD_TX_PORT_MULTI_CHNL_0(p) WCD9335_REG(0, (0x100 + 4 * p)) 624*4882a593Smuzhiyun /* ports range from 10-16 */ 625*4882a593Smuzhiyun #define WCD9335_SLIM_PGD_TX_PORT_MULTI_CHNL_1(p) WCD9335_REG(0, (0x101 + 4 * p)) 626*4882a593Smuzhiyun #define WCD9335_SLIM_PGD_RX_PORT_MULTI_CHNL_0(p) WCD9335_REG(0, (0x140 + 4 * p)) 627*4882a593Smuzhiyun 628*4882a593Smuzhiyun #define WCD9335_IRQ_SLIMBUS 0 629*4882a593Smuzhiyun #define WCD9335_IRQ_MBHC_SW_DET 8 630*4882a593Smuzhiyun #define WCD9335_IRQ_MBHC_ELECT_INS_REM_DET 9 631*4882a593Smuzhiyun #define WCD9335_IRQ_MBHC_BUTTON_PRESS_DET 10 632*4882a593Smuzhiyun #define WCD9335_IRQ_MBHC_BUTTON_RELEASE_DET 11 633*4882a593Smuzhiyun #define WCD9335_IRQ_MBHC_ELECT_INS_REM_LEG_DET 12 634*4882a593Smuzhiyun 635*4882a593Smuzhiyun #define SLIM_MANF_ID_QCOM 0x217 636*4882a593Smuzhiyun #define SLIM_PROD_CODE_WCD9335 0x1a0 637*4882a593Smuzhiyun 638*4882a593Smuzhiyun #define WCD9335_VERSION_2_0 2 639*4882a593Smuzhiyun #define WCD9335_MAX_SUPPLY 5 640*4882a593Smuzhiyun 641*4882a593Smuzhiyun #endif /* __WCD9335_H__ */ 642