1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * File: sound/soc/codecs/ssm2602.h 4*4882a593Smuzhiyun * Author: Cliff Cai <Cliff.Cai@analog.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Created: Tue June 06 2008 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Modified: 9*4882a593Smuzhiyun * Copyright 2008 Analog Devices Inc. 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * Bugs: Enter bugs at http://blackfin.uclinux.org/ 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #ifndef _SSM2602_H 15*4882a593Smuzhiyun #define _SSM2602_H 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #include <linux/regmap.h> 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun struct device; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun enum ssm2602_type { 22*4882a593Smuzhiyun SSM2602, 23*4882a593Smuzhiyun SSM2604, 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun extern const struct regmap_config ssm2602_regmap_config; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun int ssm2602_probe(struct device *dev, enum ssm2602_type type, 29*4882a593Smuzhiyun struct regmap *regmap); 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* SSM2602 Codec Register definitions */ 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define SSM2602_LINVOL 0x00 34*4882a593Smuzhiyun #define SSM2602_RINVOL 0x01 35*4882a593Smuzhiyun #define SSM2602_LOUT1V 0x02 36*4882a593Smuzhiyun #define SSM2602_ROUT1V 0x03 37*4882a593Smuzhiyun #define SSM2602_APANA 0x04 38*4882a593Smuzhiyun #define SSM2602_APDIGI 0x05 39*4882a593Smuzhiyun #define SSM2602_PWR 0x06 40*4882a593Smuzhiyun #define SSM2602_IFACE 0x07 41*4882a593Smuzhiyun #define SSM2602_SRATE 0x08 42*4882a593Smuzhiyun #define SSM2602_ACTIVE 0x09 43*4882a593Smuzhiyun #define SSM2602_RESET 0x0f 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /*SSM2602 Codec Register Field definitions 46*4882a593Smuzhiyun *(Mask value to extract the corresponding Register field) 47*4882a593Smuzhiyun */ 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /*Left ADC Volume Control (SSM2602_REG_LEFT_ADC_VOL)*/ 50*4882a593Smuzhiyun #define LINVOL_LIN_VOL 0x01F /* Left Channel PGA Volume control */ 51*4882a593Smuzhiyun #define LINVOL_LIN_ENABLE_MUTE 0x080 /* Left Channel Input Mute */ 52*4882a593Smuzhiyun #define LINVOL_LRIN_BOTH 0x100 /* Left Channel Line Input Volume update */ 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /*Right ADC Volume Control (SSM2602_REG_RIGHT_ADC_VOL)*/ 55*4882a593Smuzhiyun #define RINVOL_RIN_VOL 0x01F /* Right Channel PGA Volume control */ 56*4882a593Smuzhiyun #define RINVOL_RIN_ENABLE_MUTE 0x080 /* Right Channel Input Mute */ 57*4882a593Smuzhiyun #define RINVOL_RLIN_BOTH 0x100 /* Right Channel Line Input Volume update */ 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /*Left DAC Volume Control (SSM2602_REG_LEFT_DAC_VOL)*/ 60*4882a593Smuzhiyun #define LOUT1V_LHP_VOL 0x07F /* Left Channel Headphone volume control */ 61*4882a593Smuzhiyun #define LOUT1V_ENABLE_LZC 0x080 /* Left Channel Zero cross detect enable */ 62*4882a593Smuzhiyun #define LOUT1V_LRHP_BOTH 0x100 /* Left Channel Headphone volume update */ 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /*Right DAC Volume Control (SSM2602_REG_RIGHT_DAC_VOL)*/ 65*4882a593Smuzhiyun #define ROUT1V_RHP_VOL 0x07F /* Right Channel Headphone volume control */ 66*4882a593Smuzhiyun #define ROUT1V_ENABLE_RZC 0x080 /* Right Channel Zero cross detect enable */ 67*4882a593Smuzhiyun #define ROUT1V_RLHP_BOTH 0x100 /* Right Channel Headphone volume update */ 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /*Analogue Audio Path Control (SSM2602_REG_ANALOGUE_PATH)*/ 70*4882a593Smuzhiyun #define APANA_ENABLE_MIC_BOOST 0x001 /* Primary Microphone Amplifier gain booster control */ 71*4882a593Smuzhiyun #define APANA_ENABLE_MIC_MUTE 0x002 /* Microphone Mute Control */ 72*4882a593Smuzhiyun #define APANA_ADC_IN_SELECT 0x004 /* Microphone/Line IN select to ADC (1=MIC, 0=Line In) */ 73*4882a593Smuzhiyun #define APANA_ENABLE_BYPASS 0x008 /* Line input bypass to line output */ 74*4882a593Smuzhiyun #define APANA_SELECT_DAC 0x010 /* Select DAC (1=Select DAC, 0=Don't Select DAC) */ 75*4882a593Smuzhiyun #define APANA_ENABLE_SIDETONE 0x020 /* Enable/Disable Side Tone */ 76*4882a593Smuzhiyun #define APANA_SIDETONE_ATTN 0x0C0 /* Side Tone Attenuation */ 77*4882a593Smuzhiyun #define APANA_ENABLE_MIC_BOOST2 0x100 /* Secondary Microphone Amplifier gain booster control */ 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun /*Digital Audio Path Control (SSM2602_REG_DIGITAL_PATH)*/ 80*4882a593Smuzhiyun #define APDIGI_ENABLE_ADC_HPF 0x001 /* Enable/Disable ADC Highpass Filter */ 81*4882a593Smuzhiyun #define APDIGI_DE_EMPHASIS 0x006 /* De-Emphasis Control */ 82*4882a593Smuzhiyun #define APDIGI_ENABLE_DAC_MUTE 0x008 /* DAC Mute Control */ 83*4882a593Smuzhiyun #define APDIGI_STORE_OFFSET 0x010 /* Store/Clear DC offset when HPF is disabled */ 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /*Power Down Control (SSM2602_REG_POWER) 86*4882a593Smuzhiyun *(1=Enable PowerDown, 0=Disable PowerDown) 87*4882a593Smuzhiyun */ 88*4882a593Smuzhiyun #define PWR_LINE_IN_PDN 0x001 /* Line Input Power Down */ 89*4882a593Smuzhiyun #define PWR_MIC_PDN 0x002 /* Microphone Input & Bias Power Down */ 90*4882a593Smuzhiyun #define PWR_ADC_PDN 0x004 /* ADC Power Down */ 91*4882a593Smuzhiyun #define PWR_DAC_PDN 0x008 /* DAC Power Down */ 92*4882a593Smuzhiyun #define PWR_OUT_PDN 0x010 /* Outputs Power Down */ 93*4882a593Smuzhiyun #define PWR_OSC_PDN 0x020 /* Oscillator Power Down */ 94*4882a593Smuzhiyun #define PWR_CLK_OUT_PDN 0x040 /* CLKOUT Power Down */ 95*4882a593Smuzhiyun #define PWR_POWER_OFF 0x080 /* POWEROFF Mode */ 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun /*Digital Audio Interface Format (SSM2602_REG_DIGITAL_IFACE)*/ 98*4882a593Smuzhiyun #define IFACE_IFACE_FORMAT 0x003 /* Digital Audio input format control */ 99*4882a593Smuzhiyun #define IFACE_AUDIO_DATA_LEN 0x00C /* Audio Data word length control */ 100*4882a593Smuzhiyun #define IFACE_DAC_LR_POLARITY 0x010 /* Polarity Control for clocks in RJ,LJ and I2S modes */ 101*4882a593Smuzhiyun #define IFACE_DAC_LR_SWAP 0x020 /* Swap DAC data control */ 102*4882a593Smuzhiyun #define IFACE_ENABLE_MASTER 0x040 /* Enable/Disable Master Mode */ 103*4882a593Smuzhiyun #define IFACE_BCLK_INVERT 0x080 /* Bit Clock Inversion control */ 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun /*Sampling Control (SSM2602_REG_SAMPLING_CTRL)*/ 106*4882a593Smuzhiyun #define SRATE_ENABLE_USB_MODE 0x001 /* Enable/Disable USB Mode */ 107*4882a593Smuzhiyun #define SRATE_BOS_RATE 0x002 /* Base Over-Sampling rate */ 108*4882a593Smuzhiyun #define SRATE_SAMPLE_RATE 0x03C /* Clock setting condition (Sampling rate control) */ 109*4882a593Smuzhiyun #define SRATE_CORECLK_DIV2 0x040 /* Core Clock divider select */ 110*4882a593Smuzhiyun #define SRATE_CLKOUT_DIV2 0x080 /* Clock Out divider select */ 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun /*Active Control (SSM2602_REG_ACTIVE_CTRL)*/ 113*4882a593Smuzhiyun #define ACTIVE_ACTIVATE_CODEC 0x001 /* Activate Codec Digital Audio Interface */ 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun /*********************************************************************/ 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun #define SSM2602_CACHEREGNUM 10 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun enum ssm2602_clk { 120*4882a593Smuzhiyun SSM2602_SYSCLK, 121*4882a593Smuzhiyun SSM2602_CLK_CLKOUT, 122*4882a593Smuzhiyun SSM2602_CLK_XTO 123*4882a593Smuzhiyun }; 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun #endif 126