1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * UniPhier DDR PHY registers 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2014 Panasonic Corporation 5*4882a593Smuzhiyun * Copyright (C) 2015-2016 Socionext Inc. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef ARCH_DDRPHY_REGS_H 11*4882a593Smuzhiyun #define ARCH_DDRPHY_REGS_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define PHY_REG_SHIFT 2 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define PHY_RIDR (0x000 << PHY_REG_SHIFT) 16*4882a593Smuzhiyun #define PHY_PIR (0x001 << PHY_REG_SHIFT) 17*4882a593Smuzhiyun #define PHY_PIR_INIT BIT(0) /* Initialization Trigger */ 18*4882a593Smuzhiyun #define PHY_PIR_ZCAL BIT(1) /* Impedance Calibration */ 19*4882a593Smuzhiyun #define PHY_PIR_PLLINIT BIT(4) /* PLL Initialization */ 20*4882a593Smuzhiyun #define PHY_PIR_DCAL BIT(5) /* DDL Calibration */ 21*4882a593Smuzhiyun #define PHY_PIR_PHYRST BIT(6) /* PHY Reset */ 22*4882a593Smuzhiyun #define PHY_PIR_DRAMRST BIT(7) /* DRAM Reset */ 23*4882a593Smuzhiyun #define PHY_PIR_DRAMINIT BIT(8) /* DRAM Initialization */ 24*4882a593Smuzhiyun #define PHY_PIR_WL BIT(9) /* Write Leveling */ 25*4882a593Smuzhiyun #define PHY_PIR_QSGATE BIT(10) /* Read DQS Gate Training */ 26*4882a593Smuzhiyun #define PHY_PIR_WLADJ BIT(11) /* Write Leveling Adjust */ 27*4882a593Smuzhiyun #define PHY_PIR_RDDSKW BIT(12) /* Read Data Bit Deskew */ 28*4882a593Smuzhiyun #define PHY_PIR_WRDSKW BIT(13) /* Write Data Bit Deskew */ 29*4882a593Smuzhiyun #define PHY_PIR_RDEYE BIT(14) /* Read Data Eye Training */ 30*4882a593Smuzhiyun #define PHY_PIR_WREYE BIT(15) /* Write Data Eye Training */ 31*4882a593Smuzhiyun #define PHY_PIR_LOCKBYP BIT(28) /* PLL Lock Bypass */ 32*4882a593Smuzhiyun #define PHY_PIR_DCALBYP BIT(29) /* DDL Calibration Bypass */ 33*4882a593Smuzhiyun #define PHY_PIR_ZCALBYP BIT(30) /* Impedance Calib Bypass */ 34*4882a593Smuzhiyun #define PHY_PIR_INITBYP BIT(31) /* Initialization Bypass */ 35*4882a593Smuzhiyun #define PHY_PGCR0 (0x002 << PHY_REG_SHIFT) 36*4882a593Smuzhiyun #define PHY_PGCR1 (0x003 << PHY_REG_SHIFT) 37*4882a593Smuzhiyun #define PHY_PGCR1_INHVT BIT(26) /* VT Calculation Inhibit */ 38*4882a593Smuzhiyun #define PHY_PGSR0 (0x004 << PHY_REG_SHIFT) 39*4882a593Smuzhiyun #define PHY_PGSR0_IDONE BIT(0) /* Initialization Done */ 40*4882a593Smuzhiyun #define PHY_PGSR0_PLDONE BIT(1) /* PLL Lock Done */ 41*4882a593Smuzhiyun #define PHY_PGSR0_DCDONE BIT(2) /* DDL Calibration Done */ 42*4882a593Smuzhiyun #define PHY_PGSR0_ZCDONE BIT(3) /* Impedance Calibration Done */ 43*4882a593Smuzhiyun #define PHY_PGSR0_DIDONE BIT(4) /* DRAM Initialization Done */ 44*4882a593Smuzhiyun #define PHY_PGSR0_WLDONE BIT(5) /* Write Leveling Done */ 45*4882a593Smuzhiyun #define PHY_PGSR0_QSGDONE BIT(6) /* DQS Gate Training Done */ 46*4882a593Smuzhiyun #define PHY_PGSR0_WLADONE BIT(7) /* Write Leveling Adjust Done */ 47*4882a593Smuzhiyun #define PHY_PGSR0_RDDONE BIT(8) /* Read Bit Deskew Done */ 48*4882a593Smuzhiyun #define PHY_PGSR0_WDDONE BIT(9) /* Write Bit Deskew Done */ 49*4882a593Smuzhiyun #define PHY_PGSR0_REDONE BIT(10) /* Read Eye Training Done */ 50*4882a593Smuzhiyun #define PHY_PGSR0_WEDONE BIT(11) /* Write Eye Training Done */ 51*4882a593Smuzhiyun #define PHY_PGSR0_DIERR BIT(20) /* DRAM Initialization Error */ 52*4882a593Smuzhiyun #define PHY_PGSR0_WLERR BIT(21) /* Write Leveling Error */ 53*4882a593Smuzhiyun #define PHY_PGSR0_QSGERR BIT(22) /* DQS Gate Training Error */ 54*4882a593Smuzhiyun #define PHY_PGSR0_WLAERR BIT(23) /* Write Leveling Adj Error */ 55*4882a593Smuzhiyun #define PHY_PGSR0_RDERR BIT(24) /* Read Bit Deskew Error */ 56*4882a593Smuzhiyun #define PHY_PGSR0_WDERR BIT(25) /* Write Bit Deskew Error */ 57*4882a593Smuzhiyun #define PHY_PGSR0_REERR BIT(26) /* Read Eye Training Error */ 58*4882a593Smuzhiyun #define PHY_PGSR0_WEERR BIT(27) /* Write Eye Training Error */ 59*4882a593Smuzhiyun #define PHY_PGSR0_DTERR_SHIFT 28 /* Data Training Error Status*/ 60*4882a593Smuzhiyun #define PHY_PGSR0_DTERR (7 << (PHY_PGSR0_DTERR_SHIFT)) 61*4882a593Smuzhiyun #define PHY_PGSR1 (0x005 << PHY_REG_SHIFT) 62*4882a593Smuzhiyun #define PHY_PGSR1_VTSTOP BIT(30) /* VT Stop (v3-) */ 63*4882a593Smuzhiyun #define PHY_PLLCR (0x006 << PHY_REG_SHIFT) 64*4882a593Smuzhiyun #define PHY_PTR0 (0x007 << PHY_REG_SHIFT) 65*4882a593Smuzhiyun #define PHY_PTR1 (0x008 << PHY_REG_SHIFT) 66*4882a593Smuzhiyun #define PHY_PTR2 (0x009 << PHY_REG_SHIFT) 67*4882a593Smuzhiyun #define PHY_PTR3 (0x00A << PHY_REG_SHIFT) 68*4882a593Smuzhiyun #define PHY_PTR4 (0x00B << PHY_REG_SHIFT) 69*4882a593Smuzhiyun #define PHY_ACMDLR (0x00C << PHY_REG_SHIFT) 70*4882a593Smuzhiyun #define PHY_ACBDLR (0x00D << PHY_REG_SHIFT) 71*4882a593Smuzhiyun #define PHY_ACIOCR (0x00E << PHY_REG_SHIFT) 72*4882a593Smuzhiyun #define PHY_DXCCR (0x00F << PHY_REG_SHIFT) 73*4882a593Smuzhiyun #define PHY_DXCCR_DQSRES_OPEN (0 << 5) 74*4882a593Smuzhiyun #define PHY_DXCCR_DQSRES_688_OHM (1 << 5) 75*4882a593Smuzhiyun #define PHY_DXCCR_DQSRES_611_OHM (2 << 5) 76*4882a593Smuzhiyun #define PHY_DXCCR_DQSRES_550_OHM (3 << 5) 77*4882a593Smuzhiyun #define PHY_DXCCR_DQSRES_500_OHM (4 << 5) 78*4882a593Smuzhiyun #define PHY_DXCCR_DQSRES_458_OHM (5 << 5) 79*4882a593Smuzhiyun #define PHY_DXCCR_DQSRES_393_OHM (6 << 5) 80*4882a593Smuzhiyun #define PHY_DXCCR_DQSRES_344_OHM (7 << 5) 81*4882a593Smuzhiyun #define PHY_DXCCR_DQSNRES_OPEN (0 << 9) 82*4882a593Smuzhiyun #define PHY_DXCCR_DQSNRES_688_OHM (1 << 9) 83*4882a593Smuzhiyun #define PHY_DXCCR_DQSNRES_611_OHM (2 << 9) 84*4882a593Smuzhiyun #define PHY_DXCCR_DQSNRES_550_OHM (3 << 9) 85*4882a593Smuzhiyun #define PHY_DXCCR_DQSNRES_500_OHM (4 << 9) 86*4882a593Smuzhiyun #define PHY_DXCCR_DQSNRES_458_OHM (5 << 9) 87*4882a593Smuzhiyun #define PHY_DXCCR_DQSNRES_393_OHM (6 << 9) 88*4882a593Smuzhiyun #define PHY_DXCCR_DQSNRES_344_OHM (7 << 9) 89*4882a593Smuzhiyun #define PHY_DSGCR (0x010 << PHY_REG_SHIFT) 90*4882a593Smuzhiyun #define PHY_DCR (0x011 << PHY_REG_SHIFT) 91*4882a593Smuzhiyun #define PHY_DTPR0 (0x012 << PHY_REG_SHIFT) 92*4882a593Smuzhiyun #define PHY_DTPR1 (0x013 << PHY_REG_SHIFT) 93*4882a593Smuzhiyun #define PHY_DTPR2 (0x014 << PHY_REG_SHIFT) 94*4882a593Smuzhiyun #define PHY_MR0 (0x015 << PHY_REG_SHIFT) 95*4882a593Smuzhiyun #define PHY_MR1 (0x016 << PHY_REG_SHIFT) 96*4882a593Smuzhiyun #define PHY_MR2 (0x017 << PHY_REG_SHIFT) 97*4882a593Smuzhiyun #define PHY_MR3 (0x018 << PHY_REG_SHIFT) 98*4882a593Smuzhiyun #define PHY_ODTCR (0x019 << PHY_REG_SHIFT) 99*4882a593Smuzhiyun #define PHY_DTCR (0x01A << PHY_REG_SHIFT) 100*4882a593Smuzhiyun #define PHY_DTCR_DTRANK_SHIFT 4 /* Data Training Rank */ 101*4882a593Smuzhiyun #define PHY_DTCR_DTRANK_MASK (0x3 << (PHY_DTCR_DTRANK_SHIFT)) 102*4882a593Smuzhiyun #define PHY_DTCR_DTMPR BIT(6) /* Data Training using MPR */ 103*4882a593Smuzhiyun #define PHY_DTCR_RANKEN_SHIFT 24 /* Rank Enable */ 104*4882a593Smuzhiyun #define PHY_DTCR_RANKEN_MASK (0xf << (PHY_DTCR_RANKEN_SHIFT)) 105*4882a593Smuzhiyun #define PHY_DTAR0 (0x01B << PHY_REG_SHIFT) 106*4882a593Smuzhiyun #define PHY_DTAR1 (0x01C << PHY_REG_SHIFT) 107*4882a593Smuzhiyun #define PHY_DTAR2 (0x01D << PHY_REG_SHIFT) 108*4882a593Smuzhiyun #define PHY_DTAR3 (0x01E << PHY_REG_SHIFT) 109*4882a593Smuzhiyun #define PHY_DTDR0 (0x01F << PHY_REG_SHIFT) 110*4882a593Smuzhiyun #define PHY_DTDR1 (0x020 << PHY_REG_SHIFT) 111*4882a593Smuzhiyun #define PHY_DTEDR0 (0x021 << PHY_REG_SHIFT) 112*4882a593Smuzhiyun #define PHY_DTEDR1 (0x022 << PHY_REG_SHIFT) 113*4882a593Smuzhiyun #define PHY_PGCR2 (0x023 << PHY_REG_SHIFT) 114*4882a593Smuzhiyun #define PHY_GPR0 (0x05E << PHY_REG_SHIFT) 115*4882a593Smuzhiyun #define PHY_GPR1 (0x05F << PHY_REG_SHIFT) 116*4882a593Smuzhiyun /* ZQ */ 117*4882a593Smuzhiyun #define PHY_ZQ_BASE (0x060 << PHY_REG_SHIFT) 118*4882a593Smuzhiyun #define PHY_ZQ_STRIDE (0x004 << PHY_REG_SHIFT) 119*4882a593Smuzhiyun #define PHY_ZQ_CR0 (0x000 << PHY_REG_SHIFT) 120*4882a593Smuzhiyun #define PHY_ZQ_CR1 (0x001 << PHY_REG_SHIFT) 121*4882a593Smuzhiyun #define PHY_ZQ_SR0 (0x002 << PHY_REG_SHIFT) 122*4882a593Smuzhiyun #define PHY_ZQ_SR1 (0x003 << PHY_REG_SHIFT) 123*4882a593Smuzhiyun /* DATX8 */ 124*4882a593Smuzhiyun #define PHY_DX_BASE (0x070 << PHY_REG_SHIFT) 125*4882a593Smuzhiyun #define PHY_DX_STRIDE (0x010 << PHY_REG_SHIFT) 126*4882a593Smuzhiyun #define PHY_DX_GCR (0x000 << PHY_REG_SHIFT) 127*4882a593Smuzhiyun #define PHY_DX_GCR_WLRKEN_SHIFT 26 /* Write Level Rank Enable */ 128*4882a593Smuzhiyun #define PHY_DX_GCR_WLRKEN_MASK (0xf << (PHY_DX_GCR_WLRKEN_SHIFT)) 129*4882a593Smuzhiyun #define PHY_DX_GSR0 (0x001 << PHY_REG_SHIFT) 130*4882a593Smuzhiyun #define PHY_DX_GSR1 (0x002 << PHY_REG_SHIFT) 131*4882a593Smuzhiyun #define PHY_DX_BDLR0 (0x003 << PHY_REG_SHIFT) 132*4882a593Smuzhiyun #define PHY_DX_BDLR1 (0x004 << PHY_REG_SHIFT) 133*4882a593Smuzhiyun #define PHY_DX_BDLR2 (0x005 << PHY_REG_SHIFT) 134*4882a593Smuzhiyun #define PHY_DX_BDLR3 (0x006 << PHY_REG_SHIFT) 135*4882a593Smuzhiyun #define PHY_DX_BDLR4 (0x007 << PHY_REG_SHIFT) 136*4882a593Smuzhiyun #define PHY_DX_LCDLR0 (0x008 << PHY_REG_SHIFT) 137*4882a593Smuzhiyun #define PHY_DX_LCDLR1 (0x009 << PHY_REG_SHIFT) 138*4882a593Smuzhiyun #define PHY_DX_LCDLR2 (0x00A << PHY_REG_SHIFT) 139*4882a593Smuzhiyun #define PHY_DX_MDLR (0x00B << PHY_REG_SHIFT) 140*4882a593Smuzhiyun #define PHY_DX_GTR (0x00C << PHY_REG_SHIFT) 141*4882a593Smuzhiyun #define PHY_DX_GSR2 (0x00D << PHY_REG_SHIFT) 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun #endif /* ARCH_DDRPHY_REGS_H */ 144