1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef _ASM_HPET_H 3*4882a593Smuzhiyun #define _ASM_HPET_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #ifdef CONFIG_RS780_HPET 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #define HPET_MMAP_SIZE 1024 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define HPET_ID 0x000 10*4882a593Smuzhiyun #define HPET_PERIOD 0x004 11*4882a593Smuzhiyun #define HPET_CFG 0x010 12*4882a593Smuzhiyun #define HPET_STATUS 0x020 13*4882a593Smuzhiyun #define HPET_COUNTER 0x0f0 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define HPET_Tn_CFG(n) (0x100 + 0x20 * n) 16*4882a593Smuzhiyun #define HPET_Tn_CMP(n) (0x108 + 0x20 * n) 17*4882a593Smuzhiyun #define HPET_Tn_ROUTE(n) (0x110 + 0x20 * n) 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define HPET_T0_IRS 0x001 20*4882a593Smuzhiyun #define HPET_T1_IRS 0x002 21*4882a593Smuzhiyun #define HPET_T3_IRS 0x004 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define HPET_T0_CFG 0x100 24*4882a593Smuzhiyun #define HPET_T0_CMP 0x108 25*4882a593Smuzhiyun #define HPET_T0_ROUTE 0x110 26*4882a593Smuzhiyun #define HPET_T1_CFG 0x120 27*4882a593Smuzhiyun #define HPET_T1_CMP 0x128 28*4882a593Smuzhiyun #define HPET_T1_ROUTE 0x130 29*4882a593Smuzhiyun #define HPET_T2_CFG 0x140 30*4882a593Smuzhiyun #define HPET_T2_CMP 0x148 31*4882a593Smuzhiyun #define HPET_T2_ROUTE 0x150 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define HPET_ID_REV 0x000000ff 34*4882a593Smuzhiyun #define HPET_ID_NUMBER 0x00001f00 35*4882a593Smuzhiyun #define HPET_ID_64BIT 0x00002000 36*4882a593Smuzhiyun #define HPET_ID_LEGSUP 0x00008000 37*4882a593Smuzhiyun #define HPET_ID_VENDOR 0xffff0000 38*4882a593Smuzhiyun #define HPET_ID_NUMBER_SHIFT 8 39*4882a593Smuzhiyun #define HPET_ID_VENDOR_SHIFT 16 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define HPET_CFG_ENABLE 0x001 42*4882a593Smuzhiyun #define HPET_CFG_LEGACY 0x002 43*4882a593Smuzhiyun #define HPET_LEGACY_8254 2 44*4882a593Smuzhiyun #define HPET_LEGACY_RTC 8 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define HPET_TN_LEVEL 0x0002 47*4882a593Smuzhiyun #define HPET_TN_ENABLE 0x0004 48*4882a593Smuzhiyun #define HPET_TN_PERIODIC 0x0008 49*4882a593Smuzhiyun #define HPET_TN_PERIODIC_CAP 0x0010 50*4882a593Smuzhiyun #define HPET_TN_64BIT_CAP 0x0020 51*4882a593Smuzhiyun #define HPET_TN_SETVAL 0x0040 52*4882a593Smuzhiyun #define HPET_TN_32BIT 0x0100 53*4882a593Smuzhiyun #define HPET_TN_ROUTE 0x3e00 54*4882a593Smuzhiyun #define HPET_TN_FSB 0x4000 55*4882a593Smuzhiyun #define HPET_TN_FSB_CAP 0x8000 56*4882a593Smuzhiyun #define HPET_TN_ROUTE_SHIFT 9 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* Max HPET Period is 10^8 femto sec as in HPET spec */ 59*4882a593Smuzhiyun #define HPET_MAX_PERIOD 100000000UL 60*4882a593Smuzhiyun /* 61*4882a593Smuzhiyun * Min HPET period is 10^5 femto sec just for safety. If it is less than this, 62*4882a593Smuzhiyun * then 32 bit HPET counter wrapsaround in less than 0.5 sec. 63*4882a593Smuzhiyun */ 64*4882a593Smuzhiyun #define HPET_MIN_PERIOD 100000UL 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #define HPET_ADDR 0x20000 67*4882a593Smuzhiyun #define HPET_MMIO_ADDR 0x90000e0000020000 68*4882a593Smuzhiyun #define HPET_FREQ 14318780 69*4882a593Smuzhiyun #define HPET_COMPARE_VAL ((HPET_FREQ + HZ / 2) / HZ) 70*4882a593Smuzhiyun #define HPET_T0_IRQ 0 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun extern void __init setup_hpet_timer(void); 73*4882a593Smuzhiyun #endif /* CONFIG_RS780_HPET */ 74*4882a593Smuzhiyun #endif /* _ASM_HPET_H */ 75