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/rk3399_rockchip-uboot/arch/arm/mach-exynos/
H A Dclock.c5 * SPDX-License-Identifier: GPL-2.0+
33 {PERIPH_ID_UART0, 0xf, 0xf, -1, 0, 0, -1},
34 {PERIPH_ID_UART1, 0xf, 0xf, -1, 4, 4, -1},
35 {PERIPH_ID_UART2, 0xf, 0xf, -1, 8, 8, -1},
36 {PERIPH_ID_UART3, 0xf, 0xf, -1, 12, 12, -1},
37 {PERIPH_ID_I2C0, -1, 0x7, 0x7, -1, 24, 0},
38 {PERIPH_ID_I2C1, -1, 0x7, 0x7, -1, 24, 0},
39 {PERIPH_ID_I2C2, -1, 0x7, 0x7, -1, 24, 0},
40 {PERIPH_ID_I2C3, -1, 0x7, 0x7, -1, 24, 0},
41 {PERIPH_ID_I2C4, -1, 0x7, 0x7, -1, 24, 0},
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-at91/include/mach/
H A Datmel_mpddrc.h8 * SPDX-License-Identifier: GPL-2.0+
36 u32 lpr; /* 0x1c: Low-power Register */
39 u32 lpddr23_lpr; /* 0x28: LPDDR2-LPDDR3 Low-power Register*/
109 #define ATMEL_MPDDRC_TPR0_TRAS_MASK 0xf
111 #define ATMEL_MPDDRC_TPR0_TRCD_MASK 0xf
113 #define ATMEL_MPDDRC_TPR0_TWR_MASK 0xf
115 #define ATMEL_MPDDRC_TPR0_TRC_MASK 0xf
117 #define ATMEL_MPDDRC_TPR0_TRP_MASK 0xf
119 #define ATMEL_MPDDRC_TPR0_TRRD_MASK 0xf
125 #define ATMEL_MPDDRC_TPR0_TMRD_MASK 0xf
[all …]
H A Dsama5d3_smc.h4 * Static Memory Controllers (SMC) - System peripherals registers.
7 * SPDX-License-Identifier: GPL-2.0+
47 #define AT91_SMC_TIMINGS_TCLR(x) (x & 0xf)
48 #define AT91_SMC_TIMINGS_TADL(x) ((x & 0xf) << 4)
49 #define AT91_SMC_TIMINGS_TAR(x) ((x & 0xf) << 8)
51 #define AT91_SMC_TIMINGS_TRR(x) ((x & 0xf) << 16)
52 #define AT91_SMC_TIMINGS_TWB(x) ((x & 0xf) << 24)
53 #define AT91_SMC_TIMINGS_RBNSEL(x) ((x & 0xf) << 28)
69 #define AT91_SMC_MODE_TDF_CYCLE(x) ((x & 0xf) << 16)
H A Dat91sam9_sdramc.h2 * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_wdt.h]
4 * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
8 * SDRAM Controllers (SDRAMC) - System peripherals registers.
11 * SPDX-License-Identifier: GPL-2.0+
47 #define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */
79 #define AT91_SDRAMC_TWR (0xf << 8) /* Write Recovery Delay */
81 #define AT91_SDRAMC_TRC (0xf << 12) /* Row Cycle Delay */
83 #define AT91_SDRAMC_TRP (0xf << 16) /* Row Precharge Delay */
85 #define AT91_SDRAMC_TRCD (0xf << 20) /* Row to Column Delay */
87 #define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */
[all …]
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-omap3/
H A Domap3-regs.h4 * SPDX-License-Identifier: GPL-2.0+
15 * GPMC_CONFIG1 - GPMC_CONFIG7
18 /* Values for GPMC_CONFIG1 - signal control parameters */
40 /* Values for GPMC_CONFIG2 - CS timing */
44 #define CSONTIME(x) (((x) & 0xf) << 0)
46 /* Values for GPMC_CONFIG3 - nADV timing */
50 #define ADVONTIME(x) (((x) & 0xf) << 0)
52 /* Values for GPMC_CONFIG4 - nWE and nOE timing */
55 #define WEONTIME(x) (((x) & 0xf) << 16)
58 #define OEONTIME(x) (((x) & 0xf) << 0)
[all …]
/rk3399_rockchip-uboot/include/andestech/
H A Dandes_pcu.h5 * SPDX-License-Identifier: GPL-2.0+
25 unsigned int rev; /* 0x00 - PCU Revision */
26 unsigned int spinfo; /* 0x04 - Scratch Pad Info */
27 unsigned int rsvd1[2]; /* 0x08-0x0C: Reserved */
28 unsigned int soc_id; /* 0x10 - SoC ID */
29 unsigned int soc_ahb; /* 0x14 - SoC AHB configuration */
30 unsigned int soc_apb; /* 0x18 - SoC APB configuration */
32 unsigned int dcsrcr0; /* 0x20 - Driving Capability
34 unsigned int dcsrcr1; /* 0x24 - Driving Capability
36 unsigned int dcsrcr2; /* 0x28 - Driving Capability
[all …]
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk3506.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Finley Xiao <finley.xiao@rock-chips.com>
109 CLK_GPLL_DIV_MASK = 0xf << CLK_GPLL_DIV_SHIFT,
111 CLK_GPLL_DIV_100M_MASK = 0xf << CLK_GPLL_DIV_100M_SHIFT,
115 CLK_V0PLL_DIV_MASK = 0xf << CLK_V0PLL_DIV_SHIFT,
117 CLK_V1PLL_DIV_MASK = 0xf << CLK_V1PLL_DIV_SHIFT,
133 ACLK_CORE_DIV_MASK = 0xf << ACLK_CORE_DIV_SHIFT,
137 PCLK_CORE_DIV_MASK = 0xf << PCLK_CORE_DIV_SHIFT,
167 CLK_I2C0_DIV_MASK = 0xf << CLK_I2C0_DIV_SHIFT,
174 CLK_I2C1_DIV_MASK = 0xf << CLK_I2C1_DIV_SHIFT,
[all …]
/rk3399_rockchip-uboot/include/synopsys/
H A Ddwcddr21mctl.h5 * SPDX-License-Identifier: GPL-2.0+
9 * DWCDDR21MCTL - Synopsys DWC DDR2/DDR1 Memory Controller
75 #define DWCDDR21MCTL_DCR_CMD(x) (((x) & 0xf) << 27)
81 #define DWCDDR21MCTL_IOCR_RTT(x) (((x) & 0xf) << 0)
82 #define DWCDDR21MCTL_IOCR_DS(x) (((x) & 0xf) << 4)
104 #define DWCDDR21MCTL_DRR_RFBURST(x) (((x) & 0xf) << 24)
113 #define DWCDDR21MCTL_TPR0_TRP(x) (((x) & 0xf) << 8)
114 #define DWCDDR21MCTL_TPR0_TRCD(x) (((x) & 0xf) << 12)
116 #define DWCDDR21MCTL_TPR0_TRRD(x) (((x) & 0xf) << 21)
128 #define DWCDDR21MCTL_TPR1_XCL(x) (((x) & 0xf) << 23)
[all …]
/rk3399_rockchip-uboot/arch/arm/cpu/arm920t/imx/
H A Dspeed.c5 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/imx-regs.h>
14 /* ------------------------------------------------------------------------- */
22 /* ------------------------------------------------------------------------- */
28 u32 mfi = (spctl0 >> 10) & 0xf; in get_systemPLLCLK()
31 u32 pd = (spctl0 >> 26) & 0xf; in get_systemPLLCLK()
42 u32 mfi = (mpctl0 >> 10) & 0xf; in get_mcuPLLCLK()
45 u32 pd = (mpctl0 >> 26) & 0xf; in get_mcuPLLCLK()
60 u32 bclkdiv = (( CSCR >> 10 ) & 0xf) + 1; in get_HCLK()
73 return get_systemPLLCLK() / (((PCDR) & 0xf)+1); in get_PERCLK1()
[all …]
/rk3399_rockchip-uboot/drivers/ddr/marvell/a38x/
H A Dddr3_training_ip_engine.c4 * SPDX-License-Identifier: GPL-2.0
19 ((((e2) - (e1) + 1) > 33) && ((e1) < 67))
92 {0xf, 0x7, 2, 0x7, 0x0140, 16}, /* PATTERN_STATIC_PBS */
93 {0xf, 0x7, 2, 0x7, 0x0190, 16}, /* PATTERN_KILLER_DQ0 */
94 {0xf, 0x7, 2, 0x7, 0x01d0, 16}, /* PATTERN_KILLER_DQ1 */
95 {0xf, 0x7, 2, 0x7, 0x0210, 16}, /* PATTERN_KILLER_DQ2 */
96 {0xf, 0x7, 2, 0x7, 0x0250, 16}, /* PATTERN_KILLER_DQ3 */
97 {0xf, 0x7, 2, 0x7, 0x0290, 16}, /* PATTERN_KILLER_DQ4 */
98 {0xf, 0x7, 2, 0x7, 0x02d0, 16}, /* PATTERN_KILLER_DQ5 */
99 {0xf, 0x7, 2, 0x7, 0x0310, 16}, /* PATTERN_KILLER_DQ6 */
[all …]
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-mxs/
H A Dregs-lradc.h8 * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
10 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/mach-imx/regs-common.h>
98 #define LRADC_CTRL2_TEMP_ISRC1_MASK (0xf << 4)
100 #define LRADC_CTRL2_TEMP_ISRC1_300 (0xf << 4)
116 #define LRADC_CTRL2_TEMP_ISRC0_MASK (0xf << 0)
118 #define LRADC_CTRL2_TEMP_ISRC0_300 (0xf << 0)
185 #define LRADC_DELAY_TRIGGER_DELAYS_MASK (0xf << 16)
215 #define LRADC_CTRL4_LRADC7SELECT_MASK (0xf << 28)
232 #define LRADC_CTRL4_LRADC7SELECT_CHANNEL15 (0xf << 28)
[all …]
H A Dregs-usbphy.h7 * SPDX-License-Identifier: GPL-2.0+
40 #define USBPHY_TX_TXCAL45DP_MASK (0xf << 16)
43 #define USBPHY_TX_TXCAL45DM_MASK (0xf << 8)
45 #define USBPHY_TX_D_CAL_MASK 0xf
91 #define USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK (0xf << 25)
97 #define USBPHY_DEBUG_TX2RXCOUNT_MASK (0xf << 8)
116 #define USBPHY_DEBUG1_DBG_ADDRESS_MASK 0xf
/rk3399_rockchip-uboot/board/samsung/odroid/
H A Dsetup.h5 * SPDX-License-Identifier: GPL-2.0+
86 #define MUX_PWI_SEL(x) (((x) & 0xf) << 16)
96 /* #define PWI_SEL(x) (((x) & 0xf) << 16) - Reserved */
133 #define G2D_ACP_RATIO(x) ((x) & 0xf)
135 #define PWI_RATIO(x) (((x) & 0xf) << 8)
156 #define UART4_SEL(x) (((x) & 0xf) << 16)
157 #define UART3_SEL(x) (((x) & 0xf) << 12)
158 #define UART2_SEL(x) (((x) & 0xf) << 8)
159 #define UART1_SEL(x) (((x) & 0xf) << 4)
160 #define UART0_SEL(x) ((x) & 0xf)
[all …]
/rk3399_rockchip-uboot/cmd/ddr_tool/ddr_test/
H A Dddr_test_rk1808.S1 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
6 .arch armv8-a+nosimd
21 stp x29, x30, [sp, -144]!
23 .cfi_offset 29, -144
24 .cfi_offset 30, -136
28 .cfi_offset 21, -112
29 .cfi_offset 22, -104
34 .cfi_offset 23, -96
35 .cfi_offset 24, -88
45 .cfi_offset 19, -128
[all …]
H A Dddr_test_rk3328.S1 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
6 .arch armv8-a+nosimd
21 stp x29, x30, [sp, -144]!
23 .cfi_offset 29, -144
24 .cfi_offset 30, -136
28 .cfi_offset 21, -112
29 .cfi_offset 22, -104
34 .cfi_offset 23, -96
35 .cfi_offset 24, -88
45 .cfi_offset 19, -128
[all …]
H A Dddr_test_px30.S1 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
6 .arch armv8-a+nosimd
21 stp x29, x30, [sp, -144]!
23 .cfi_offset 29, -144
24 .cfi_offset 30, -136
28 .cfi_offset 21, -112
29 .cfi_offset 22, -104
34 .cfi_offset 23, -96
35 .cfi_offset 24, -88
45 .cfi_offset 19, -128
[all …]
/rk3399_rockchip-uboot/include/faraday/
H A Dftsmc020.h3 * Po-Yu Chuang <ratbert@faraday-tech.com>
5 * SPDX-License-Identifier: GPL-2.0+
22 struct ftsmc020_bank bank[4]; /* 0x00 - 0x1c */
23 unsigned int pad[8]; /* 0x20 - 0x3c */
47 #define FTSMC020_BANK_SIZE_512K (0xf << 4)
63 #define FTSMC020_TPR_ETRNA(x) (((x) & 0xf) << 28)
64 #define FTSMC020_TPR_EATI(x) (((x) & 0xf) << 24)
68 #define FTSMC020_TPR_ATI(x) (((x) & 0xf) << 12)
72 #define FTSMC020_TPR_TRNA(x) (((x) & 0xf) << 0)
H A Dftsdmc020.h3 * Po-Yu Chuang <ratbert@faraday-tech.com>
5 * SPDX-License-Identifier: GPL-2.0+
32 #define FTSDMC020_TP0_TRF(x) (((x) & 0xf) << 8)
34 #define FTSDMC020_TP0_TRP(x) (((x) & 0xf) << 16)
35 #define FTSDMC020_TP0_TRAS(x) (((x) & 0xf) << 20)
41 #define FTSDMC020_TP1_INI_REFT(x) (((x) & 0xf) << 16)
42 #define FTSDMC020_TP1_INI_PREC(x) (((x) & 0xf) << 20)
H A Dftsdmc021.h3 * Po-Yu Chuang <ratbert@faraday-tech.com>
8 * SPDX-License-Identifier: GPL-2.0+
12 * FTSDMC021 - SDRAM Controller
19 unsigned int tp1; /* 0x00 - SDRAM Timing Parameter 1 */
20 unsigned int tp2; /* 0x04 - SDRAM Timing Parameter 2 */
21 unsigned int cr1; /* 0x08 - SDRAM Configuration Reg 1 */
22 unsigned int cr2; /* 0x0c - SDRAM Configuration Reg 2 */
23 unsigned int bank0_bsr; /* 0x10 - Ext. Bank Base/Size Reg 0 */
24 unsigned int bank1_bsr; /* 0x14 - Ext. Bank Base/Size Reg 1 */
25 unsigned int bank2_bsr; /* 0x18 - Ext. Bank Base/Size Reg 2 */
[all …]
/rk3399_rockchip-uboot/arch/mips/mach-ath79/qca953x/
H A Dddr.c2 * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
5 * SPDX-License-Identifier: GPL-2.0+
32 #define DDR_TRCD_M 0xf
35 #define DDR_TRP_M 0xf
38 #define DDR_TRRD_M 0xf
44 #define DDR_TMRD_M 0xf
61 #define DDR_BURST_LEN_M 0xf
68 #define DDR_TWR_M 0xf
74 #define DDR_TRTP_M 0xf
80 #define DDR_G_OPEN_L_M 0xf
[all …]
/rk3399_rockchip-uboot/drivers/net/
H A Darmada100_fec.c4 * Written-by: Ajay Bhargav <contact@8051projects.net>
10 * SPDX-License-Identifier: GPL-2.0+
32 struct armdfec_reg *regs = darmdfec->regs; in eth_dump_regs()
35 printf("\noffset: phy_adr, value: 0x%x\n", readl(&regs->phyadr)); in eth_dump_regs()
36 printf("offset: smi, value: 0x%x\n", readl(&regs->smi)); in eth_dump_regs()
49 while (--timeout) { in armdfec_phy_timeout()
64 struct eth_device *dev = eth_get_dev_by_name(bus->name); in smi_reg_read()
66 struct armdfec_reg *regs = darmdfec->regs; in smi_reg_read()
70 val = readl(&regs->phyadr); in smi_reg_read()
79 return -EINVAL; in smi_reg_read()
[all …]
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-vf610/
H A Dimx-regs.h2 * Copyright 2013-2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
143 #define DDRMC_CR14_TWTR(v) (((v) & 0xf) << 8)
146 #define DDRMC_CR16_TRTP(v) (((v) & 0xf) << 16)
168 #define DDRMC_CR34_CKSRX(v) (((v) & 0xf) << 16)
169 #define DDRMC_CR34_CKSRE(v) (((v) & 0xf) << 8)
180 #define DDRMC_CR69_ZQ_ON_SREF_EX(v) (((v) & 0xf) << 8)
183 #define DDRMC_CR73_APREBIT(v) (((v) & 0xf) << 24)
202 #define DDRMC_CR78_BUR_ON_FLY_BIT(v) ((v) & 0xf)
208 #define DDRMC_CR89_AODT_RWSMCS(v) ((v) & 0xf)
[all …]
/rk3399_rockchip-uboot/drivers/ram/rockchip/
H A Dsdram_phy_px30.c1 // SPDX-License-Identifier: GPL-2.0
79 writel(dqs_drv, PHY_REG(phy_base, j + 0xf)); in sdram_phy_set_ds_odt()
99 clrsetbits_le32(PHY_REG(phy_base, 0), 0xf << 4, 0xf << 4); in phy_dram_set_bw()
103 clrsetbits_le32(PHY_REG(phy_base, 0), 0xf << 4, 3 << 4); in phy_dram_set_bw()
107 clrsetbits_le32(PHY_REG(phy_base, 0), 0xf << 4, 1 << 4); in phy_dram_set_bw()
156 ret = -1; in phy_data_training()
158 ret = (ret & 0xf) ^ (readl(PHY_REG(phy_base, 0)) >> 4); in phy_data_training()
159 ret = (ret == 0) ? 0 : -1; in phy_data_training()
176 sdram_phy_dll_bypass_set(phy_base, base->ddr_freq); in phy_cfg()
177 for (i = 0; phy_regs->phy[i][0] != 0xFFFFFFFF; i++) { in phy_cfg()
[all …]
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-sunxi/
H A Dclock_sun6i.h4 * (C) Copyright 2007-2011
8 * SPDX-License-Identifier: GPL-2.0+
174 #define APB2_CLK_RATE_M(m) (((m)-1) << 0)
181 #define APB2_GATE_TWI_MASK (0xf << APB2_GATE_TWI_SHIFT)
199 #define CCM_PLL1_CTRL_M(n) ((((n) - 1) & 0x3) << 0)
200 #define CCM_PLL1_CTRL_K(n) ((((n) - 1) & 0x3) << 4)
201 #define CCM_PLL1_CTRL_N(n) ((((n) - 1) & 0x1f) << 8)
206 #define CCM_PLL3_CTRL_M_MASK (0xf << CCM_PLL3_CTRL_M_SHIFT)
207 #define CCM_PLL3_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
210 #define CCM_PLL3_CTRL_N(n) ((((n) - 1) & 0x7f) << 8)
[all …]
/rk3399_rockchip-uboot/arch/arm/include/asm/
H A Demif.h4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
78 #define EMIF_REG_CL_MASK (0xf << 10)
116 #define EMIF_REG_T_RP_MASK (0xf << 25)
118 #define EMIF_REG_T_RCD_MASK (0xf << 21)
120 #define EMIF_REG_T_WR_MASK (0xf << 17)
132 #define EMIF_REG_T_RP_SHDW_MASK (0xf << 25)
134 #define EMIF_REG_T_RCD_SHDW_MASK (0xf << 21)
136 #define EMIF_REG_T_WR_SHDW_MASK (0xf << 17)
184 #define EMIF_REG_T_RAS_MAX_MASK (0xf << 0)
196 #define EMIF_REG_T_RAS_MAX_SHDW_MASK (0xf << 0)
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