1*af930827SMasahiro Yamada /* 2*af930827SMasahiro Yamada * Copyright (C) 2012 Atmel Corporation. 3*af930827SMasahiro Yamada * 4*af930827SMasahiro Yamada * Static Memory Controllers (SMC) - System peripherals registers. 5*af930827SMasahiro Yamada * Based on SAMA5D3 datasheet. 6*af930827SMasahiro Yamada * 7*af930827SMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+ 8*af930827SMasahiro Yamada */ 9*af930827SMasahiro Yamada 10*af930827SMasahiro Yamada #ifndef SAMA5D3_SMC_H 11*af930827SMasahiro Yamada #define SAMA5D3_SMC_H 12*af930827SMasahiro Yamada 13*af930827SMasahiro Yamada #ifdef __ASSEMBLY__ 14*af930827SMasahiro Yamada #define AT91_ASM_SMC_SETUP0 (ATMEL_BASE_SMC + 0x600) 15*af930827SMasahiro Yamada #define AT91_ASM_SMC_PULSE0 (ATMEL_BASE_SMC + 0x604) 16*af930827SMasahiro Yamada #define AT91_ASM_SMC_CYCLE0 (ATMEL_BASE_SMC + 0x608) 17*af930827SMasahiro Yamada #define AT91_ASM_SMC_TIMINGS0 (ATMEL_BASE_SMC + 0x60c) 18*af930827SMasahiro Yamada #define AT91_ASM_SMC_MODE0 (ATMEL_BASE_SMC + 0x610) 19*af930827SMasahiro Yamada #else 20*af930827SMasahiro Yamada struct at91_cs { 21*af930827SMasahiro Yamada u32 setup; /* 0x600 SMC Setup Register */ 22*af930827SMasahiro Yamada u32 pulse; /* 0x604 SMC Pulse Register */ 23*af930827SMasahiro Yamada u32 cycle; /* 0x608 SMC Cycle Register */ 24*af930827SMasahiro Yamada u32 timings; /* 0x60C SMC Cycle Register */ 25*af930827SMasahiro Yamada u32 mode; /* 0x610 SMC Mode Register */ 26*af930827SMasahiro Yamada }; 27*af930827SMasahiro Yamada 28*af930827SMasahiro Yamada struct at91_smc { 29*af930827SMasahiro Yamada u32 reserved[384]; 30*af930827SMasahiro Yamada struct at91_cs cs[4]; 31*af930827SMasahiro Yamada }; 32*af930827SMasahiro Yamada #endif /* __ASSEMBLY__ */ 33*af930827SMasahiro Yamada 34*af930827SMasahiro Yamada #define AT91_SMC_SETUP_NWE(x) (x & 0x3f) 35*af930827SMasahiro Yamada #define AT91_SMC_SETUP_NCS_WR(x) ((x & 0x3f) << 8) 36*af930827SMasahiro Yamada #define AT91_SMC_SETUP_NRD(x) ((x & 0x3f) << 16) 37*af930827SMasahiro Yamada #define AT91_SMC_SETUP_NCS_RD(x) ((x & 0x3f) << 24) 38*af930827SMasahiro Yamada 39*af930827SMasahiro Yamada #define AT91_SMC_PULSE_NWE(x) (x & 0x3f) 40*af930827SMasahiro Yamada #define AT91_SMC_PULSE_NCS_WR(x) ((x & 0x3f) << 8) 41*af930827SMasahiro Yamada #define AT91_SMC_PULSE_NRD(x) ((x & 0x3f) << 16) 42*af930827SMasahiro Yamada #define AT91_SMC_PULSE_NCS_RD(x) ((x & 0x3f) << 24) 43*af930827SMasahiro Yamada 44*af930827SMasahiro Yamada #define AT91_SMC_CYCLE_NWE(x) (x & 0x1ff) 45*af930827SMasahiro Yamada #define AT91_SMC_CYCLE_NRD(x) ((x & 0x1ff) << 16) 46*af930827SMasahiro Yamada 47*af930827SMasahiro Yamada #define AT91_SMC_TIMINGS_TCLR(x) (x & 0xf) 48*af930827SMasahiro Yamada #define AT91_SMC_TIMINGS_TADL(x) ((x & 0xf) << 4) 49*af930827SMasahiro Yamada #define AT91_SMC_TIMINGS_TAR(x) ((x & 0xf) << 8) 50*af930827SMasahiro Yamada #define AT91_SMC_TIMINGS_OCMS(x) ((x & 0x1) << 12) 51*af930827SMasahiro Yamada #define AT91_SMC_TIMINGS_TRR(x) ((x & 0xf) << 16) 52*af930827SMasahiro Yamada #define AT91_SMC_TIMINGS_TWB(x) ((x & 0xf) << 24) 53*af930827SMasahiro Yamada #define AT91_SMC_TIMINGS_RBNSEL(x) ((x & 0xf) << 28) 54*af930827SMasahiro Yamada #define AT91_SMC_TIMINGS_NFSEL(x) ((x & 0x1) << 31) 55*af930827SMasahiro Yamada 56*af930827SMasahiro Yamada #define AT91_SMC_MODE_RM_NCS 0x00000000 57*af930827SMasahiro Yamada #define AT91_SMC_MODE_RM_NRD 0x00000001 58*af930827SMasahiro Yamada #define AT91_SMC_MODE_WM_NCS 0x00000000 59*af930827SMasahiro Yamada #define AT91_SMC_MODE_WM_NWE 0x00000002 60*af930827SMasahiro Yamada 61*af930827SMasahiro Yamada #define AT91_SMC_MODE_EXNW_DISABLE 0x00000000 62*af930827SMasahiro Yamada #define AT91_SMC_MODE_EXNW_FROZEN 0x00000020 63*af930827SMasahiro Yamada #define AT91_SMC_MODE_EXNW_READY 0x00000030 64*af930827SMasahiro Yamada 65*af930827SMasahiro Yamada #define AT91_SMC_MODE_BAT 0x00000100 66*af930827SMasahiro Yamada #define AT91_SMC_MODE_DBW_8 0x00000000 67*af930827SMasahiro Yamada #define AT91_SMC_MODE_DBW_16 0x00001000 68*af930827SMasahiro Yamada #define AT91_SMC_MODE_DBW_32 0x00002000 69*af930827SMasahiro Yamada #define AT91_SMC_MODE_TDF_CYCLE(x) ((x & 0xf) << 16) 70*af930827SMasahiro Yamada #define AT91_SMC_MODE_TDF 0x00100000 71*af930827SMasahiro Yamada #define AT91_SMC_MODE_PMEN 0x01000000 72*af930827SMasahiro Yamada #define AT91_SMC_MODE_PS_4 0x00000000 73*af930827SMasahiro Yamada #define AT91_SMC_MODE_PS_8 0x10000000 74*af930827SMasahiro Yamada #define AT91_SMC_MODE_PS_16 0x20000000 75*af930827SMasahiro Yamada #define AT91_SMC_MODE_PS_32 0x30000000 76*af930827SMasahiro Yamada 77*af930827SMasahiro Yamada #endif 78