100d10eb0SMacpaul Lin /* 200d10eb0SMacpaul Lin * (C) Copyright 2009 Faraday Technology 300d10eb0SMacpaul Lin * Po-Yu Chuang <ratbert@faraday-tech.com> 400d10eb0SMacpaul Lin * 5*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 600d10eb0SMacpaul Lin */ 700d10eb0SMacpaul Lin 800d10eb0SMacpaul Lin /* 900d10eb0SMacpaul Lin * Static Memory Controller 1000d10eb0SMacpaul Lin */ 1100d10eb0SMacpaul Lin #ifndef __FTSMC020_H 1200d10eb0SMacpaul Lin #define __FTSMC020_H 1300d10eb0SMacpaul Lin 1400d10eb0SMacpaul Lin #ifndef __ASSEMBLY__ 1500d10eb0SMacpaul Lin 1656cd2472SMacpaul Lin struct ftsmc020_bank { 1756cd2472SMacpaul Lin unsigned int cr; 1856cd2472SMacpaul Lin unsigned int tpr; 1956cd2472SMacpaul Lin }; 2056cd2472SMacpaul Lin 2100d10eb0SMacpaul Lin struct ftsmc020 { 2256cd2472SMacpaul Lin struct ftsmc020_bank bank[4]; /* 0x00 - 0x1c */ 2300d10eb0SMacpaul Lin unsigned int pad[8]; /* 0x20 - 0x3c */ 2400d10eb0SMacpaul Lin unsigned int ssr; /* 0x40 */ 2500d10eb0SMacpaul Lin }; 2600d10eb0SMacpaul Lin 2700d10eb0SMacpaul Lin void ftsmc020_init(void); 2800d10eb0SMacpaul Lin 2900d10eb0SMacpaul Lin #endif /* __ASSEMBLY__ */ 3000d10eb0SMacpaul Lin 3100d10eb0SMacpaul Lin /* 3200d10eb0SMacpaul Lin * Memory Bank Configuration Register 3300d10eb0SMacpaul Lin */ 3400d10eb0SMacpaul Lin #define FTSMC020_BANK_ENABLE (1 << 28) 3500d10eb0SMacpaul Lin #define FTSMC020_BANK_BASE(x) ((x) & 0x0fff1000) 3600d10eb0SMacpaul Lin 3700d10eb0SMacpaul Lin #define FTSMC020_BANK_WPROT (1 << 11) 3800d10eb0SMacpaul Lin 3910ba1d3cSMacpaul Lin #define FTSMC020_BANK_TYPE1 (1 << 10) 4010ba1d3cSMacpaul Lin #define FTSMC020_BANK_TYPE2 (1 << 9) 4110ba1d3cSMacpaul Lin #define FTSMC020_BANK_TYPE3 (1 << 8) 4210ba1d3cSMacpaul Lin 4300d10eb0SMacpaul Lin #define FTSMC020_BANK_SIZE_32K (0xb << 4) 4400d10eb0SMacpaul Lin #define FTSMC020_BANK_SIZE_64K (0xc << 4) 4500d10eb0SMacpaul Lin #define FTSMC020_BANK_SIZE_128K (0xd << 4) 4600d10eb0SMacpaul Lin #define FTSMC020_BANK_SIZE_256K (0xe << 4) 4700d10eb0SMacpaul Lin #define FTSMC020_BANK_SIZE_512K (0xf << 4) 4800d10eb0SMacpaul Lin #define FTSMC020_BANK_SIZE_1M (0x0 << 4) 4900d10eb0SMacpaul Lin #define FTSMC020_BANK_SIZE_2M (0x1 << 4) 5000d10eb0SMacpaul Lin #define FTSMC020_BANK_SIZE_4M (0x2 << 4) 5100d10eb0SMacpaul Lin #define FTSMC020_BANK_SIZE_8M (0x3 << 4) 5200d10eb0SMacpaul Lin #define FTSMC020_BANK_SIZE_16M (0x4 << 4) 5300d10eb0SMacpaul Lin #define FTSMC020_BANK_SIZE_32M (0x5 << 4) 5410ba1d3cSMacpaul Lin #define FTSMC020_BANK_SIZE_64M (0x6 << 4) 5500d10eb0SMacpaul Lin 5600d10eb0SMacpaul Lin #define FTSMC020_BANK_MBW_8 (0x0 << 0) 5700d10eb0SMacpaul Lin #define FTSMC020_BANK_MBW_16 (0x1 << 0) 5800d10eb0SMacpaul Lin #define FTSMC020_BANK_MBW_32 (0x2 << 0) 5900d10eb0SMacpaul Lin 6000d10eb0SMacpaul Lin /* 6100d10eb0SMacpaul Lin * Memory Bank Timing Parameter Register 6200d10eb0SMacpaul Lin */ 6300d10eb0SMacpaul Lin #define FTSMC020_TPR_ETRNA(x) (((x) & 0xf) << 28) 6400d10eb0SMacpaul Lin #define FTSMC020_TPR_EATI(x) (((x) & 0xf) << 24) 6500d10eb0SMacpaul Lin #define FTSMC020_TPR_RBE (1 << 20) 6600d10eb0SMacpaul Lin #define FTSMC020_TPR_AST(x) (((x) & 0x3) << 18) 6700d10eb0SMacpaul Lin #define FTSMC020_TPR_CTW(x) (((x) & 0x3) << 16) 6800d10eb0SMacpaul Lin #define FTSMC020_TPR_ATI(x) (((x) & 0xf) << 12) 6900d10eb0SMacpaul Lin #define FTSMC020_TPR_AT2(x) (((x) & 0x3) << 8) 7000d10eb0SMacpaul Lin #define FTSMC020_TPR_WTC(x) (((x) & 0x3) << 6) 7100d10eb0SMacpaul Lin #define FTSMC020_TPR_AHT(x) (((x) & 0x3) << 4) 7200d10eb0SMacpaul Lin #define FTSMC020_TPR_TRNA(x) (((x) & 0xf) << 0) 7300d10eb0SMacpaul Lin 7400d10eb0SMacpaul Lin #endif /* __FTSMC020_H */ 75