include/andestech/andes_pcu.h

5  * SPDX-License-Identifier:	GPL-2.0+
25 	unsigned int	rev;		/* 0x00 - PCU Revision */
26 	unsigned int	spinfo;		/* 0x04 - Scratch Pad Info */
27 	unsigned int	rsvd1[2];	/* 0x08-0x0C: Reserved */
28 	unsigned int	soc_id;		/* 0x10 - SoC ID */
29 	unsigned int	soc_ahb;	/* 0x14 - SoC AHB configuration */
30 	unsigned int	soc_apb;	/* 0x18 - SoC APB configuration */
32 	unsigned int	dcsrcr0;	/* 0x20 - Driving Capability
34 	unsigned int	dcsrcr1;	/* 0x24 - Driving Capability
36 	unsigned int	dcsrcr2;	/* 0x28 - Driving Capability
39 	unsigned int	mfpsr0;		/* 0x30 - Multi-Func Port Setting 0 */
40 	unsigned int	mfpsr1;		/* 0x34 - Multi-Func Port Setting 1 */
41 	unsigned int	dmaes;		/* 0x38 - DMA Engine Selection */
43 	unsigned int	oscc;		/* 0x40 - OSC Control */
44 	unsigned int	pwmcd;		/* 0x44 - PWM Clock divider */
45 	unsigned int	socmisc;	/* 0x48 - SoC Misc. */
46 	unsigned int	rsvd5[13];	/* 0x4C-0x7C: Reserved */
47 	unsigned int	bsmcr;		/* 0x80 - BSM Controrl */
48 	unsigned int	bsmst;		/* 0x84 - BSM Status */
49 	unsigned int	wes;		/* 0x88 - Wakeup Event Sensitivity*/
50 	unsigned int	west;		/* 0x8C - Wakeup Event Status */
51 	unsigned int	rsttiming;	/* 0x90 - Reset Timing  */
52 	unsigned int	intr_st;	/* 0x94 - PCU Interrupt Status */
53 	unsigned int	rsvd6[2];	/* 0x98-0x9C: Reserved */
54 	struct pcs	pcs1;		/* 0xA0-0xB0: PCS1 (clock scaling) */
55 	unsigned int	pcsrsvd1[3];	/* 0xB4-0xBC: Reserved */
56 	struct pcs	pcs2;		/* 0xC0-0xD0: PCS2 (AHB clock gating) */
57 	unsigned int	pcsrsvd2[3];	/* 0xD4-0xDC: Reserved */
58 	struct pcs	pcs3;		/* 0xE0-0xF0: PCS3 (APB clock gating) */
59 	unsigned int	pcsrsvd3[3];	/* 0xF4-0xFC: Reserved */
60 	struct pcs	pcs4;		/* 0x100-0x110: PCS4 main PLL scaling */
61 	unsigned int	pcsrsvd4[3];	/* 0x114-0x11C: Reserved */
62 	struct pcs	pcs5;		/* 0x120-0x130: PCS5 PCI PLL scaling */
63 	unsigned int	pcsrsvd5[3];	/* 0x134-0x13C: Reserved */
64 	struct pcs	pcs6;		/* 0x140-0x150: PCS6 AC97 PLL scaling */
65 	unsigned int	pcsrsvd6[3];	/* 0x154-0x15C: Reserved */
66 	struct pcs	pcs7;		/* 0x160-0x170: PCS7 GMAC PLL scaling */
67 	unsigned int	pcsrsvd7[3];	/* 0x174-0x17C: Reserved */
68 	struct pcs	pcs8;		/* 0x180-0x190: PCS8 voltage scaling */
69 	unsigned int	pcsrsvd8[3];	/* 0x194-0x19C: Reserved */
70 	struct pcs	pcs9;		/* 0x1A0-0x1B0: PCS9 power control */
71 	unsigned int	pcsrsvd9[93];	/* 0x1B4-0x3FC: Reserved */
72 	unsigned int	pmspdm[40];	/* 0x400-0x4fC: Power Manager
87 #define ANDES_PCU_SPINFO_OFFSET(x)	(((x) >> 8) & 0xf)
92 #define ANDES_PCU_SOC_ID_VER_MINOR(x)	(((x) >> 0) & 0xf)
145 #define ANDES_PCU_DCSRCR0_LPC(x)	(((x) & 0xf) << 8)
146 #define ANDES_PCU_DCSRCR0_ULPI(x)	(((x) & 0xf) << 12)
147 #define ANDES_PCU_DCSRCR0_GMAC(x)	(((x) & 0xf) << 16)
148 #define ANDES_PCU_DCSRCR0_GPU(x)	(((x) & 0xf) << 20)
153 #define ANDES_PCU_DCSRCR1_I2C(x)	(((x) & 0xf) << 0)
158 #define ANDES_PCU_DCSRCR2_UART1(x)	(((x) & 0xf) << 0)
159 #define ANDES_PCU_DCSRCR2_UART2(x)	(((x) & 0xf) << 4)
160 #define ANDES_PCU_DCSRCR2_AC97(x)	(((x) & 0xf) << 8)
161 #define ANDES_PCU_DCSRCR2_SPI(x)	(((x) & 0xf) << 12)
162 #define ANDES_PCU_DCSRCR2_SD(x)		(((x) & 0xf) << 16)
163 #define ANDES_PCU_DCSRCR2_CFC(x)	(((x) & 0xf) << 20)
164 #define ANDES_PCU_DCSRCR2_GPIO(x)	(((x) & 0xf) << 24)
165 #define ANDES_PCU_DCSRCR2_PCU(x)	(((x) & 0xf) << 28)
168  * Multi-function Port Setting Register 0 (rw)
179  * Multi-function Port Setting Register 1 (rw)
223 #define ANDES_PCU_PWMCD_PWMDIV(x)	(((x) & 0xf) << 0)
262 #define ANDES_PCU_BSMCR_LINK0(x)	(((x) & 0xf) << 0)
263 #define ANDES_PCU_BSMCR_LINK1(x)	(((x) & 0xf) << 4)
264 #define ANDES_PCU_BSMCR_SYNCSRC(x)	(((x) & 0xf) << 24)
271 #define ANDES_PCU_BSMSR_CI0(x)		(((x) & 0xf) << 0)
272 #define ANDES_PCU_BSMSR_CI1(x)		(((x) & 0xf) << 4)
273 #define ANDES_PCU_BSMSR_SYNCSRC(x)	(((x) & 0xf) << 24)
274 #define ANDES_PCU_BSMSR_BSMST(x)	(((x) & 0xf) << 28)
312 #define ANDES_PCU_PCSX_CR_LW(x)		(((x) & 0xf) << 16)
313 #define ANDES_PCU_PCSX_CR_LS(x)		(((x) & 0xf) << 20)
320 #define ANDES_PCU_PCSX_PARM_SYNCSRC(x)	(((x) & 0xf) << 24)
327 #define ANDES_PCU_PCSX_STAT1_ERRNO(x)	(((x) & 0xf) << 0)
334 #define ANDES_PCU_PCSX_STAT2_SYNCSRC(x)		(((x) & 0xf) << 24)
338  * This is reserved for PCS(1-7)