rockchip: clk: rk3368: support more clks to set and get rate

Make clock ids consistent with kernel.
Support more clks to set and get rate.
Add clk dump.

Change-Id: I348c98ce81ce76af9c492a30480fcb49

rockchip: clk: rk3368: support more clks to set and get rate

Make clock ids consistent with kernel.
Support more clks to set and get rate.
Add clk dump.

Change-Id: I348c98ce81ce76af9c492a30480fcb495da7ed79
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

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rockchip: clk: px30: Add support to set vopl aclk and dclk rate

Change-Id: I31376ebb8d1d40d46ad4e2b6421b65ac7fae096d
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

rockchip: clk: rk3128: support more clks to set and get rate

Make clock ids consistent with kernel.
support more clks to set and get rate.
add clk init.

Change-Id: I1e6b5734887e0bd5d845f1286f10eb0e

rockchip: clk: rk3128: support more clks to set and get rate

Make clock ids consistent with kernel.
support more clks to set and get rate.
add clk init.

Change-Id: I1e6b5734887e0bd5d845f1286f10eb0e3e42bc08
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

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rockchip: clk: rk322x: support more clks to set and get rate

Change-Id: Ibed40f1826469263a8015d8af2dea4d3567a08e6
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

rockchip: clk: rk3328: support more clks to set and get rate

Change-Id: Ic231b7701c6eb23b0e9db21c1d28fb4d08c4debf
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

rockchip: clk: pll: add common pll setting funcs

Change-Id: I99887338a4f84aead905938eee066b460c4c1b9f
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

ARM64: invalid icache for cortex a35

Different loader can not boot normally in cortex-A35,like rk3308,
because cortex-A35 enable icache in default.

Change-Id: I87f3e8a2539186f3e408fad8ea903c375118b

ARM64: invalid icache for cortex a35

Different loader can not boot normally in cortex-A35,like rk3308,
because cortex-A35 enable icache in default.

Change-Id: I87f3e8a2539186f3e408fad8ea903c375118b1d9
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>

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clk: rockchip: rk3399: add gpll and npll init

remove clk_set_defaults(), need init pll freq as kernel.

Change-Id: I245d01bf65b3092c21a0c2aa06a0a6eaca8528ef
Signed-off-by: Elaine Zhang <zhangqing@ro

clk: rockchip: rk3399: add gpll and npll init

remove clk_set_defaults(), need init pll freq as kernel.

Change-Id: I245d01bf65b3092c21a0c2aa06a0a6eaca8528ef
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

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rockchip: sdram_common: move BROM_BOOTSOURCE_ID_ADDR to sdram_common.h

Change-Id: I35d33524ffb19da21bf12622b5cbfd9933ea5a49
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>

drivers: ram: rockchip: add px30 sdram init code

Change-Id: Ia7496d062d3041e22f26cb9ee91e72f6f463cde5
Signed-off-by: YouMin Chen <cym@rock-chips.com>

rockchip: px30: add UART clock and iomux for TPL_BUILD

Change-Id: Id2fed3e99e0e421063e006fcf857fed889216b72
Signed-off-by: YouMin Chen <cym@rock-chips.com>

rockchip: ARM64: tpl: modify TPL_TINY_FRAMEWORK flow to reduce code size

If sram size is small for TPL build, it can defined
CONFIG_TPL_TINY_FRAMEWORK to reduce TPL size.
For ARM64 if defined CONFIG

rockchip: ARM64: tpl: modify TPL_TINY_FRAMEWORK flow to reduce code size

If sram size is small for TPL build, it can defined
CONFIG_TPL_TINY_FRAMEWORK to reduce TPL size.
For ARM64 if defined CONFIG_TPL_TINY_FRAMEWORK when build TPL, after
save_boot_params(), it jump to board_init_f() directly, then return to
maskrom. and stack also use maskrom defined result, never change the SP.

Change-Id: I80dc414fcc276f5ea2c09afd6d1eb16e2f2f4cf6
Signed-off-by: YouMin Chen <cym@rock-chips.com>

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rockchip: tpl: rename CONFIG_TINY_TPL to CONFIG_TPL_TINY_FRAMEWORK

Change-Id: Ia05a73467578f5620a9ba168e67bcfb02c40e1d0
Signed-off-by: YouMin Chen <cym@rock-chips.com>

rockchip: sdram: change sdram_init return value to int

Change-Id: Iccd78d83e898683d7315dfa1670a0308a5863824
Signed-off-by: YouMin Chen <cym@rock-chips.com>

rockchip: sdram: the enum of DDR type move to sdram_common.h

Change-Id: I62877384b6f0ee232e9765143b3deea2c5693a36
Signed-off-by: YouMin Chen <cym@rock-chips.com>

armv8: exceptions: optimize exception regs info

Add arm core registers bits description, it looks like:

Relocate offset = 000000003db55000
* ELR(PC) = 000000000025bd78
* LR = 0000000

armv8: exceptions: optimize exception regs info

Add arm core registers bits description, it looks like:

Relocate offset = 000000003db55000
* ELR(PC) = 000000000025bd78
* LR = 000000000025def4
* SP = 0000000039d4a6b0

* ESR_EL2 = 0000000040732550
EC[31:26] == 001100, Exception from an MCRR or MRRC access
IL[25] == 0, 16-bit instruction trapped

* DAIF = 00000000000003c0
D[9] == 1, DBG masked
A[8] == 1, ABORT masked
I[7] == 1, IRQ masked
F[6] == 1, FIQ masked

* SPSR_EL2 = 0000000080000349
D[9] == 1, DBG masked
A[8] == 1, ABORT masked
I[7] == 0, IRQ not masked
F[6] == 1, FIQ masked
M[4] == 0, Exception taken from AArch64
M[3:0] == 1001, EL2h

* SCTLR_EL2 = 0000000030c51835
I[12] == 1, Icaches enabled
C[2] == 1, Dcache enabled
M[0] == 1, MMU enabled

* VBAR_EL2 = 000000003dd55800
* HCR_EL2 = 000000000800003a
* TTBR0_EL2 = 000000003fff0000

x0 : 00000000ff300000 x1 : 0000000054808028
x2 : 000000000000002f x3 : 00000000ff160000
x4 : 0000000039d7fe80 x5 : 000000003de24ab0
......
x28: 0000000039d81ef0 x29: 0000000039d4a910

Change-Id: I828cafc961fdc3fcb2aa08916a7e36f690627313
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

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rockchip: vendor: export vendor_storage_test()

used for rockchip test driver.

Change-Id: Ib25a5ff4bae5fdf510dbbb89defabd8e3d0fcbfd
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

clk: rockchip: rk3399: support dual pll for vop

set the vop's parent just vpll and cpll,
set vop parent in dts node,the same as kernel setting.
i.e:
&vopb {
status = "okay";
assigned-clocks = <&cr

clk: rockchip: rk3399: support dual pll for vop

set the vop's parent just vpll and cpll,
set vop parent in dts node,the same as kernel setting.
i.e:
&vopb {
status = "okay";
assigned-clocks = <&cru DCLK_VOP0_DIV>;
assigned-clock-parents = <&cru PLL_VPLL>;
};
&vopl {
status = "okay";
assigned-clocks = <&cru DCLK_VOP1_DIV>;
assigned-clock-parents = <&cru PLL_CPLL>;
};

Change-Id: I07ab4e2837cf7fc0860e8b4d14adb8936f5cb27a
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

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rockchip: clk: px30: Add support to set and get armclk rate

Change-Id: I40948e5cedb781cad7129b02dfbf34fecb8689ca
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

rockchip: clk: px30: Change apll rate to 600MHz

The initial voltage may be too low for 816MHz and it is enough for
600MHz.

Change-Id: Ifa1438d8d3056c9fb8fb3e578a28c26682a27e46
Signed-off-by: Finley

rockchip: clk: px30: Change apll rate to 600MHz

The initial voltage may be too low for 816MHz and it is enough for
600MHz.

Change-Id: Ifa1438d8d3056c9fb8fb3e578a28c26682a27e46
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

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clk: rockchip: px30: implement soc_clk_dump

Change-Id: I8c5c4468ed6c6d1f4767a0a6ddaa2b47037fe8bc
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

clk: rockchip: px30: Add support for pmucru

Change-Id: I445ae2b2491d1709d2790412fcc07dccf56189d9
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

clk: rockchip: rv1108: support i2c clk get and set rate

Change-Id: Iff7e9191e66e0eff828b9ea51cb952ee7139457f
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: rk3308: implement soc_clk_dump

Change-Id: I6f0c3f56a878f491c4bb1deafd8e020e052e2287
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

clk: rockchip: px30: Add support to set rate for bus and peri clks

Change-Id: Ic122eaea3c1c63e6108eabf41ca1b46a30cc66ef
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>