1 /* 2 * (C) Copyright 2015 Google, Inc 3 * (C) 2017 Theobroma Systems Design und Consulting GmbH 4 * 5 * SPDX-License-Identifier: GPL-2.0 6 */ 7 8 #include <common.h> 9 #include <clk-uclass.h> 10 #include <dm.h> 11 #include <dt-structs.h> 12 #include <errno.h> 13 #include <mapmem.h> 14 #include <syscon.h> 15 #include <bitfield.h> 16 #include <asm/io.h> 17 #include <asm/arch/clock.h> 18 #include <asm/arch/cru_rk3399.h> 19 #include <asm/arch/hardware.h> 20 #include <dm/lists.h> 21 #include <dt-bindings/clock/rk3399-cru.h> 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 #if CONFIG_IS_ENABLED(OF_PLATDATA) 26 struct rk3399_clk_plat { 27 struct dtd_rockchip_rk3399_cru dtd; 28 }; 29 30 struct rk3399_pmuclk_plat { 31 struct dtd_rockchip_rk3399_pmucru dtd; 32 }; 33 #endif 34 35 struct pll_div { 36 u32 refdiv; 37 u32 fbdiv; 38 u32 postdiv1; 39 u32 postdiv2; 40 u32 frac; 41 u32 freq; 42 }; 43 44 #define RATE_TO_DIV(input_rate, output_rate) \ 45 ((input_rate) / (output_rate) - 1); 46 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) 47 48 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ 49 .refdiv = _refdiv,\ 50 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\ 51 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2, .freq = hz}; 52 53 #if !defined(CONFIG_SPL_BUILD) 54 static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1); 55 #endif 56 static const struct pll_div apll_1600_cfg = PLL_DIVISORS(1600*MHz, 3, 1, 1); 57 static const struct pll_div apll_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1); 58 59 static const struct pll_div *apll_cfgs[] = { 60 [APLL_1600_MHZ] = &apll_1600_cfg, 61 [APLL_600_MHZ] = &apll_600_cfg, 62 }; 63 64 enum { 65 /* PLL_CON0 */ 66 PLL_FBDIV_MASK = 0xfff, 67 PLL_FBDIV_SHIFT = 0, 68 69 /* PLL_CON1 */ 70 PLL_POSTDIV2_SHIFT = 12, 71 PLL_POSTDIV2_MASK = 0x7 << PLL_POSTDIV2_SHIFT, 72 PLL_POSTDIV1_SHIFT = 8, 73 PLL_POSTDIV1_MASK = 0x7 << PLL_POSTDIV1_SHIFT, 74 PLL_REFDIV_MASK = 0x3f, 75 PLL_REFDIV_SHIFT = 0, 76 77 /* PLL_CON2 */ 78 PLL_LOCK_STATUS_SHIFT = 31, 79 PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT, 80 PLL_FRACDIV_MASK = 0xffffff, 81 PLL_FRACDIV_SHIFT = 0, 82 83 /* PLL_CON3 */ 84 PLL_MODE_SHIFT = 8, 85 PLL_MODE_MASK = 3 << PLL_MODE_SHIFT, 86 PLL_MODE_SLOW = 0, 87 PLL_MODE_NORM, 88 PLL_MODE_DEEP, 89 PLL_DSMPD_SHIFT = 3, 90 PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT, 91 PLL_INTEGER_MODE = 1, 92 93 /* PMUCRU_CLKSEL_CON0 */ 94 PMU_PCLK_DIV_CON_MASK = 0x1f, 95 PMU_PCLK_DIV_CON_SHIFT = 0, 96 97 /* PMUCRU_CLKSEL_CON1 */ 98 SPI3_PLL_SEL_SHIFT = 7, 99 SPI3_PLL_SEL_MASK = 1 << SPI3_PLL_SEL_SHIFT, 100 SPI3_PLL_SEL_24M = 0, 101 SPI3_PLL_SEL_PPLL = 1, 102 SPI3_DIV_CON_SHIFT = 0x0, 103 SPI3_DIV_CON_MASK = 0x7f, 104 105 /* PMUCRU_CLKSEL_CON2 */ 106 I2C_DIV_CON_MASK = 0x7f, 107 CLK_I2C8_DIV_CON_SHIFT = 8, 108 CLK_I2C0_DIV_CON_SHIFT = 0, 109 110 /* PMUCRU_CLKSEL_CON3 */ 111 CLK_I2C4_DIV_CON_SHIFT = 0, 112 113 /* CLKSEL_CON0 / CLKSEL_CON2 */ 114 ACLKM_CORE_DIV_CON_MASK = 0x1f, 115 ACLKM_CORE_DIV_CON_SHIFT = 8, 116 CLK_CORE_PLL_SEL_MASK = 3, 117 CLK_CORE_PLL_SEL_SHIFT = 6, 118 CLK_CORE_PLL_SEL_ALPLL = 0x0, 119 CLK_CORE_PLL_SEL_ABPLL = 0x1, 120 CLK_CORE_PLL_SEL_DPLL = 0x10, 121 CLK_CORE_PLL_SEL_GPLL = 0x11, 122 CLK_CORE_DIV_MASK = 0x1f, 123 CLK_CORE_DIV_SHIFT = 0, 124 125 /* CLKSEL_CON1 / CLKSEL_CON3 */ 126 PCLK_DBG_DIV_MASK = 0x1f, 127 PCLK_DBG_DIV_SHIFT = 0x8, 128 ATCLK_CORE_DIV_MASK = 0x1f, 129 ATCLK_CORE_DIV_SHIFT = 0, 130 131 /* CLKSEL_CON14 */ 132 PCLK_PERIHP_DIV_CON_SHIFT = 12, 133 PCLK_PERIHP_DIV_CON_MASK = 0x7 << PCLK_PERIHP_DIV_CON_SHIFT, 134 HCLK_PERIHP_DIV_CON_SHIFT = 8, 135 HCLK_PERIHP_DIV_CON_MASK = 3 << HCLK_PERIHP_DIV_CON_SHIFT, 136 ACLK_PERIHP_PLL_SEL_SHIFT = 7, 137 ACLK_PERIHP_PLL_SEL_MASK = 1 << ACLK_PERIHP_PLL_SEL_SHIFT, 138 ACLK_PERIHP_PLL_SEL_CPLL = 0, 139 ACLK_PERIHP_PLL_SEL_GPLL = 1, 140 ACLK_PERIHP_DIV_CON_SHIFT = 0, 141 ACLK_PERIHP_DIV_CON_MASK = 0x1f, 142 143 /* CLKSEL_CON21 */ 144 ACLK_EMMC_PLL_SEL_SHIFT = 7, 145 ACLK_EMMC_PLL_SEL_MASK = 0x1 << ACLK_EMMC_PLL_SEL_SHIFT, 146 ACLK_EMMC_PLL_SEL_GPLL = 0x1, 147 ACLK_EMMC_DIV_CON_SHIFT = 0, 148 ACLK_EMMC_DIV_CON_MASK = 0x1f, 149 150 /* CLKSEL_CON22 */ 151 CLK_EMMC_PLL_SHIFT = 8, 152 CLK_EMMC_PLL_MASK = 0x7 << CLK_EMMC_PLL_SHIFT, 153 CLK_EMMC_PLL_SEL_GPLL = 0x1, 154 CLK_EMMC_PLL_SEL_24M = 0x5, 155 CLK_EMMC_DIV_CON_SHIFT = 0, 156 CLK_EMMC_DIV_CON_MASK = 0x7f << CLK_EMMC_DIV_CON_SHIFT, 157 158 /* CLKSEL_CON23 */ 159 PCLK_PERILP0_DIV_CON_SHIFT = 12, 160 PCLK_PERILP0_DIV_CON_MASK = 0x7 << PCLK_PERILP0_DIV_CON_SHIFT, 161 HCLK_PERILP0_DIV_CON_SHIFT = 8, 162 HCLK_PERILP0_DIV_CON_MASK = 3 << HCLK_PERILP0_DIV_CON_SHIFT, 163 ACLK_PERILP0_PLL_SEL_SHIFT = 7, 164 ACLK_PERILP0_PLL_SEL_MASK = 1 << ACLK_PERILP0_PLL_SEL_SHIFT, 165 ACLK_PERILP0_PLL_SEL_CPLL = 0, 166 ACLK_PERILP0_PLL_SEL_GPLL = 1, 167 ACLK_PERILP0_DIV_CON_SHIFT = 0, 168 ACLK_PERILP0_DIV_CON_MASK = 0x1f, 169 170 /* CLKSEL_CON25 */ 171 PCLK_PERILP1_DIV_CON_SHIFT = 8, 172 PCLK_PERILP1_DIV_CON_MASK = 0x7 << PCLK_PERILP1_DIV_CON_SHIFT, 173 HCLK_PERILP1_PLL_SEL_SHIFT = 7, 174 HCLK_PERILP1_PLL_SEL_MASK = 1 << HCLK_PERILP1_PLL_SEL_SHIFT, 175 HCLK_PERILP1_PLL_SEL_CPLL = 0, 176 HCLK_PERILP1_PLL_SEL_GPLL = 1, 177 HCLK_PERILP1_DIV_CON_SHIFT = 0, 178 HCLK_PERILP1_DIV_CON_MASK = 0x1f, 179 180 /* CLKSEL_CON26 */ 181 CLK_SARADC_DIV_CON_SHIFT = 8, 182 CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8), 183 CLK_SARADC_DIV_CON_WIDTH = 8, 184 185 /* CLKSEL_CON27 */ 186 CLK_TSADC_SEL_X24M = 0x0, 187 CLK_TSADC_SEL_SHIFT = 15, 188 CLK_TSADC_SEL_MASK = 1 << CLK_TSADC_SEL_SHIFT, 189 CLK_TSADC_DIV_CON_SHIFT = 0, 190 CLK_TSADC_DIV_CON_MASK = 0x3ff, 191 192 /* CLKSEL_CON47 & CLKSEL_CON48 */ 193 ACLK_VOP_PLL_SEL_SHIFT = 6, 194 ACLK_VOP_PLL_SEL_MASK = 0x3 << ACLK_VOP_PLL_SEL_SHIFT, 195 ACLK_VOP_PLL_SEL_CPLL = 0x1, 196 ACLK_VOP_PLL_SEL_GPLL = 0x2, 197 ACLK_VOP_DIV_CON_SHIFT = 0, 198 ACLK_VOP_DIV_CON_MASK = 0x1f << ACLK_VOP_DIV_CON_SHIFT, 199 200 /* CLKSEL_CON49 & CLKSEL_CON50 */ 201 DCLK_VOP_DCLK_SEL_SHIFT = 11, 202 DCLK_VOP_DCLK_SEL_MASK = 1 << DCLK_VOP_DCLK_SEL_SHIFT, 203 DCLK_VOP_DCLK_SEL_DIVOUT = 0, 204 DCLK_VOP_PLL_SEL_SHIFT = 8, 205 DCLK_VOP_PLL_SEL_MASK = 3 << DCLK_VOP_PLL_SEL_SHIFT, 206 DCLK_VOP_PLL_SEL_VPLL = 0, 207 DCLK_VOP_PLL_SEL_CPLL = 1, 208 DCLK_VOP_DIV_CON_MASK = 0xff, 209 DCLK_VOP_DIV_CON_SHIFT = 0, 210 211 /* CLKSEL_CON58 */ 212 CLK_SPI_PLL_SEL_WIDTH = 1, 213 CLK_SPI_PLL_SEL_MASK = ((1 < CLK_SPI_PLL_SEL_WIDTH) - 1), 214 CLK_SPI_PLL_SEL_CPLL = 0, 215 CLK_SPI_PLL_SEL_GPLL = 1, 216 CLK_SPI_PLL_DIV_CON_WIDTH = 7, 217 CLK_SPI_PLL_DIV_CON_MASK = ((1 << CLK_SPI_PLL_DIV_CON_WIDTH) - 1), 218 219 CLK_SPI5_PLL_DIV_CON_SHIFT = 8, 220 CLK_SPI5_PLL_SEL_SHIFT = 15, 221 222 /* CLKSEL_CON59 */ 223 CLK_SPI1_PLL_SEL_SHIFT = 15, 224 CLK_SPI1_PLL_DIV_CON_SHIFT = 8, 225 CLK_SPI0_PLL_SEL_SHIFT = 7, 226 CLK_SPI0_PLL_DIV_CON_SHIFT = 0, 227 228 /* CLKSEL_CON60 */ 229 CLK_SPI4_PLL_SEL_SHIFT = 15, 230 CLK_SPI4_PLL_DIV_CON_SHIFT = 8, 231 CLK_SPI2_PLL_SEL_SHIFT = 7, 232 CLK_SPI2_PLL_DIV_CON_SHIFT = 0, 233 234 /* CLKSEL_CON61 */ 235 CLK_I2C_PLL_SEL_MASK = 1, 236 CLK_I2C_PLL_SEL_CPLL = 0, 237 CLK_I2C_PLL_SEL_GPLL = 1, 238 CLK_I2C5_PLL_SEL_SHIFT = 15, 239 CLK_I2C5_DIV_CON_SHIFT = 8, 240 CLK_I2C1_PLL_SEL_SHIFT = 7, 241 CLK_I2C1_DIV_CON_SHIFT = 0, 242 243 /* CLKSEL_CON62 */ 244 CLK_I2C6_PLL_SEL_SHIFT = 15, 245 CLK_I2C6_DIV_CON_SHIFT = 8, 246 CLK_I2C2_PLL_SEL_SHIFT = 7, 247 CLK_I2C2_DIV_CON_SHIFT = 0, 248 249 /* CLKSEL_CON63 */ 250 CLK_I2C7_PLL_SEL_SHIFT = 15, 251 CLK_I2C7_DIV_CON_SHIFT = 8, 252 CLK_I2C3_PLL_SEL_SHIFT = 7, 253 CLK_I2C3_DIV_CON_SHIFT = 0, 254 255 /* CRU_SOFTRST_CON4 */ 256 RESETN_DDR0_REQ_SHIFT = 8, 257 RESETN_DDR0_REQ_MASK = 1 << RESETN_DDR0_REQ_SHIFT, 258 RESETN_DDRPHY0_REQ_SHIFT = 9, 259 RESETN_DDRPHY0_REQ_MASK = 1 << RESETN_DDRPHY0_REQ_SHIFT, 260 RESETN_DDR1_REQ_SHIFT = 12, 261 RESETN_DDR1_REQ_MASK = 1 << RESETN_DDR1_REQ_SHIFT, 262 RESETN_DDRPHY1_REQ_SHIFT = 13, 263 RESETN_DDRPHY1_REQ_MASK = 1 << RESETN_DDRPHY1_REQ_SHIFT, 264 }; 265 266 #define VCO_MAX_KHZ (3200 * (MHz / KHz)) 267 #define VCO_MIN_KHZ (800 * (MHz / KHz)) 268 #define OUTPUT_MAX_KHZ (3200 * (MHz / KHz)) 269 #define OUTPUT_MIN_KHZ (16 * (MHz / KHz)) 270 271 /* 272 * the div restructions of pll in integer mode, these are defined in 273 * * CRU_*PLL_CON0 or PMUCRU_*PLL_CON0 274 */ 275 #define PLL_DIV_MIN 16 276 #define PLL_DIV_MAX 3200 277 278 /* 279 * How to calculate the PLL(from TRM V0.3 Part 1 Page 63): 280 * Formulas also embedded within the Fractional PLL Verilog model: 281 * If DSMPD = 1 (DSM is disabled, "integer mode") 282 * FOUTVCO = FREF / REFDIV * FBDIV 283 * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2 284 * Where: 285 * FOUTVCO = Fractional PLL non-divided output frequency 286 * FOUTPOSTDIV = Fractional PLL divided output frequency 287 * (output of second post divider) 288 * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input) 289 * REFDIV = Fractional PLL input reference clock divider 290 * FBDIV = Integer value programmed into feedback divide 291 * 292 */ 293 294 static uint32_t rkclk_pll_get_rate(u32 *pll_con) 295 { 296 u32 refdiv, fbdiv, postdiv1, postdiv2; 297 u32 con; 298 299 con = readl(&pll_con[3]); 300 switch ((con & PLL_MODE_MASK) >> PLL_MODE_SHIFT) { 301 case PLL_MODE_SLOW: 302 return OSC_HZ; 303 case PLL_MODE_NORM: 304 /* normal mode */ 305 con = readl(&pll_con[0]); 306 fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT; 307 con = readl(&pll_con[1]); 308 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; 309 postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; 310 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; 311 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; 312 case PLL_MODE_DEEP: 313 default: 314 return 32768; 315 } 316 } 317 318 static void rkclk_set_pll(u32 *pll_con, const struct pll_div *div) 319 { 320 /* All 8 PLLs have same VCO and output frequency range restrictions. */ 321 u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv; 322 u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2; 323 324 debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, " 325 "postdiv2=%d, vco=%u khz, output=%u khz\n", 326 pll_con, div->fbdiv, div->refdiv, div->postdiv1, 327 div->postdiv2, vco_khz, output_khz); 328 assert(vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ && 329 output_khz >= OUTPUT_MIN_KHZ && output_khz <= OUTPUT_MAX_KHZ && 330 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX); 331 332 /* 333 * When power on or changing PLL setting, 334 * we must force PLL into slow mode to ensure output stable clock. 335 */ 336 rk_clrsetreg(&pll_con[3], PLL_MODE_MASK, 337 PLL_MODE_SLOW << PLL_MODE_SHIFT); 338 339 /* use integer mode */ 340 rk_clrsetreg(&pll_con[3], PLL_DSMPD_MASK, 341 PLL_INTEGER_MODE << PLL_DSMPD_SHIFT); 342 343 rk_clrsetreg(&pll_con[0], PLL_FBDIV_MASK, 344 div->fbdiv << PLL_FBDIV_SHIFT); 345 rk_clrsetreg(&pll_con[1], 346 PLL_POSTDIV2_MASK | PLL_POSTDIV1_MASK | 347 PLL_REFDIV_MASK | PLL_REFDIV_SHIFT, 348 (div->postdiv2 << PLL_POSTDIV2_SHIFT) | 349 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | 350 (div->refdiv << PLL_REFDIV_SHIFT)); 351 352 /* waiting for pll lock */ 353 while (!(readl(&pll_con[2]) & (1 << PLL_LOCK_STATUS_SHIFT))) 354 udelay(1); 355 356 /* pll enter normal mode */ 357 rk_clrsetreg(&pll_con[3], PLL_MODE_MASK, 358 PLL_MODE_NORM << PLL_MODE_SHIFT); 359 } 360 361 static ulong rk3399_pll_get_rate(struct rk3399_clk_priv *priv, 362 enum rk3399_pll_id pll_id) 363 { 364 struct rk3399_cru *cru = priv->cru; 365 u32 *pll_con; 366 367 switch (pll_id) { 368 case PLL_APLLL: 369 pll_con = &cru->apll_l_con[0]; 370 break; 371 case PLL_APLLB: 372 pll_con = &cru->apll_b_con[0]; 373 break; 374 case PLL_DPLL: 375 pll_con = &cru->dpll_con[0]; 376 break; 377 case PLL_CPLL: 378 pll_con = &cru->cpll_con[0]; 379 break; 380 case PLL_GPLL: 381 pll_con = &cru->gpll_con[0]; 382 break; 383 case PLL_NPLL: 384 pll_con = &cru->npll_con[0]; 385 break; 386 case PLL_VPLL: 387 pll_con = &cru->vpll_con[0]; 388 break; 389 default: 390 pll_con = &cru->vpll_con[0]; 391 break; 392 } 393 394 return rkclk_pll_get_rate(pll_con); 395 } 396 397 static int pll_para_config(u32 freq_hz, struct pll_div *div) 398 { 399 u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0; 400 u32 postdiv1, postdiv2 = 1; 401 u32 fref_khz; 402 u32 diff_khz, best_diff_khz; 403 const u32 max_refdiv = 63, max_fbdiv = 3200, min_fbdiv = 16; 404 const u32 max_postdiv1 = 7, max_postdiv2 = 7; 405 u32 vco_khz; 406 u32 freq_khz = freq_hz / KHz; 407 408 if (!freq_hz) { 409 printf("%s: the frequency can't be 0 Hz\n", __func__); 410 return -1; 411 } 412 413 postdiv1 = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz); 414 if (postdiv1 > max_postdiv1) { 415 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1); 416 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2); 417 } 418 419 vco_khz = freq_khz * postdiv1 * postdiv2; 420 421 if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ || 422 postdiv2 > max_postdiv2) { 423 printf("%s: Cannot find out a supported VCO" 424 " for Frequency (%uHz).\n", __func__, freq_hz); 425 return -1; 426 } 427 428 div->postdiv1 = postdiv1; 429 div->postdiv2 = postdiv2; 430 431 best_diff_khz = vco_khz; 432 for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) { 433 fref_khz = ref_khz / refdiv; 434 435 fbdiv = vco_khz / fref_khz; 436 if ((fbdiv >= max_fbdiv) || (fbdiv <= min_fbdiv)) 437 continue; 438 diff_khz = vco_khz - fbdiv * fref_khz; 439 if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) { 440 fbdiv++; 441 diff_khz = fref_khz - diff_khz; 442 } 443 444 if (diff_khz >= best_diff_khz) 445 continue; 446 447 best_diff_khz = diff_khz; 448 div->refdiv = refdiv; 449 div->fbdiv = fbdiv; 450 } 451 452 if (best_diff_khz > 4 * (MHz/KHz)) { 453 printf("%s: Failed to match output frequency %u, " 454 "difference is %u Hz,exceed 4MHZ\n", __func__, freq_hz, 455 best_diff_khz * KHz); 456 return -1; 457 } 458 return 0; 459 } 460 461 void rk3399_configure_cpu(struct rk3399_cru *cru, 462 enum apll_frequencies freq, 463 enum cpu_cluster cluster) 464 { 465 u32 aclkm_div; 466 u32 pclk_dbg_div; 467 u32 atclk_div, apll_hz; 468 int con_base, parent; 469 u32 *pll_con; 470 471 switch (cluster) { 472 case CPU_CLUSTER_LITTLE: 473 con_base = 0; 474 parent = CLK_CORE_PLL_SEL_ALPLL; 475 pll_con = &cru->apll_l_con[0]; 476 break; 477 case CPU_CLUSTER_BIG: 478 default: 479 con_base = 2; 480 parent = CLK_CORE_PLL_SEL_ABPLL; 481 pll_con = &cru->apll_b_con[0]; 482 break; 483 } 484 485 apll_hz = apll_cfgs[freq]->freq; 486 rkclk_set_pll(pll_con, apll_cfgs[freq]); 487 488 aclkm_div = apll_hz / ACLKM_CORE_HZ - 1; 489 assert((aclkm_div + 1) * ACLKM_CORE_HZ == apll_hz && 490 aclkm_div < 0x1f); 491 492 pclk_dbg_div = apll_hz / PCLK_DBG_HZ - 1; 493 assert((pclk_dbg_div + 1) * PCLK_DBG_HZ == apll_hz && 494 pclk_dbg_div < 0x1f); 495 496 atclk_div = apll_hz / ATCLK_CORE_HZ - 1; 497 assert((atclk_div + 1) * ATCLK_CORE_HZ == apll_hz && 498 atclk_div < 0x1f); 499 500 rk_clrsetreg(&cru->clksel_con[con_base], 501 ACLKM_CORE_DIV_CON_MASK | CLK_CORE_PLL_SEL_MASK | 502 CLK_CORE_DIV_MASK, 503 aclkm_div << ACLKM_CORE_DIV_CON_SHIFT | 504 parent << CLK_CORE_PLL_SEL_SHIFT | 505 0 << CLK_CORE_DIV_SHIFT); 506 507 rk_clrsetreg(&cru->clksel_con[con_base + 1], 508 PCLK_DBG_DIV_MASK | ATCLK_CORE_DIV_MASK, 509 pclk_dbg_div << PCLK_DBG_DIV_SHIFT | 510 atclk_div << ATCLK_CORE_DIV_SHIFT); 511 } 512 #define I2C_CLK_REG_MASK(bus) \ 513 (I2C_DIV_CON_MASK << \ 514 CLK_I2C ##bus## _DIV_CON_SHIFT | \ 515 CLK_I2C_PLL_SEL_MASK << \ 516 CLK_I2C ##bus## _PLL_SEL_SHIFT) 517 518 #define I2C_CLK_REG_VALUE(bus, clk_div) \ 519 ((clk_div - 1) << \ 520 CLK_I2C ##bus## _DIV_CON_SHIFT | \ 521 CLK_I2C_PLL_SEL_GPLL << \ 522 CLK_I2C ##bus## _PLL_SEL_SHIFT) 523 524 #define I2C_CLK_DIV_VALUE(con, bus) \ 525 (con >> CLK_I2C ##bus## _DIV_CON_SHIFT) & \ 526 I2C_DIV_CON_MASK; 527 528 #define I2C_PMUCLK_REG_MASK(bus) \ 529 (I2C_DIV_CON_MASK << \ 530 CLK_I2C ##bus## _DIV_CON_SHIFT) 531 532 #define I2C_PMUCLK_REG_VALUE(bus, clk_div) \ 533 ((clk_div - 1) << \ 534 CLK_I2C ##bus## _DIV_CON_SHIFT) 535 536 static ulong rk3399_i2c_get_clk(struct rk3399_cru *cru, ulong clk_id) 537 { 538 u32 div, con; 539 540 switch (clk_id) { 541 case SCLK_I2C1: 542 con = readl(&cru->clksel_con[61]); 543 div = I2C_CLK_DIV_VALUE(con, 1); 544 break; 545 case SCLK_I2C2: 546 con = readl(&cru->clksel_con[62]); 547 div = I2C_CLK_DIV_VALUE(con, 2); 548 break; 549 case SCLK_I2C3: 550 con = readl(&cru->clksel_con[63]); 551 div = I2C_CLK_DIV_VALUE(con, 3); 552 break; 553 case SCLK_I2C5: 554 con = readl(&cru->clksel_con[61]); 555 div = I2C_CLK_DIV_VALUE(con, 5); 556 break; 557 case SCLK_I2C6: 558 con = readl(&cru->clksel_con[62]); 559 div = I2C_CLK_DIV_VALUE(con, 6); 560 break; 561 case SCLK_I2C7: 562 con = readl(&cru->clksel_con[63]); 563 div = I2C_CLK_DIV_VALUE(con, 7); 564 break; 565 default: 566 printf("do not support this i2c bus\n"); 567 return -EINVAL; 568 } 569 570 return DIV_TO_RATE(GPLL_HZ, div); 571 } 572 573 static ulong rk3399_i2c_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz) 574 { 575 int src_clk_div; 576 577 /* i2c0,4,8 src clock from ppll, i2c1,2,3,5,6,7 src clock from gpll*/ 578 src_clk_div = GPLL_HZ / hz; 579 assert(src_clk_div - 1 <= 127); 580 581 switch (clk_id) { 582 case SCLK_I2C1: 583 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(1), 584 I2C_CLK_REG_VALUE(1, src_clk_div)); 585 break; 586 case SCLK_I2C2: 587 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(2), 588 I2C_CLK_REG_VALUE(2, src_clk_div)); 589 break; 590 case SCLK_I2C3: 591 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(3), 592 I2C_CLK_REG_VALUE(3, src_clk_div)); 593 break; 594 case SCLK_I2C5: 595 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(5), 596 I2C_CLK_REG_VALUE(5, src_clk_div)); 597 break; 598 case SCLK_I2C6: 599 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(6), 600 I2C_CLK_REG_VALUE(6, src_clk_div)); 601 break; 602 case SCLK_I2C7: 603 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(7), 604 I2C_CLK_REG_VALUE(7, src_clk_div)); 605 break; 606 default: 607 printf("do not support this i2c bus\n"); 608 return -EINVAL; 609 } 610 611 return rk3399_i2c_get_clk(cru, clk_id); 612 } 613 614 /* 615 * RK3399 SPI clocks have a common divider-width (7 bits) and a single bit 616 * to select either CPLL or GPLL as the clock-parent. The location within 617 * the enclosing CLKSEL_CON (i.e. div_shift and sel_shift) are variable. 618 */ 619 620 struct spi_clkreg { 621 uint8_t reg; /* CLKSEL_CON[reg] register in CRU */ 622 uint8_t div_shift; 623 uint8_t sel_shift; 624 }; 625 626 /* 627 * The entries are numbered relative to their offset from SCLK_SPI0. 628 * 629 * Note that SCLK_SPI3 (which is configured via PMUCRU and requires different 630 * logic is not supported). 631 */ 632 static const struct spi_clkreg spi_clkregs[] = { 633 [0] = { .reg = 59, 634 .div_shift = CLK_SPI0_PLL_DIV_CON_SHIFT, 635 .sel_shift = CLK_SPI0_PLL_SEL_SHIFT, }, 636 [1] = { .reg = 59, 637 .div_shift = CLK_SPI1_PLL_DIV_CON_SHIFT, 638 .sel_shift = CLK_SPI1_PLL_SEL_SHIFT, }, 639 [2] = { .reg = 60, 640 .div_shift = CLK_SPI2_PLL_DIV_CON_SHIFT, 641 .sel_shift = CLK_SPI2_PLL_SEL_SHIFT, }, 642 [3] = { .reg = 60, 643 .div_shift = CLK_SPI4_PLL_DIV_CON_SHIFT, 644 .sel_shift = CLK_SPI4_PLL_SEL_SHIFT, }, 645 [4] = { .reg = 58, 646 .div_shift = CLK_SPI5_PLL_DIV_CON_SHIFT, 647 .sel_shift = CLK_SPI5_PLL_SEL_SHIFT, }, 648 }; 649 650 static ulong rk3399_spi_get_clk(struct rk3399_cru *cru, ulong clk_id) 651 { 652 const struct spi_clkreg *spiclk = NULL; 653 u32 div, val; 654 655 switch (clk_id) { 656 case SCLK_SPI0 ... SCLK_SPI5: 657 spiclk = &spi_clkregs[clk_id - SCLK_SPI0]; 658 break; 659 660 default: 661 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id); 662 return -EINVAL; 663 } 664 665 val = readl(&cru->clksel_con[spiclk->reg]); 666 div = bitfield_extract(val, spiclk->div_shift, 667 CLK_SPI_PLL_DIV_CON_WIDTH); 668 669 return DIV_TO_RATE(GPLL_HZ, div); 670 } 671 672 static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz) 673 { 674 const struct spi_clkreg *spiclk = NULL; 675 int src_clk_div; 676 677 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1; 678 assert(src_clk_div < 128); 679 680 switch (clk_id) { 681 case SCLK_SPI1 ... SCLK_SPI5: 682 spiclk = &spi_clkregs[clk_id - SCLK_SPI0]; 683 break; 684 685 default: 686 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id); 687 return -EINVAL; 688 } 689 690 rk_clrsetreg(&cru->clksel_con[spiclk->reg], 691 ((CLK_SPI_PLL_DIV_CON_MASK << spiclk->div_shift) | 692 (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift)), 693 ((src_clk_div << spiclk->div_shift) | 694 (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift))); 695 696 return rk3399_spi_get_clk(cru, clk_id); 697 } 698 699 #define RK3399_LIMIT_PLL_ACLK_VOP (400 * 1000000) 700 701 static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz) 702 { 703 struct pll_div vpll_config = {0}, cpll_config = {0}; 704 int aclk_vop = RK3399_LIMIT_PLL_ACLK_VOP; 705 void *aclkreg_addr, *dclkreg_addr; 706 u32 div = 1; 707 708 switch (clk_id) { 709 case DCLK_VOP0: 710 aclkreg_addr = &cru->clksel_con[47]; 711 dclkreg_addr = &cru->clksel_con[49]; 712 break; 713 case DCLK_VOP1: 714 aclkreg_addr = &cru->clksel_con[48]; 715 dclkreg_addr = &cru->clksel_con[50]; 716 break; 717 default: 718 return -EINVAL; 719 } 720 /* vop aclk source clk: cpll */ 721 div = GPLL_HZ / aclk_vop; 722 assert(div - 1 <= 31); 723 724 rk_clrsetreg(aclkreg_addr, 725 ACLK_VOP_PLL_SEL_MASK | ACLK_VOP_DIV_CON_MASK, 726 ACLK_VOP_PLL_SEL_GPLL << ACLK_VOP_PLL_SEL_SHIFT | 727 (div - 1) << ACLK_VOP_DIV_CON_SHIFT); 728 729 if (readl(dclkreg_addr) & DCLK_VOP_PLL_SEL_MASK) { 730 if (pll_para_config(hz, &cpll_config)) 731 return -1; 732 rkclk_set_pll(&cru->cpll_con[0], &cpll_config); 733 } else { 734 if (pll_para_config(hz, &vpll_config)) 735 return -1; 736 rkclk_set_pll(&cru->vpll_con[0], &vpll_config); 737 } 738 739 rk_clrsetreg(dclkreg_addr, 740 DCLK_VOP_DCLK_SEL_MASK | DCLK_VOP_DIV_CON_MASK, 741 DCLK_VOP_DCLK_SEL_DIVOUT << DCLK_VOP_DCLK_SEL_SHIFT | 742 (1 - 1) << DCLK_VOP_DIV_CON_SHIFT); 743 744 return hz; 745 } 746 747 static ulong rk3399_mmc_get_clk(struct rk3399_cru *cru, uint clk_id) 748 { 749 u32 div, con; 750 751 switch (clk_id) { 752 case HCLK_SDMMC: 753 case SCLK_SDMMC: 754 con = readl(&cru->clksel_con[16]); 755 /* dwmmc controller have internal div 2 */ 756 div = 2; 757 break; 758 case SCLK_EMMC: 759 con = readl(&cru->clksel_con[21]); 760 div = 1; 761 break; 762 default: 763 return -EINVAL; 764 } 765 766 div *= (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT; 767 if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT 768 == CLK_EMMC_PLL_SEL_24M) 769 return DIV_TO_RATE(OSC_HZ, div); 770 else 771 return DIV_TO_RATE(GPLL_HZ, div); 772 } 773 774 static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru, 775 ulong clk_id, ulong set_rate) 776 { 777 int src_clk_div; 778 int aclk_emmc = 198*MHz; 779 780 switch (clk_id) { 781 case HCLK_SDMMC: 782 case SCLK_SDMMC: 783 /* Select clk_sdmmc source from GPLL by default */ 784 /* mmc clock defaulg div 2 internal, provide double in cru */ 785 src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate); 786 787 if (src_clk_div > 128) { 788 /* use 24MHz source for 400KHz clock */ 789 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate); 790 assert(src_clk_div - 1 < 128); 791 rk_clrsetreg(&cru->clksel_con[16], 792 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, 793 CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT | 794 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); 795 } else { 796 rk_clrsetreg(&cru->clksel_con[16], 797 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, 798 CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT | 799 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); 800 } 801 break; 802 case SCLK_EMMC: 803 /* Select aclk_emmc source from GPLL */ 804 src_clk_div = DIV_ROUND_UP(GPLL_HZ , aclk_emmc); 805 assert(src_clk_div - 1 < 32); 806 807 rk_clrsetreg(&cru->clksel_con[21], 808 ACLK_EMMC_PLL_SEL_MASK | ACLK_EMMC_DIV_CON_MASK, 809 ACLK_EMMC_PLL_SEL_GPLL << ACLK_EMMC_PLL_SEL_SHIFT | 810 (src_clk_div - 1) << ACLK_EMMC_DIV_CON_SHIFT); 811 812 /* Select clk_emmc source from GPLL too */ 813 src_clk_div = DIV_ROUND_UP(GPLL_HZ, set_rate); 814 assert(src_clk_div - 1 < 128); 815 816 rk_clrsetreg(&cru->clksel_con[22], 817 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, 818 CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT | 819 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); 820 break; 821 default: 822 return -EINVAL; 823 } 824 return rk3399_mmc_get_clk(cru, clk_id); 825 } 826 827 static ulong rk3399_gmac_set_clk(struct rk3399_cru *cru, ulong rate) 828 { 829 ulong ret; 830 831 /* 832 * The RGMII CLK can be derived either from an external "clkin" 833 * or can be generated from internally by a divider from SCLK_MAC. 834 */ 835 if (readl(&cru->clksel_con[19]) & BIT(4)) { 836 /* An external clock will always generate the right rate... */ 837 ret = rate; 838 } else { 839 /* 840 * No platform uses an internal clock to date. 841 * Implement this once it becomes necessary and print an error 842 * if someone tries to use it (while it remains unimplemented). 843 */ 844 pr_err("%s: internal clock is UNIMPLEMENTED\n", __func__); 845 ret = 0; 846 } 847 848 return ret; 849 } 850 851 #define PMUSGRF_DDR_RGN_CON16 0xff330040 852 static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru, 853 ulong set_rate) 854 { 855 struct pll_div dpll_cfg; 856 857 /* IC ECO bug, need to set this register */ 858 writel(0xc000c000, PMUSGRF_DDR_RGN_CON16); 859 860 /* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */ 861 switch (set_rate) { 862 case 200*MHz: 863 dpll_cfg = (struct pll_div) 864 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 6, .postdiv2 = 1}; 865 break; 866 case 300*MHz: 867 dpll_cfg = (struct pll_div) 868 {.refdiv = 2, .fbdiv = 100, .postdiv1 = 4, .postdiv2 = 1}; 869 break; 870 case 666*MHz: 871 dpll_cfg = (struct pll_div) 872 {.refdiv = 2, .fbdiv = 111, .postdiv1 = 2, .postdiv2 = 1}; 873 break; 874 case 800*MHz: 875 dpll_cfg = (struct pll_div) 876 {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1}; 877 break; 878 case 933*MHz: 879 dpll_cfg = (struct pll_div) 880 {.refdiv = 1, .fbdiv = 116, .postdiv1 = 3, .postdiv2 = 1}; 881 break; 882 default: 883 pr_err("Unsupported SDRAM frequency!,%ld\n", set_rate); 884 } 885 rkclk_set_pll(&cru->dpll_con[0], &dpll_cfg); 886 887 return set_rate; 888 } 889 890 static ulong rk3399_saradc_get_clk(struct rk3399_cru *cru) 891 { 892 u32 div, val; 893 894 val = readl(&cru->clksel_con[26]); 895 div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT, 896 CLK_SARADC_DIV_CON_WIDTH); 897 898 return DIV_TO_RATE(OSC_HZ, div); 899 } 900 901 static ulong rk3399_saradc_set_clk(struct rk3399_cru *cru, uint hz) 902 { 903 int src_clk_div; 904 905 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; 906 assert(src_clk_div <= 255); 907 908 rk_clrsetreg(&cru->clksel_con[26], 909 CLK_SARADC_DIV_CON_MASK, 910 src_clk_div << CLK_SARADC_DIV_CON_SHIFT); 911 912 return rk3399_saradc_get_clk(cru); 913 } 914 915 static ulong rk3399_clk_get_rate(struct clk *clk) 916 { 917 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev); 918 ulong rate = 0; 919 920 switch (clk->id) { 921 case PLL_APLLL: 922 case PLL_APLLB: 923 case PLL_DPLL: 924 case PLL_CPLL: 925 case PLL_GPLL: 926 case PLL_NPLL: 927 case PLL_VPLL: 928 rate = rk3399_pll_get_rate(priv, clk->id - 1); 929 break; 930 case HCLK_SDMMC: 931 case SCLK_SDMMC: 932 case SCLK_EMMC: 933 rate = rk3399_mmc_get_clk(priv->cru, clk->id); 934 break; 935 case SCLK_I2C1: 936 case SCLK_I2C2: 937 case SCLK_I2C3: 938 case SCLK_I2C5: 939 case SCLK_I2C6: 940 case SCLK_I2C7: 941 rate = rk3399_i2c_get_clk(priv->cru, clk->id); 942 break; 943 case SCLK_SPI0...SCLK_SPI5: 944 rate = rk3399_spi_get_clk(priv->cru, clk->id); 945 break; 946 case SCLK_UART0: 947 case SCLK_UART1: 948 case SCLK_UART2: 949 case SCLK_UART3: 950 return 24000000; 951 break; 952 case PCLK_HDMI_CTRL: 953 break; 954 case DCLK_VOP0: 955 case DCLK_VOP1: 956 break; 957 case PCLK_EFUSE1024NS: 958 break; 959 case SCLK_SARADC: 960 rate = rk3399_saradc_get_clk(priv->cru); 961 break; 962 default: 963 return -ENOENT; 964 } 965 966 return rate; 967 } 968 969 static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate) 970 { 971 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev); 972 ulong ret = 0; 973 974 switch (clk->id) { 975 case 0 ... 63: 976 return 0; 977 978 case ACLK_PERIHP: 979 case HCLK_PERIHP: 980 case PCLK_PERIHP: 981 return 0; 982 983 case ACLK_PERILP0: 984 case HCLK_PERILP0: 985 case PCLK_PERILP0: 986 return 0; 987 988 case ACLK_CCI: 989 return 0; 990 991 case HCLK_PERILP1: 992 case PCLK_PERILP1: 993 return 0; 994 995 case HCLK_SDMMC: 996 case SCLK_SDMMC: 997 case SCLK_EMMC: 998 ret = rk3399_mmc_set_clk(priv->cru, clk->id, rate); 999 break; 1000 case SCLK_MAC: 1001 ret = rk3399_gmac_set_clk(priv->cru, rate); 1002 break; 1003 case SCLK_I2C1: 1004 case SCLK_I2C2: 1005 case SCLK_I2C3: 1006 case SCLK_I2C5: 1007 case SCLK_I2C6: 1008 case SCLK_I2C7: 1009 ret = rk3399_i2c_set_clk(priv->cru, clk->id, rate); 1010 break; 1011 case SCLK_SPI0...SCLK_SPI5: 1012 ret = rk3399_spi_set_clk(priv->cru, clk->id, rate); 1013 break; 1014 case PCLK_HDMI_CTRL: 1015 case PCLK_VIO_GRF: 1016 /* the PCLK gates for video are enabled by default */ 1017 break; 1018 case DCLK_VOP0: 1019 case DCLK_VOP1: 1020 ret = rk3399_vop_set_clk(priv->cru, clk->id, rate); 1021 break; 1022 case SCLK_DDRCLK: 1023 ret = rk3399_ddr_set_clk(priv->cru, rate); 1024 break; 1025 case PCLK_EFUSE1024NS: 1026 break; 1027 case SCLK_SARADC: 1028 ret = rk3399_saradc_set_clk(priv->cru, rate); 1029 break; 1030 default: 1031 return -ENOENT; 1032 } 1033 1034 return ret; 1035 } 1036 1037 static int __maybe_unused rk3399_gmac_set_parent(struct clk *clk, struct clk *parent) 1038 { 1039 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev); 1040 const char *clock_output_name; 1041 int ret; 1042 1043 /* 1044 * If the requested parent is in the same clock-controller and 1045 * the id is SCLK_MAC ("clk_gmac"), switch to the internal clock. 1046 */ 1047 if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC)) { 1048 debug("%s: switching RGMII to SCLK_MAC\n", __func__); 1049 rk_clrreg(&priv->cru->clksel_con[19], BIT(4)); 1050 return 0; 1051 } 1052 1053 /* 1054 * Otherwise, we need to check the clock-output-names of the 1055 * requested parent to see if the requested id is "clkin_gmac". 1056 */ 1057 ret = dev_read_string_index(parent->dev, "clock-output-names", 1058 parent->id, &clock_output_name); 1059 if (ret < 0) 1060 return -ENODATA; 1061 1062 /* If this is "clkin_gmac", switch to the external clock input */ 1063 if (!strcmp(clock_output_name, "clkin_gmac")) { 1064 debug("%s: switching RGMII to CLKIN\n", __func__); 1065 rk_setreg(&priv->cru->clksel_con[19], BIT(4)); 1066 return 0; 1067 } 1068 1069 return -EINVAL; 1070 } 1071 1072 static int __maybe_unused rk3399_dclk_vop_set_parent(struct clk *clk, 1073 struct clk *parent) 1074 { 1075 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev); 1076 void *dclkreg_addr; 1077 1078 switch (clk->id) { 1079 case DCLK_VOP0_DIV: 1080 dclkreg_addr = &priv->cru->clksel_con[49]; 1081 break; 1082 case DCLK_VOP1_DIV: 1083 dclkreg_addr = &priv->cru->clksel_con[50]; 1084 break; 1085 default: 1086 return -EINVAL; 1087 } 1088 if (parent->id == PLL_CPLL) { 1089 rk_clrsetreg(dclkreg_addr, DCLK_VOP_PLL_SEL_MASK, 1090 DCLK_VOP_PLL_SEL_CPLL << DCLK_VOP_PLL_SEL_SHIFT); 1091 } else { 1092 rk_clrsetreg(dclkreg_addr, DCLK_VOP_PLL_SEL_MASK, 1093 DCLK_VOP_PLL_SEL_VPLL << DCLK_VOP_PLL_SEL_SHIFT); 1094 } 1095 1096 return 0; 1097 } 1098 1099 static int __maybe_unused rk3399_clk_set_parent(struct clk *clk, struct clk *parent) 1100 { 1101 switch (clk->id) { 1102 case SCLK_RMII_SRC: 1103 return rk3399_gmac_set_parent(clk, parent); 1104 case DCLK_VOP0_DIV: 1105 case DCLK_VOP1_DIV: 1106 return rk3399_dclk_vop_set_parent(clk, parent); 1107 } 1108 1109 debug("%s: unsupported clk %ld\n", __func__, clk->id); 1110 return -ENOENT; 1111 } 1112 1113 static int rk3399_clk_enable(struct clk *clk) 1114 { 1115 switch (clk->id) { 1116 case HCLK_HOST0: 1117 case HCLK_HOST0_ARB: 1118 case SCLK_USBPHY0_480M_SRC: 1119 case HCLK_HOST1: 1120 case HCLK_HOST1_ARB: 1121 case SCLK_USBPHY1_480M_SRC: 1122 return 0; 1123 } 1124 1125 debug("%s: unsupported clk %ld\n", __func__, clk->id); 1126 return -ENOENT; 1127 } 1128 1129 static struct clk_ops rk3399_clk_ops = { 1130 .get_rate = rk3399_clk_get_rate, 1131 .set_rate = rk3399_clk_set_rate, 1132 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) 1133 .set_parent = rk3399_clk_set_parent, 1134 #endif 1135 .enable = rk3399_clk_enable, 1136 }; 1137 1138 static void rkclk_init(struct rk3399_cru *cru) 1139 { 1140 u32 aclk_div; 1141 u32 hclk_div; 1142 u32 pclk_div; 1143 1144 rk3399_configure_cpu(cru, APLL_600_MHZ, CPU_CLUSTER_LITTLE); 1145 1146 /* 1147 * some cru registers changed by bootrom, we'd better reset them to 1148 * reset/default values described in TRM to avoid confusion in kernel. 1149 * Please consider these three lines as a fix of bootrom bug. 1150 */ 1151 rk_clrsetreg(&cru->clksel_con[12], 0xffff, 0x4101); 1152 rk_clrsetreg(&cru->clksel_con[19], 0xffff, 0x033f); 1153 rk_clrsetreg(&cru->clksel_con[56], 0x0003, 0x0003); 1154 1155 /* configure perihp aclk, hclk, pclk */ 1156 aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1; 1157 assert((aclk_div + 1) * PERIHP_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); 1158 1159 hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1; 1160 assert((hclk_div + 1) * PERIHP_HCLK_HZ == 1161 PERIHP_ACLK_HZ && (hclk_div <= 0x3)); 1162 1163 pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1; 1164 assert((pclk_div + 1) * PERIHP_PCLK_HZ == 1165 PERIHP_ACLK_HZ && (pclk_div <= 0x7)); 1166 1167 rk_clrsetreg(&cru->clksel_con[14], 1168 PCLK_PERIHP_DIV_CON_MASK | HCLK_PERIHP_DIV_CON_MASK | 1169 ACLK_PERIHP_PLL_SEL_MASK | ACLK_PERIHP_DIV_CON_MASK, 1170 pclk_div << PCLK_PERIHP_DIV_CON_SHIFT | 1171 hclk_div << HCLK_PERIHP_DIV_CON_SHIFT | 1172 ACLK_PERIHP_PLL_SEL_GPLL << ACLK_PERIHP_PLL_SEL_SHIFT | 1173 aclk_div << ACLK_PERIHP_DIV_CON_SHIFT); 1174 1175 /* configure perilp0 aclk, hclk, pclk */ 1176 aclk_div = GPLL_HZ / PERILP0_ACLK_HZ - 1; 1177 assert((aclk_div + 1) * PERILP0_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); 1178 1179 hclk_div = PERILP0_ACLK_HZ / PERILP0_HCLK_HZ - 1; 1180 assert((hclk_div + 1) * PERILP0_HCLK_HZ == 1181 PERILP0_ACLK_HZ && (hclk_div <= 0x3)); 1182 1183 pclk_div = PERILP0_ACLK_HZ / PERILP0_PCLK_HZ - 1; 1184 assert((pclk_div + 1) * PERILP0_PCLK_HZ == 1185 PERILP0_ACLK_HZ && (pclk_div <= 0x7)); 1186 1187 rk_clrsetreg(&cru->clksel_con[23], 1188 PCLK_PERILP0_DIV_CON_MASK | HCLK_PERILP0_DIV_CON_MASK | 1189 ACLK_PERILP0_PLL_SEL_MASK | ACLK_PERILP0_DIV_CON_MASK, 1190 pclk_div << PCLK_PERILP0_DIV_CON_SHIFT | 1191 hclk_div << HCLK_PERILP0_DIV_CON_SHIFT | 1192 ACLK_PERILP0_PLL_SEL_GPLL << ACLK_PERILP0_PLL_SEL_SHIFT | 1193 aclk_div << ACLK_PERILP0_DIV_CON_SHIFT); 1194 1195 /* perilp1 hclk select gpll as source */ 1196 hclk_div = GPLL_HZ / PERILP1_HCLK_HZ - 1; 1197 assert((hclk_div + 1) * PERILP1_HCLK_HZ == 1198 GPLL_HZ && (hclk_div <= 0x1f)); 1199 1200 pclk_div = PERILP1_HCLK_HZ / PERILP1_PCLK_HZ - 1; 1201 assert((pclk_div + 1) * PERILP1_PCLK_HZ == 1202 PERILP1_HCLK_HZ && (pclk_div <= 0x7)); 1203 1204 rk_clrsetreg(&cru->clksel_con[25], 1205 PCLK_PERILP1_DIV_CON_MASK | HCLK_PERILP1_DIV_CON_MASK | 1206 HCLK_PERILP1_PLL_SEL_MASK, 1207 pclk_div << PCLK_PERILP1_DIV_CON_SHIFT | 1208 hclk_div << HCLK_PERILP1_DIV_CON_SHIFT | 1209 HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT); 1210 } 1211 1212 static int rk3399_clk_probe(struct udevice *dev) 1213 { 1214 struct rk3399_clk_priv *priv = dev_get_priv(dev); 1215 1216 #if CONFIG_IS_ENABLED(OF_PLATDATA) 1217 struct rk3399_clk_plat *plat = dev_get_platdata(dev); 1218 1219 priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); 1220 #endif 1221 rkclk_init(priv->cru); 1222 return 0; 1223 } 1224 1225 static int rk3399_clk_ofdata_to_platdata(struct udevice *dev) 1226 { 1227 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 1228 struct rk3399_clk_priv *priv = dev_get_priv(dev); 1229 1230 priv->cru = dev_read_addr_ptr(dev); 1231 #endif 1232 return 0; 1233 } 1234 1235 static int rk3399_clk_bind(struct udevice *dev) 1236 { 1237 int ret; 1238 struct udevice *sys_child, *sf_child; 1239 struct sysreset_reg *priv; 1240 struct softreset_reg *sf_priv; 1241 1242 /* The reset driver does not have a device node, so bind it here */ 1243 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", 1244 &sys_child); 1245 if (ret) { 1246 debug("Warning: No sysreset driver: ret=%d\n", ret); 1247 } else { 1248 priv = malloc(sizeof(struct sysreset_reg)); 1249 priv->glb_srst_fst_value = offsetof(struct rk3399_cru, 1250 glb_srst_fst_value); 1251 priv->glb_srst_snd_value = offsetof(struct rk3399_cru, 1252 glb_srst_snd_value); 1253 sys_child->priv = priv; 1254 } 1255 1256 ret = device_bind_driver_to_node(dev, "rockchip_reset", "reset", 1257 dev_ofnode(dev), &sf_child); 1258 if (ret) { 1259 debug("Warning: No rockchip reset driver: ret=%d\n", ret); 1260 } else { 1261 sf_priv = malloc(sizeof(struct softreset_reg)); 1262 sf_priv->sf_reset_offset = offsetof(struct rk3399_cru, 1263 softrst_con[0]); 1264 sf_priv->sf_reset_num = 21; 1265 sf_child->priv = sf_priv; 1266 } 1267 1268 return 0; 1269 } 1270 1271 static const struct udevice_id rk3399_clk_ids[] = { 1272 { .compatible = "rockchip,rk3399-cru" }, 1273 { } 1274 }; 1275 1276 U_BOOT_DRIVER(clk_rk3399) = { 1277 .name = "rockchip_rk3399_cru", 1278 .id = UCLASS_CLK, 1279 .of_match = rk3399_clk_ids, 1280 .priv_auto_alloc_size = sizeof(struct rk3399_clk_priv), 1281 .ofdata_to_platdata = rk3399_clk_ofdata_to_platdata, 1282 .ops = &rk3399_clk_ops, 1283 .bind = rk3399_clk_bind, 1284 .probe = rk3399_clk_probe, 1285 #if CONFIG_IS_ENABLED(OF_PLATDATA) 1286 .platdata_auto_alloc_size = sizeof(struct rk3399_clk_plat), 1287 #endif 1288 }; 1289 1290 static ulong rk3399_i2c_get_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id) 1291 { 1292 u32 div, con; 1293 1294 switch (clk_id) { 1295 case SCLK_I2C0_PMU: 1296 con = readl(&pmucru->pmucru_clksel[2]); 1297 div = I2C_CLK_DIV_VALUE(con, 0); 1298 break; 1299 case SCLK_I2C4_PMU: 1300 con = readl(&pmucru->pmucru_clksel[3]); 1301 div = I2C_CLK_DIV_VALUE(con, 4); 1302 break; 1303 case SCLK_I2C8_PMU: 1304 con = readl(&pmucru->pmucru_clksel[2]); 1305 div = I2C_CLK_DIV_VALUE(con, 8); 1306 break; 1307 default: 1308 printf("do not support this i2c bus\n"); 1309 return -EINVAL; 1310 } 1311 1312 return DIV_TO_RATE(PPLL_HZ, div); 1313 } 1314 1315 static ulong rk3399_i2c_set_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id, 1316 uint hz) 1317 { 1318 int src_clk_div; 1319 1320 src_clk_div = PPLL_HZ / hz; 1321 assert(src_clk_div - 1 < 127); 1322 1323 switch (clk_id) { 1324 case SCLK_I2C0_PMU: 1325 rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(0), 1326 I2C_PMUCLK_REG_VALUE(0, src_clk_div)); 1327 break; 1328 case SCLK_I2C4_PMU: 1329 rk_clrsetreg(&pmucru->pmucru_clksel[3], I2C_PMUCLK_REG_MASK(4), 1330 I2C_PMUCLK_REG_VALUE(4, src_clk_div)); 1331 break; 1332 case SCLK_I2C8_PMU: 1333 rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(8), 1334 I2C_PMUCLK_REG_VALUE(8, src_clk_div)); 1335 break; 1336 default: 1337 printf("do not support this i2c bus\n"); 1338 return -EINVAL; 1339 } 1340 1341 return DIV_TO_RATE(PPLL_HZ, src_clk_div); 1342 } 1343 1344 static ulong rk3399_pwm_get_clk(struct rk3399_pmucru *pmucru) 1345 { 1346 u32 div, con; 1347 1348 /* PWM closk rate is same as pclk_pmu */ 1349 con = readl(&pmucru->pmucru_clksel[0]); 1350 div = con & PMU_PCLK_DIV_CON_MASK; 1351 1352 return DIV_TO_RATE(PPLL_HZ, div); 1353 } 1354 1355 static ulong rk3399_pmuclk_get_rate(struct clk *clk) 1356 { 1357 struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev); 1358 ulong rate = 0; 1359 1360 switch (clk->id) { 1361 case PCLK_RKPWM_PMU: 1362 rate = rk3399_pwm_get_clk(priv->pmucru); 1363 break; 1364 case SCLK_I2C0_PMU: 1365 case SCLK_I2C4_PMU: 1366 case SCLK_I2C8_PMU: 1367 rate = rk3399_i2c_get_pmuclk(priv->pmucru, clk->id); 1368 break; 1369 case SCLK_UART4_PMU: 1370 rate = 24000000; 1371 break; 1372 default: 1373 return -ENOENT; 1374 } 1375 1376 return rate; 1377 } 1378 1379 static ulong rk3399_pmuclk_set_rate(struct clk *clk, ulong rate) 1380 { 1381 struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev); 1382 ulong ret = 0; 1383 1384 switch (clk->id) { 1385 case SCLK_I2C0_PMU: 1386 case SCLK_I2C4_PMU: 1387 case SCLK_I2C8_PMU: 1388 ret = rk3399_i2c_set_pmuclk(priv->pmucru, clk->id, rate); 1389 break; 1390 default: 1391 return -ENOENT; 1392 } 1393 1394 return ret; 1395 } 1396 1397 static struct clk_ops rk3399_pmuclk_ops = { 1398 .get_rate = rk3399_pmuclk_get_rate, 1399 .set_rate = rk3399_pmuclk_set_rate, 1400 }; 1401 1402 #ifndef CONFIG_SPL_BUILD 1403 static void pmuclk_init(struct rk3399_pmucru *pmucru) 1404 { 1405 u32 pclk_div; 1406 1407 /* configure pmu pll(ppll) */ 1408 rkclk_set_pll(&pmucru->ppll_con[0], &ppll_init_cfg); 1409 1410 /* configure pmu pclk */ 1411 pclk_div = PPLL_HZ / PMU_PCLK_HZ - 1; 1412 assert((pclk_div + 1) * PMU_PCLK_HZ == PPLL_HZ && pclk_div <= 0x1f); 1413 rk_clrsetreg(&pmucru->pmucru_clksel[0], 1414 PMU_PCLK_DIV_CON_MASK, 1415 pclk_div << PMU_PCLK_DIV_CON_SHIFT); 1416 } 1417 #endif 1418 1419 static int rk3399_pmuclk_probe(struct udevice *dev) 1420 { 1421 #if CONFIG_IS_ENABLED(OF_PLATDATA) || !defined(CONFIG_SPL_BUILD) 1422 struct rk3399_pmuclk_priv *priv = dev_get_priv(dev); 1423 #endif 1424 1425 #if CONFIG_IS_ENABLED(OF_PLATDATA) 1426 struct rk3399_pmuclk_plat *plat = dev_get_platdata(dev); 1427 1428 priv->pmucru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); 1429 #endif 1430 1431 #ifndef CONFIG_SPL_BUILD 1432 pmuclk_init(priv->pmucru); 1433 #endif 1434 return 0; 1435 } 1436 1437 static int rk3399_pmuclk_ofdata_to_platdata(struct udevice *dev) 1438 { 1439 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 1440 struct rk3399_pmuclk_priv *priv = dev_get_priv(dev); 1441 1442 priv->pmucru = dev_read_addr_ptr(dev); 1443 #endif 1444 return 0; 1445 } 1446 1447 static int rk3399_pmuclk_bind(struct udevice *dev) 1448 { 1449 int ret = 0; 1450 struct udevice *sf_child; 1451 struct softreset_reg *sf_priv; 1452 1453 ret = device_bind_driver_to_node(dev, "rockchip_reset", 1454 "reset", dev_ofnode(dev), 1455 &sf_child); 1456 if (ret) { 1457 debug("Warning: No rockchip reset driver: ret=%d\n", ret); 1458 } else { 1459 sf_priv = malloc(sizeof(struct softreset_reg)); 1460 sf_priv->sf_reset_offset = offsetof(struct rk3399_pmucru, 1461 pmucru_softrst_con[0]); 1462 sf_priv->sf_reset_num = 2; 1463 sf_child->priv = sf_priv; 1464 } 1465 1466 return 0; 1467 } 1468 1469 static const struct udevice_id rk3399_pmuclk_ids[] = { 1470 { .compatible = "rockchip,rk3399-pmucru" }, 1471 { } 1472 }; 1473 1474 U_BOOT_DRIVER(rockchip_rk3399_pmuclk) = { 1475 .name = "rockchip_rk3399_pmucru", 1476 .id = UCLASS_CLK, 1477 .of_match = rk3399_pmuclk_ids, 1478 .priv_auto_alloc_size = sizeof(struct rk3399_pmuclk_priv), 1479 .ofdata_to_platdata = rk3399_pmuclk_ofdata_to_platdata, 1480 .ops = &rk3399_pmuclk_ops, 1481 .probe = rk3399_pmuclk_probe, 1482 .bind = rk3399_pmuclk_bind, 1483 #if CONFIG_IS_ENABLED(OF_PLATDATA) 1484 .platdata_auto_alloc_size = sizeof(struct rk3399_pmuclk_plat), 1485 #endif 1486 }; 1487