1if ARCH_ROCKCHIP 2 3config ROCKCHIP_PX30 4 bool "Support Rockchip PX30" 5 select ARM64 6 select GICV2 7 select ARM_SMCCC 8 select SUPPORT_SPL 9 select SUPPORT_TPL 10 select SPL 11 select TPL 12 select TPL_TINY_FRAMEWORK if TPL 13 14 imply SPL_SERIAL_SUPPORT 15 imply TPL_SERIAL_SUPPORT 16 select DEBUG_UART_BOARD_INIT 17 help 18 The Rockchip PX30 is a ARM-based SoC with a quad-core Cortex-A35 19 including NEON and GPU, Mali-400 graphics, several DDR3 options 20 and video codec support. Peripherals include Gigabit Ethernet, 21 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. 22 23if ROCKCHIP_PX30 24 25config TPL_LDSCRIPT 26 default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds" 27 28config TPL_TEXT_BASE 29 default 0xff0e1000 30 31config TPL_MAX_SIZE 32 default 10240 33 34config ROCKCHIP_RK3326 35 bool "Support Rockchip RK3326 " 36 help 37 RK3326 can use most code from PX30, but at some situations we have 38 to distinguish between RK3326 and PX30, so this macro gives help. 39 It is usually selected in rk3326 board defconfig. 40endif 41 42config ROCKCHIP_RK3036 43 bool "Support Rockchip RK3036" 44 select CPU_V7 45 select SUPPORT_SPL 46 select SUPPORT_TPL 47 select SPL 48 select TPL 49 select BOARD_LATE_INIT 50 select ROCKCHIP_BROM_HELPER 51 select TPL_NEEDS_SEPARATE_TEXT_BASE if TPL 52 select TPL_NEEDS_SEPARATE_STACK if TPL 53 select DEBUG_UART_BOARD_INIT 54 select ARM_SMCCC 55 help 56 The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7 57 including NEON and GPU, Mali-400 graphics, several DDR3 options 58 and video codec support. Peripherals include Gigabit Ethernet, 59 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. 60 61config ROCKCHIP_RK3128 62 bool "Support Rockchip RK3128" 63 select CPU_V7 64 select GICV2 65 select ARM_SMCCC 66 help 67 The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7 68 including NEON and GPU, Mali-400 graphics, several DDR3 options 69 and video codec support. Peripherals include Gigabit Ethernet, 70 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. 71 72if ROCKCHIP_RK3128 73 74config ROCKCHIP_RK3126 75 bool "Support Rockchip RK3126 " 76 help 77 RK3126 can use most code from RK3128, but at some situations we have 78 to distinguish between RK3126 and RK3128, so this macro gives help. 79 It is usually selected in rk3126 board defconfig. 80endif 81 82config ROCKCHIP_RK3066 83 bool "Support Rockchip RK3066" 84 select CPU_V7 85 select SUPPORT_SPL 86 select SUPPORT_TPL 87 select SPL 88 select TPL 89 select BOARD_LATE_INIT 90 select ROCKCHIP_BROM_HELPER 91 select SPL_ROCKCHIP_EARLYRETURN_TO_BROM 92 help 93 The Rockchip RK3066 is a ARM-based SoC with a dual-core Cortex-A9 94 including NEON and GPU, Mali-400 graphics, several DDR3 options 95 and video codec support. Peripherals include ethernet, USB2 host 96 and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. 97 98config ROCKCHIP_RK3188 99 bool "Support Rockchip RK3188" 100 select CPU_V7 101 select SPL_BOARD_INIT if SPL 102 select SUPPORT_SPL 103 select SPL 104 select SPL_CLK 105 select SPL_REGMAP 106 select SPL_SYSCON 107 select SPL_RAM 108 select SPL_DRIVERS_MISC_SUPPORT 109 select SPL_ROCKCHIP_EARLYRETURN_TO_BROM 110 select BOARD_LATE_INIT 111 select ROCKCHIP_BROM_HELPER 112 help 113 The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9 114 including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two 115 video interfaces, several memory options and video codec support. 116 Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S, 117 UART, SPI, I2C and PWMs. 118 119config ROCKCHIP_RK322X 120 bool "Support Rockchip RK3228/RK3229" 121 select CPU_V7 122 select SUPPORT_SPL 123 select SUPPORT_TPL 124 select SPL 125 select TPL 126 select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL 127 select TPL_NEEDS_SEPARATE_STACK if TPL 128 select SPL_DRIVERS_MISC_SUPPORT 129 imply SPL_SERIAL_SUPPORT 130 imply TPL_SERIAL_SUPPORT 131 select ROCKCHIP_BROM_HELPER 132 select DEBUG_UART_BOARD_INIT 133 select TPL_LIBCOMMON_SUPPORT 134 select TPL_LIBGENERIC_SUPPORT 135 select GICV2 136 select ARM_SMCCC 137 help 138 The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7 139 including NEON and GPU, Mali-400 graphics, several DDR3 options 140 and video codec support. Peripherals include Gigabit Ethernet, 141 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. 142 143config ROCKCHIP_RK3288 144 bool "Support Rockchip RK3288" 145 select CPU_V7 146 select SPL_BOARD_INIT if SPL 147 select SUPPORT_SPL 148 select SPL 149 select GICV2 150 select ARM_SMCCC 151 help 152 The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17 153 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two 154 video interfaces supporting HDMI and eDP, several DDR3 options 155 and video codec support. Peripherals include Gigabit Ethernet, 156 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. 157 158config ROCKCHIP_RK3308 159 bool "Support Rockchip RK3308" 160 select ARM64 if !ARM64_BOOT_AARCH32 161 select DEBUG_UART_BOARD_INIT 162 select ARM_SMCCC 163 help 164 The Rockchip RK3308 is a ARM-based Soc which embeded with quad 165 Cortex-A35 and highly integrated audio interfaces. 166 167config ROCKCHIP_RK3328 168 bool "Support Rockchip RK3328" 169 select ARM64 170 select GICV2 171 select SUPPORT_SPL 172 select SUPPORT_TPL 173 select SPL 174 select TPL 175 select TPL_NEEDS_SEPARATE_TEXT_BASE if TPL 176 select TPL_NEEDS_SEPARATE_STACK if TPL 177 imply SPL_SERIAL_SUPPORT 178 imply TPL_SERIAL_SUPPORT 179 imply SPL_SEPARATE_BSS 180 select DEBUG_UART_BOARD_INIT 181 select ARM_SMCCC 182 help 183 The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53. 184 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two 185 video interfaces supporting HDMI and eDP, several DDR3 options 186 and video codec support. Peripherals include Gigabit Ethernet, 187 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. 188 189if ROCKCHIP_RK3328 190 191config TPL_LDSCRIPT 192 default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds" 193 194config TPL_TEXT_BASE 195 default 0xff091000 196 197config TPL_MAX_SIZE 198 default 28672 199 200config TPL_STACK 201 default 0xff098000 202 203endif 204 205config ROCKCHIP_RK3368 206 bool "Support Rockchip RK3368" 207 select ARM64 208 select SUPPORT_SPL 209 select SUPPORT_TPL 210 select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL 211 select TPL_NEEDS_SEPARATE_STACK if TPL 212 imply SPL_SEPARATE_BSS 213 imply SPL_SERIAL_SUPPORT 214 imply TPL_SERIAL_SUPPORT 215 select DEBUG_UART_BOARD_INIT 216 select GICV2 217 select ARM_SMCCC 218 help 219 The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised 220 into a big and little cluster with 4 cores each) Cortex-A53 including 221 AdvSIMD, 512KB L2 cache (for the big cluster) and 256 KB L2 cache 222 (for the little cluster), PowerVR G6110 based graphics, one video 223 output processor supporting LVDS/HDMI/eDP, several DDR3 options and 224 video codec support. 225 226 On-chip peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, 227 I2S, UARTs, SPI, I2C and PWMs. 228 229if ROCKCHIP_RK3368 230 231config TPL_LDSCRIPT 232 default "arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds" 233 234config TPL_TEXT_BASE 235 default 0xff8c1000 236 237config TPL_MAX_SIZE 238 default 28672 239 240config TPL_STACK 241 default 0xff8cffff 242 243endif 244 245config ROCKCHIP_RK3399 246 bool "Support Rockchip RK3399" 247 select ARM64 248 select SUPPORT_SPL 249 select SPL 250 select SPL_SEPARATE_BSS 251 select SPL_SERIAL_SUPPORT 252 select SPL_DRIVERS_MISC_SUPPORT 253 select DEBUG_UART_BOARD_INIT 254 select GICV3 255 select BOARD_LATE_INIT 256 select ROCKCHIP_BROM_HELPER 257 select ARM_SMCCC 258 help 259 The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72 260 and quad-core Cortex-A53. 261 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two 262 video interfaces supporting HDMI and eDP, several DDR3 options 263 and video codec support. Peripherals include Gigabit Ethernet, 264 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. 265 266config ROCKCHIP_RV1108 267 bool "Support Rockchip RV1108" 268 select CPU_V7 269 select SUPPORT_SPL 270 select SPL 271 select BOARD_LATE_INIT 272 help 273 The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7 274 and a DSP. 275 276config SPL_ROCKCHIP_BACK_TO_BROM 277 bool "SPL returns to bootrom" 278 default y if ROCKCHIP_RK3036 279 select ROCKCHIP_BROM_HELPER 280 depends on SPL 281 help 282 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled, 283 SPL will return to the boot rom, which will then load the U-Boot 284 binary to keep going on. 285 286config TPL_ROCKCHIP_BACK_TO_BROM 287 bool "TPL returns to bootrom" 288 default y if ROCKCHIP_RK3368 || ROCKCHIP_RK3328 289 select ROCKCHIP_BROM_HELPER 290 depends on TPL 291 help 292 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled, 293 SPL will return to the boot rom, which will then load the U-Boot 294 binary to keep going on. 295 296config ARM64_BOOT_AARCH32 297 bool "Support Boot an ARM64 on AArch32 execution state" 298 select CPU_V7 299 default n 300 help 301 If you want to boot an ARM64 processor on 32-bit mode, say y here. 302 303config ROCKCHIP_BOOT_MODE_REG 304 hex "Rockchip boot mode flag register address" 305 default 0xff010200 if ROCKCHIP_PX30 306 default 0x200081c8 if ROCKCHIP_RK3036 307 default 0x100a0038 if ROCKCHIP_RK3128 308 default 0x20004040 if ROCKCHIP_RK3188 309 default 0x110005c8 if ROCKCHIP_RK322X 310 default 0xff730094 if ROCKCHIP_RK3288 311 default 0xff000500 if ROCKCHIP_RK3308 312 default 0xff1005c8 if ROCKCHIP_RK3328 313 default 0xff738200 if ROCKCHIP_RK3368 314 default 0xff320300 if ROCKCHIP_RK3399 315 default 0x10300580 if ROCKCHIP_RV1108 316 default 0 317 help 318 The Soc will enter to different boot mode(defined in asm/arch/boot_mode.h) 319 according to the value from this register. 320 321config ROCKCHIP_STIMER_BASE 322 hex "Rockchip Secure timer base address" 323 default 0xff220020 if ROCKCHIP_PX30 324 default 0x200440a0 if ROCKCHIP_RK3036 325 default 0x2000e000 if ROCKCHIP_RK3066 326 default 0x20018020 if ROCKCHIP_RK3126 327 default 0x200440a0 if ROCKCHIP_RK3128 328 default 0x2000e000 if ROCKCHIP_RK3188 329 default 0x110d0020 if ROCKCHIP_RK322X 330 default 0xff810020 if ROCKCHIP_RK3288 331 default 0xff1d0020 if ROCKCHIP_RK3328 332 default 0xff830020 if ROCKCHIP_RK3368 333 default 0xff8680a0 if ROCKCHIP_RK3399 334 default 0x10350020 if ROCKCHIP_RV1108 335 default 0 336 help 337 The secure timer inited in SPL/TPL in secure word, ARM generic timer 338 works after this timer work. 339 340config ROCKCHIP_IRAM_START_ADDR 341 hex "Rockchip Secure timer base address" 342 default 0xff0e0000 if ROCKCHIP_PX30 343 default 0x10080000 if ROCKCHIP_RK3036 344 default 0x10080000 if ROCKCHIP_RK3128 345 default 0x10080000 if ROCKCHIP_RK3188 346 default 0x10080000 if ROCKCHIP_RK322X 347 default 0xff700000 if ROCKCHIP_RK3288 348 default 0xfff80000 if ROCKCHIP_RK3308 349 default 0xff091000 if ROCKCHIP_RK3328 350 default 0xff8c0000 if ROCKCHIP_RK3368 351 default 0xff8c0000 if ROCKCHIP_RK3399 352 default 0x10080000 if ROCKCHIP_RV1108 353 default 0 354 help 355 The IRAM start addr is to locate variant of the boot device from 356 bootrom. 357 358config ROCKCHIP_SPL_RESERVE_IRAM 359 hex "Size of IRAM reserved in SPL" 360 default 0 361 help 362 SPL may need reserve memory for firmware loaded by SPL, whose load 363 address is in IRAM and may overlay with SPL text area if not 364 reserved. 365 366config ROCKCHIP_BROM_HELPER 367 bool 368 369config SPL_ROCKCHIP_EARLYRETURN_TO_BROM 370 bool "SPL requires early-return (for RK3188-style BROM) to BROM" 371 depends on SPL && ENABLE_ARM_SOC_BOOT0_HOOK 372 help 373 Some Rockchip BROM variants (e.g. on the RK3188) load the 374 first stage in segments and enter multiple times. E.g. on 375 the RK3188, the first 1KB of the first stage are loaded 376 first and entered; after returning to the BROM, the 377 remainder of the first stage is loaded, but the BROM 378 re-enters at the same address/to the same code as previously. 379 380 This enables support code in the BOOT0 hook for the SPL stage 381 to allow multiple entries. 382 383config TPL_ROCKCHIP_EARLYRETURN_TO_BROM 384 bool "TPL requires early-return (for RK3188-style BROM) to BROM" 385 depends on TPL && ENABLE_ARM_SOC_BOOT0_HOOK 386 help 387 Some Rockchip BROM variants (e.g. on the RK3188) load the 388 first stage in segments and enter multiple times. E.g. on 389 the RK3188, the first 1KB of the first stage are loaded 390 first and entered; after returning to the BROM, the 391 remainder of the first stage is loaded, but the BROM 392 re-enters at the same address/to the same code as previously. 393 394 This enables support code in the BOOT0 hook for the TPL stage 395 to allow multiple entries. 396 397config SPL_MMC_SUPPORT 398 default y if !SPL_ROCKCHIP_BACK_TO_BROM 399 400config RKIMG_BOOTLOADER 401 bool "Support for Rockchip Image Bootloader boot flow" 402 default n 403 help 404 Rockchip use this to boot Android during development cycle and for 405 other OS, typical content kernel.img with zImage/Image, boot.img and 406 recovery.img with Ramdisk, packed with 'KNRL' header; and resource.img 407 with dtb and uboot/kernel logo bmp, vendor storage for custom info 408 like SN and MAC address. 409 410config ROCKCHIP_RESOURCE_IMAGE 411 bool "Enable support for rockchip resource image" 412 depends on RKIMG_BOOTLOADER 413 default y 414 help 415 This enables support to get dtb or logo files from 416 rockchip resource image format partition. 417 418config ROCKCHIP_VENDOR_PARTITION 419 bool "Rockchip vendor storage partition support" 420 depends on RKIMG_BOOTLOADER 421 help 422 This enable support to read/write vendor configuration data from/to 423 this partition. 424 425config USING_KERNEL_DTB 426 bool "Using dtb from Kernel/resource for U-Boot" 427 depends on RKIMG_BOOTLOADER && OF_LIVE 428 default y 429 help 430 This enable support to read dtb from resource and use it for U-Boot, 431 the uart and emmc will still using U-Boot dtb, but other devices like 432 regulator/pmic, display, usb will use dts node from kernel. 433 434config ROCKCHIP_CRC 435 bool "Rockchip CRC verify images" 436 help 437 This enable support Rockchip CRC verify images. It takes a lot of time, 438 so it is better only used for debug. 439 440config ROCKCHIP_SMCCC 441 bool "Rockchip SMCCC" 442 default y if ARM_SMCCC 443 help 444 This enable support for Rockchip SMC calls 445 446config ROCKCHIP_DEBUGGER 447 bool "Rockchip debugger" 448 depends on IRQ 449 help 450 This enable support for Rockchip debugger. Now we install a timer interrupt 451 and dump pt_regs when the timeout event trigger. This helps us to know cpu 452 state when system hang. 453 454config ROCKCHIP_CRASH_DUMP 455 bool "Rockchip crash dump registers" 456 help 457 This enable dump registers when system crash, the registers you would like 458 to dump can be added in show_regs(). 459 460config GICV2 461 bool "ARM GICv2" 462 463config GICV3 464 bool "ARM GICv3" 465 466source "arch/arm/mach-rockchip/px30/Kconfig" 467source "arch/arm/mach-rockchip/rk3036/Kconfig" 468source "arch/arm/mach-rockchip/rk3066/Kconfig" 469source "arch/arm/mach-rockchip/rk3128/Kconfig" 470source "arch/arm/mach-rockchip/rk3188/Kconfig" 471source "arch/arm/mach-rockchip/rk322x/Kconfig" 472source "arch/arm/mach-rockchip/rk3288/Kconfig" 473source "arch/arm/mach-rockchip/rk3308/Kconfig" 474source "arch/arm/mach-rockchip/rk3328/Kconfig" 475source "arch/arm/mach-rockchip/rk3368/Kconfig" 476source "arch/arm/mach-rockchip/rk3399/Kconfig" 477source "arch/arm/mach-rockchip/rv1108/Kconfig" 478endif 479