1/* 2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#include <dt-bindings/clock/rk3328-cru.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12 13/ { 14 compatible = "rockchip,rk3328"; 15 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 serial0 = &uart0; 22 serial1 = &uart1; 23 serial2 = &uart2; 24 i2c0 = &i2c0; 25 i2c1 = &i2c1; 26 i2c2 = &i2c2; 27 i2c3 = &i2c3; 28 mmc0 = &emmc; 29 mmc1 = &sdmmc; 30 mmc2 = &sdmmc_ext; 31 }; 32 33 cpus { 34 #address-cells = <2>; 35 #size-cells = <0>; 36 37 cpu0: cpu@0 { 38 device_type = "cpu"; 39 compatible = "arm,cortex-a53", "arm,armv8"; 40 reg = <0x0 0x0>; 41 enable-method = "psci"; 42// clocks = <&cru ARMCLK>; 43 operating-points-v2 = <&cpu0_opp_table>; 44 }; 45 cpu1: cpu@1 { 46 device_type = "cpu"; 47 compatible = "arm,cortex-a53", "arm,armv8"; 48 reg = <0x0 0x1>; 49 enable-method = "psci"; 50 }; 51 cpu2: cpu@2 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a53", "arm,armv8"; 54 reg = <0x0 0x2>; 55 enable-method = "psci"; 56 }; 57 cpu3: cpu@3 { 58 device_type = "cpu"; 59 compatible = "arm,cortex-a53", "arm,armv8"; 60 reg = <0x0 0x3>; 61 enable-method = "psci"; 62 }; 63 }; 64 65 cpu0_opp_table: opp_table0 { 66 compatible = "operating-points-v2"; 67 opp-shared; 68 69 opp@408000000 { 70 opp-hz = /bits/ 64 <408000000>; 71 opp-microvolt = <950000>; 72 clock-latency-ns = <40000>; 73 opp-suspend; 74 }; 75 opp@600000000 { 76 opp-hz = /bits/ 64 <600000000>; 77 opp-microvolt = <950000>; 78 clock-latency-ns = <40000>; 79 }; 80 opp@816000000 { 81 opp-hz = /bits/ 64 <816000000>; 82 opp-microvolt = <1000000>; 83 clock-latency-ns = <40000>; 84 }; 85 opp@1008000000 { 86 opp-hz = /bits/ 64 <1008000000>; 87 opp-microvolt = <1100000>; 88 clock-latency-ns = <40000>; 89 }; 90 opp@1200000000 { 91 opp-hz = /bits/ 64 <1200000000>; 92 opp-microvolt = <1225000>; 93 clock-latency-ns = <40000>; 94 }; 95 opp@1296000000 { 96 opp-hz = /bits/ 64 <1296000000>; 97 opp-microvolt = <1300000>; 98 clock-latency-ns = <40000>; 99 }; 100 }; 101 102 arm-pmu { 103 compatible = "arm,cortex-a53-pmu"; 104 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 108 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 109 }; 110 111 psci { 112 compatible = "arm,psci-1.0"; 113 method = "smc"; 114 }; 115 116 timer { 117 compatible = "arm,armv8-timer"; 118 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 119 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 120 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 121 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 122 }; 123 124 xin24m: xin24m { 125 compatible = "fixed-clock"; 126 #clock-cells = <0>; 127 clock-frequency = <24000000>; 128 clock-output-names = "xin24m"; 129 }; 130 131 i2s0: i2s@ff000000 { 132 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 133 reg = <0x0 0xff000000 0x0 0x1000>; 134 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 135 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; 136 clock-names = "i2s_clk", "i2s_hclk"; 137 dmas = <&dmac 11>, <&dmac 12>; 138 #dma-cells = <2>; 139 dma-names = "tx", "rx"; 140 status = "disabled"; 141 }; 142 143 i2s1: i2s@ff010000 { 144 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 145 reg = <0x0 0xff010000 0x0 0x1000>; 146 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 147 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; 148 clock-names = "i2s_clk", "i2s_hclk"; 149 dmas = <&dmac 14>, <&dmac 15>; 150 #dma-cells = <2>; 151 dma-names = "tx", "rx"; 152 status = "disabled"; 153 }; 154 155 i2s2: i2s@ff020000 { 156 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 157 reg = <0x0 0xff020000 0x0 0x1000>; 158 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 159 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; 160 clock-names = "i2s_clk", "i2s_hclk"; 161 dmas = <&dmac 0>, <&dmac 1>; 162 #dma-cells = <2>; 163 dma-names = "tx", "rx"; 164 pinctrl-names = "default", "sleep"; 165 pinctrl-0 = <&i2s2m0_mclk 166 &i2s2m0_sclk 167 &i2s2m0_lrcktx 168 &i2s2m0_lrckrx 169 &i2s2m0_sdo 170 &i2s2m0_sdi>; 171 pinctrl-1 = <&i2s2m0_sleep>; 172 status = "disabled"; 173 }; 174 175 spdif: spdif@ff030000 { 176 compatible = "rockchip,rk3328-spdif"; 177 reg = <0x0 0xff030000 0x0 0x1000>; 178 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 179 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; 180 clock-names = "mclk", "hclk"; 181 dmas = <&dmac 10>; 182 #dma-cells = <1>; 183 dma-names = "tx"; 184 pinctrl-names = "default"; 185 pinctrl-0 = <&spdifm2_tx>; 186 status = "disabled"; 187 }; 188 189 grf: syscon@ff100000 { 190 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd"; 191 reg = <0x0 0xff100000 0x0 0x1000>; 192 #address-cells = <1>; 193 #size-cells = <1>; 194 195 io_domains: io-domains { 196 compatible = "rockchip,rk3328-io-voltage-domain"; 197 status = "disabled"; 198 }; 199 }; 200 201 uart0: serial@ff110000 { 202 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 203 reg = <0x0 0xff110000 0x0 0x100>; 204 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 205 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 206 clock-names = "baudclk", "apb_pclk"; 207 reg-shift = <2>; 208 reg-io-width = <4>; 209 dmas = <&dmac 2>, <&dmac 3>; 210 #dma-cells = <2>; 211 pinctrl-names = "default"; 212 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 213 status = "disabled"; 214 }; 215 216 uart1: serial@ff120000 { 217 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 218 reg = <0x0 0xff120000 0x0 0x100>; 219 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 220 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 221 clock-names = "sclk_uart", "pclk_uart"; 222 reg-shift = <2>; 223 reg-io-width = <4>; 224 dmas = <&dmac 4>, <&dmac 5>; 225 #dma-cells = <2>; 226 pinctrl-names = "default"; 227 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 228 status = "disabled"; 229 }; 230 231 uart2: serial@ff130000 { 232 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 233 reg = <0x0 0xff130000 0x0 0x100>; 234 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 235 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 236 clock-names = "baudclk", "apb_pclk"; 237 clock-frequency = <24000000>; 238 reg-shift = <2>; 239 reg-io-width = <4>; 240 dmas = <&dmac 6>, <&dmac 7>; 241 #dma-cells = <2>; 242 pinctrl-names = "default"; 243 pinctrl-0 = <&uart2m1_xfer>; 244 status = "disabled"; 245 }; 246 247 pmu: power-management@ff140000 { 248 compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd"; 249 reg = <0x0 0xff140000 0x0 0x1000>; 250 }; 251 252 i2c0: i2c@ff150000 { 253 compatible = "rockchip,rk3328-i2c"; 254 reg = <0x0 0xff150000 0x0 0x1000>; 255 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 256 #address-cells = <1>; 257 #size-cells = <0>; 258 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 259 clock-names = "i2c", "pclk"; 260 pinctrl-names = "default"; 261 pinctrl-0 = <&i2c0_xfer>; 262 status = "disabled"; 263 }; 264 265 i2c1: i2c@ff160000 { 266 compatible = "rockchip,rk3328-i2c"; 267 reg = <0x0 0xff160000 0x0 0x1000>; 268 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 269 #address-cells = <1>; 270 #size-cells = <0>; 271 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 272 clock-names = "i2c", "pclk"; 273 pinctrl-names = "default"; 274 pinctrl-0 = <&i2c1_xfer>; 275 status = "disabled"; 276 }; 277 278 i2c2: i2c@ff170000 { 279 compatible = "rockchip,rk3328-i2c"; 280 reg = <0x0 0xff170000 0x0 0x1000>; 281 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 282 #address-cells = <1>; 283 #size-cells = <0>; 284 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 285 clock-names = "i2c", "pclk"; 286 pinctrl-names = "default"; 287 pinctrl-0 = <&i2c2_xfer>; 288 status = "disabled"; 289 }; 290 291 i2c3: i2c@ff180000 { 292 compatible = "rockchip,rk3328-i2c"; 293 reg = <0x0 0xff180000 0x0 0x1000>; 294 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 295 #address-cells = <1>; 296 #size-cells = <0>; 297 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 298 clock-names = "i2c", "pclk"; 299 pinctrl-names = "default"; 300 pinctrl-0 = <&i2c3_xfer>; 301 status = "disabled"; 302 }; 303 304 spi0: spi@ff190000 { 305 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi"; 306 reg = <0x0 0xff190000 0x0 0x1000>; 307 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 308 #address-cells = <1>; 309 #size-cells = <0>; 310 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>; 311 clock-names = "spiclk", "apb_pclk"; 312 dmas = <&dmac 8>, <&dmac 9>; 313 #dma-cells = <2>; 314 dma-names = "tx", "rx"; 315 pinctrl-names = "default"; 316 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>; 317 status = "disabled"; 318 }; 319 320 wdt: watchdog@ff1a0000 { 321 compatible = "snps,dw-wdt"; 322 reg = <0x0 0xff1a0000 0x0 0x100>; 323 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 324 status = "disabled"; 325 }; 326 327 amba { 328 compatible = "simple-bus"; 329 #address-cells = <2>; 330 #size-cells = <2>; 331 ranges; 332 333 dmac: dmac@ff1f0000 { 334 compatible = "arm,pl330", "arm,primecell"; 335 reg = <0x0 0xff1f0000 0x0 0x4000>; 336 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 337 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 338 clocks = <&cru ACLK_DMAC>; 339 clock-names = "apb_pclk"; 340 #dma-cells = <1>; 341 }; 342 }; 343 344 saradc: saradc@ff280000 { 345 compatible = "rockchip,rk3328-saradc", "rockchip,saradc"; 346 reg = <0x0 0xff280000 0x0 0x100>; 347 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 348 #io-channel-cells = <1>; 349 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 350 clock-names = "saradc", "apb_pclk"; 351 resets = <&cru SRST_SARADC_P>; 352 reset-names = "saradc-apb"; 353 status = "disabled"; 354 }; 355 356 dmc: dmc { 357 compatible = "rockchip,rk3328-dmc"; 358 reg = <0x0 0xff400000 0x0 0x1000 359 0x0 0xff780000 0x0 0x3000 360 0x0 0xff100000 0x0 0x1000 361 0x0 0xff440000 0x0 0x1000 362 0x0 0xff720000 0x0 0x1000 363 0x0 0xff798000 0x0 0x1000>; 364 }; 365 366 cru: clock-controller@ff440000 { 367 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon"; 368 reg = <0x0 0xff440000 0x0 0x1000>; 369 rockchip,grf = <&grf>; 370 #clock-cells = <1>; 371 #reset-cells = <1>; 372 assigned-clocks = 373 <&cru DCLK_LCDC>, <&cru SCLK_PDM>, 374 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>, 375 <&cru SCLK_UART1>, <&cru SCLK_UART2>, 376 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 377 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>, 378 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>, 379 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>, 380 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>, 381 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>, 382 <&cru SCLK_SDIO>, <&cru SCLK_TSP>, 383 <&cru SCLK_WIFI>, <&cru ARMCLK>, 384 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 385 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>, 386 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 387 <&cru HCLK_PERI>, <&cru PCLK_PERI>, 388 <&cru ACLK_VIO_PRE>, <&cru HCLK_VIO_PRE>, 389 <&cru ACLK_RGA_PRE>, <&cru SCLK_RGA>, 390 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>, 391 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>, 392 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>, 393 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>, 394 <&cru SCLK_EFUSE>, <&cru PCLK_DDR>, 395 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>, 396 <&cru SCLK_RTC32K>, <&cru SCLK_USB3OTG_SUSPEND>; 397 assigned-clock-parents = 398 <&cru HDMIPHY>, <&cru PLL_APLL>, 399 <&cru PLL_GPLL>, <&xin24m>, 400 <&xin24m>, <&xin24m>; 401 assigned-clock-rates = 402 <0>, <61440000>, 403 <0>, <24000000>, 404 <24000000>, <24000000>, 405 <15000000>, <15000000>, 406 <100000000>, <100000000>, 407 <100000000>, <100000000>, 408 <50000000>, <100000000>, 409 <100000000>, <100000000>, 410 <50000000>, <50000000>, 411 <50000000>, <50000000>, 412 <24000000>, <600000000>, 413 <491520000>, <1200000000>, 414 <150000000>, <75000000>, 415 <75000000>, <150000000>, 416 <75000000>, <75000000>, 417 <300000000>, <100000000>, 418 <300000000>, <200000000>, 419 <400000000>, <500000000>, 420 <200000000>, <300000000>, 421 <300000000>, <250000000>, 422 <200000000>, <100000000>, 423 <24000000>, <100000000>, 424 <150000000>, <50000000>, 425 <32768>, <32768>; 426 }; 427 428 usb2phy_grf: syscon-usb@ff450000 { 429 compatible = "rockchip,rk3328-usb2phy-grf", 430 "simple-mfd", "syscon"; 431 reg = <0x0 0xff450000 0x0 0x10000>; 432 #address-cells = <1>; 433 #size-cells = <1>; 434 435 u2phy: usb2-phy@100 { 436 compatible = "rockchip,rk3328-usb2phy"; 437 reg = <0x100 0x10>; 438 clocks = <&xin24m>; 439 clock-names = "phyclk"; 440 clock-output-names = "usb480m_phy"; 441 #clock-cells = <0>; 442 assigned-clocks = <&cru USB480M>; 443 assigned-clock-parents = <&u2phy>; 444 #phy-cells = <1>; 445 status = "disabled"; 446 447 u2phy_otg: otg-port { 448 #phy-cells = <0>; 449 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 450 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 451 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 452 interrupt-names = "otg-bvalid", "otg-id", 453 "linestate"; 454 status = "disabled"; 455 }; 456 457 u2phy_host: host-port { 458 #phy-cells = <0>; 459 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 460 interrupt-names = "linestate"; 461 status = "disabled"; 462 }; 463 }; 464 }; 465 466 sdmmc: rksdmmc@ff500000 { 467 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 468 reg = <0x0 0xff500000 0x0 0x4000>; 469 max-frequency = <150000000>; 470 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; 471 clock-names = "biu", "ciu"; 472 fifo-depth = <0x100>; 473 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 474 status = "disabled"; 475 }; 476 477 sdio: dwmmc@ff510000 { 478 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 479 reg = <0x0 0xff510000 0x0 0x4000>; 480 max-frequency = <150000000>; 481 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 482 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 483 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 484 fifo-depth = <0x100>; 485 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 486 status = "disabled"; 487 }; 488 489 emmc: rksdmmc@ff520000 { 490 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 491 reg = <0x0 0xff520000 0x0 0x4000>; 492 max-frequency = <150000000>; 493 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; 494 clock-names = "biu", "ciu"; 495 fifo-depth = <0x100>; 496 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 497 status = "disabled"; 498 }; 499 500 gmac2io: ethernet@ff540000 { 501 compatible = "rockchip,rk3328-gmac"; 502 reg = <0x0 0xff540000 0x0 0x10000>; 503 rockchip,grf = <&grf>; 504 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 505 interrupt-names = "macirq"; 506 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>, 507 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>, 508 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>, 509 <&cru PCLK_MAC2IO>; 510 clock-names = "stmmaceth", "mac_clk_rx", 511 "mac_clk_tx", "clk_mac_ref", 512 "clk_mac_refout", "aclk_mac", 513 "pclk_mac"; 514 resets = <&cru SRST_GMAC2IO_A>; 515 reset-names = "stmmaceth"; 516 status = "disabled"; 517 }; 518 519 usb_host0_ehci: usb@ff5c0000 { 520 compatible = "generic-ehci"; 521 reg = <0x0 0xff5c0000 0x0 0x10000>; 522 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 523 phys = <&u2phy 1>; 524 phy-names = "usb"; 525 status = "disabled"; 526 }; 527 528 usb_host0_ohci: usb@ff5d0000 { 529 compatible = "generic-ohci"; 530 reg = <0x0 0xff5d0000 0x0 0x10000>; 531 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 532 phys = <&u2phy 1>; 533 phy-names = "usb"; 534 status = "disabled"; 535 }; 536 537 usb20_otg: usb@ff580000 { 538 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb", 539 "snps,dwc2"; 540 reg = <0x0 0xff580000 0x0 0x40000>; 541 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 542 hnp-srp-disable; 543 dr_mode = "otg"; 544 phys = <&u2phy 0>; 545 phy-names = "usb"; 546 status = "disabled"; 547 }; 548 549 sdmmc_ext: rksdmmc@ff5f0000 { 550 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 551 reg = <0x0 0xff5f0000 0x0 0x4000>; 552 max-frequency = <150000000>; 553 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; 554 clock-names = "biu", "ciu"; 555 fifo-depth = <0x100>; 556 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 557 status = "disabled"; 558 }; 559 560 usb_host0_xhci: usb@ff600000 { 561 compatible = "rockchip,rk3328-xhci"; 562 reg = <0x0 0xff600000 0x0 0x100000>; 563 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 564 snps,dis-enblslpm-quirk; 565 snps,phyif-utmi-bits = <16>; 566 snps,dis-u2-freeclk-exists-quirk; 567 snps,dis-u2-susphy-quirk; 568 status = "disabled"; 569 }; 570 571 gic: interrupt-controller@ffb70000 { 572 compatible = "arm,gic-400"; 573 #interrupt-cells = <3>; 574 #address-cells = <0>; 575 interrupt-controller; 576 reg = <0x0 0xff811000 0 0x1000>, 577 <0x0 0xff812000 0 0x2000>, 578 <0x0 0xff814000 0 0x2000>, 579 <0x0 0xff816000 0 0x2000>; 580 interrupts = <GIC_PPI 9 581 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 582 }; 583 584 pinctrl: pinctrl { 585 compatible = "rockchip,rk3328-pinctrl"; 586 rockchip,grf = <&grf>; 587 #address-cells = <2>; 588 #size-cells = <2>; 589 ranges; 590 591 gpio0: gpio0@ff210000 { 592 compatible = "rockchip,gpio-bank"; 593 reg = <0x0 0xff210000 0x0 0x100>; 594 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 595 clocks = <&cru PCLK_GPIO0>; 596 597 gpio-controller; 598 #gpio-cells = <2>; 599 600 interrupt-controller; 601 #interrupt-cells = <2>; 602 }; 603 604 gpio1: gpio1@ff220000 { 605 compatible = "rockchip,gpio-bank"; 606 reg = <0x0 0xff220000 0x0 0x100>; 607 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 608 clocks = <&cru PCLK_GPIO1>; 609 610 gpio-controller; 611 #gpio-cells = <2>; 612 613 interrupt-controller; 614 #interrupt-cells = <2>; 615 }; 616 617 gpio2: gpio2@ff230000 { 618 compatible = "rockchip,gpio-bank"; 619 reg = <0x0 0xff230000 0x0 0x100>; 620 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 621 clocks = <&cru PCLK_GPIO2>; 622 623 gpio-controller; 624 #gpio-cells = <2>; 625 626 interrupt-controller; 627 #interrupt-cells = <2>; 628 }; 629 630 gpio3: gpio3@ff240000 { 631 compatible = "rockchip,gpio-bank"; 632 reg = <0x0 0xff240000 0x0 0x100>; 633 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 634 clocks = <&cru PCLK_GPIO3>; 635 636 gpio-controller; 637 #gpio-cells = <2>; 638 639 interrupt-controller; 640 #interrupt-cells = <2>; 641 }; 642 643 pcfg_pull_up: pcfg-pull-up { 644 bias-pull-up; 645 }; 646 647 pcfg_pull_down: pcfg-pull-down { 648 bias-pull-down; 649 }; 650 651 pcfg_pull_none: pcfg-pull-none { 652 bias-disable; 653 }; 654 655 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 656 bias-disable; 657 drive-strength = <2>; 658 }; 659 660 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 661 bias-pull-up; 662 drive-strength = <2>; 663 }; 664 665 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 666 bias-pull-up; 667 drive-strength = <4>; 668 }; 669 670 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 671 bias-disable; 672 drive-strength = <4>; 673 }; 674 675 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 676 bias-pull-down; 677 drive-strength = <4>; 678 }; 679 680 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 681 bias-disable; 682 drive-strength = <8>; 683 }; 684 685 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 686 bias-pull-up; 687 drive-strength = <8>; 688 }; 689 690 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 691 bias-disable; 692 drive-strength = <12>; 693 }; 694 695 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 696 bias-pull-up; 697 drive-strength = <12>; 698 }; 699 700 pcfg_output_high: pcfg-output-high { 701 output-high; 702 }; 703 704 pcfg_output_low: pcfg-output-low { 705 output-low; 706 }; 707 708 pcfg_input_high: pcfg-input-high { 709 bias-pull-up; 710 input-enable; 711 }; 712 713 pcfg_input: pcfg-input { 714 input-enable; 715 }; 716 717 i2c0 { 718 i2c0_xfer: i2c0-xfer { 719 rockchip,pins = 720 <2 24 RK_FUNC_1 &pcfg_pull_none>, 721 <2 25 RK_FUNC_1 &pcfg_pull_none>; 722 }; 723 }; 724 725 i2c1 { 726 i2c1_xfer: i2c1-xfer { 727 rockchip,pins = 728 <2 4 RK_FUNC_2 &pcfg_pull_none>, 729 <2 5 RK_FUNC_2 &pcfg_pull_none>; 730 }; 731 }; 732 733 i2c2 { 734 i2c2_xfer: i2c2-xfer { 735 rockchip,pins = 736 <2 13 RK_FUNC_1 &pcfg_pull_none>, 737 <2 14 RK_FUNC_1 &pcfg_pull_none>; 738 }; 739 }; 740 741 i2c3 { 742 i2c3_xfer: i2c3-xfer { 743 rockchip,pins = 744 <0 5 RK_FUNC_2 &pcfg_pull_none>, 745 <0 6 RK_FUNC_2 &pcfg_pull_none>; 746 }; 747 i2c3_gpio: i2c3-gpio { 748 rockchip,pins = 749 <0 5 RK_FUNC_GPIO &pcfg_pull_none>, 750 <0 6 RK_FUNC_GPIO &pcfg_pull_none>; 751 }; 752 }; 753 754 hdmi_i2c { 755 hdmii2c_xfer: hdmii2c-xfer { 756 rockchip,pins = 757 <0 5 RK_FUNC_1 &pcfg_pull_none>, 758 <0 6 RK_FUNC_1 &pcfg_pull_none>; 759 }; 760 }; 761 762 uart0 { 763 uart0_xfer: uart0-xfer { 764 rockchip,pins = 765 <1 9 RK_FUNC_1 &pcfg_pull_up>, 766 <1 8 RK_FUNC_1 &pcfg_pull_up>; 767 }; 768 769 uart0_cts: uart0-cts { 770 rockchip,pins = 771 <1 11 RK_FUNC_1 &pcfg_pull_none>; 772 }; 773 774 uart0_rts: uart0-rts { 775 rockchip,pins = 776 <1 10 RK_FUNC_1 &pcfg_pull_none>; 777 }; 778 779 uart0_rts_gpio: uart0-rts-gpio { 780 rockchip,pins = 781 <1 10 RK_FUNC_GPIO &pcfg_pull_none>; 782 }; 783 }; 784 785 uart1 { 786 uart1_xfer: uart1-xfer { 787 rockchip,pins = 788 <3 4 RK_FUNC_4 &pcfg_pull_up>, 789 <3 6 RK_FUNC_4 &pcfg_pull_up>; 790 }; 791 792 uart1_cts: uart1-cts { 793 rockchip,pins = 794 <3 7 RK_FUNC_4 &pcfg_pull_none>; 795 }; 796 797 uart1_rts: uart1-rts { 798 rockchip,pins = 799 <3 5 RK_FUNC_4 &pcfg_pull_none>; 800 }; 801 802 uart1_rts_gpio: uart1-rts-gpio { 803 rockchip,pins = 804 <3 5 RK_FUNC_GPIO &pcfg_pull_none>; 805 }; 806 }; 807 808 uart2-0 { 809 uart2m0_xfer: uart2m0-xfer { 810 rockchip,pins = 811 <1 0 RK_FUNC_2 &pcfg_pull_up>, 812 <1 1 RK_FUNC_2 &pcfg_pull_up>; 813 }; 814 }; 815 816 uart2-1 { 817 uart2m1_xfer: uart2m1-xfer { 818 rockchip,pins = 819 <2 0 RK_FUNC_1 &pcfg_pull_up>, 820 <2 1 RK_FUNC_1 &pcfg_pull_up>; 821 }; 822 }; 823 824 spi0-0 { 825 spi0m0_clk: spi0m0-clk { 826 rockchip,pins = 827 <2 8 RK_FUNC_1 &pcfg_pull_up>; 828 }; 829 830 spi0m0_cs0: spi0m0-cs0 { 831 rockchip,pins = 832 <2 11 RK_FUNC_1 &pcfg_pull_up>; 833 }; 834 835 spi0m0_tx: spi0m0-tx { 836 rockchip,pins = 837 <2 9 RK_FUNC_1 &pcfg_pull_up>; 838 }; 839 840 spi0m0_rx: spi0m0-rx { 841 rockchip,pins = 842 <2 10 RK_FUNC_1 &pcfg_pull_up>; 843 }; 844 845 spi0m0_cs1: spi0m0-cs1 { 846 rockchip,pins = 847 <2 12 RK_FUNC_1 &pcfg_pull_up>; 848 }; 849 }; 850 851 spi0-1 { 852 spi0m1_clk: spi0m1-clk { 853 rockchip,pins = 854 <3 23 RK_FUNC_2 &pcfg_pull_up>; 855 }; 856 857 spi0m1_cs0: spi0m1-cs0 { 858 rockchip,pins = 859 <3 26 RK_FUNC_2 &pcfg_pull_up>; 860 }; 861 862 spi0m1_tx: spi0m1-tx { 863 rockchip,pins = 864 <3 25 RK_FUNC_2 &pcfg_pull_up>; 865 }; 866 867 spi0m1_rx: spi0m1-rx { 868 rockchip,pins = 869 <3 24 RK_FUNC_2 &pcfg_pull_up>; 870 }; 871 872 spi0m1_cs1: spi0m1-cs1 { 873 rockchip,pins = 874 <3 27 RK_FUNC_2 &pcfg_pull_up>; 875 }; 876 }; 877 878 spi0-2 { 879 spi0m2_clk: spi0m2-clk { 880 rockchip,pins = 881 <3 0 RK_FUNC_4 &pcfg_pull_up>; 882 }; 883 884 spi0m2_cs0: spi0m2-cs0 { 885 rockchip,pins = 886 <3 8 RK_FUNC_3 &pcfg_pull_up>; 887 }; 888 889 spi0m2_tx: spi0m2-tx { 890 rockchip,pins = 891 <3 1 RK_FUNC_4 &pcfg_pull_up>; 892 }; 893 894 spi0m2_rx: spi0m2-rx { 895 rockchip,pins = 896 <3 2 RK_FUNC_4 &pcfg_pull_up>; 897 }; 898 }; 899 900 i2s1 { 901 i2s1_mclk: i2s1-mclk { 902 rockchip,pins = 903 <2 15 RK_FUNC_1 &pcfg_pull_none>; 904 }; 905 906 i2s1_sclk: i2s1-sclk { 907 rockchip,pins = 908 <2 18 RK_FUNC_1 &pcfg_pull_none>; 909 }; 910 911 i2s1_lrckrx: i2s1-lrckrx { 912 rockchip,pins = 913 <2 16 RK_FUNC_1 &pcfg_pull_none>; 914 }; 915 916 i2s1_lrcktx: i2s1-lrcktx { 917 rockchip,pins = 918 <2 17 RK_FUNC_1 &pcfg_pull_none>; 919 }; 920 921 i2s1_sdi: i2s1-sdi { 922 rockchip,pins = 923 <2 19 RK_FUNC_1 &pcfg_pull_none>; 924 }; 925 926 i2s1_sdo: i2s1-sdo { 927 rockchip,pins = 928 <2 23 RK_FUNC_1 &pcfg_pull_none>; 929 }; 930 931 i2s1_sdio1: i2s1-sdio1 { 932 rockchip,pins = 933 <2 20 RK_FUNC_1 &pcfg_pull_none>; 934 }; 935 936 i2s1_sdio2: i2s1-sdio2 { 937 rockchip,pins = 938 <2 21 RK_FUNC_1 &pcfg_pull_none>; 939 }; 940 941 i2s1_sdio3: i2s1-sdio3 { 942 rockchip,pins = 943 <2 22 RK_FUNC_1 &pcfg_pull_none>; 944 }; 945 946 i2s1_sleep: i2s1-sleep { 947 rockchip,pins = 948 <2 15 RK_FUNC_GPIO &pcfg_input_high>, 949 <2 16 RK_FUNC_GPIO &pcfg_input_high>, 950 <2 17 RK_FUNC_GPIO &pcfg_input_high>, 951 <2 18 RK_FUNC_GPIO &pcfg_input_high>, 952 <2 19 RK_FUNC_GPIO &pcfg_input_high>, 953 <2 20 RK_FUNC_GPIO &pcfg_input_high>, 954 <2 21 RK_FUNC_GPIO &pcfg_input_high>, 955 <2 22 RK_FUNC_GPIO &pcfg_input_high>, 956 <2 23 RK_FUNC_GPIO &pcfg_input_high>; 957 }; 958 }; 959 960 i2s2-0 { 961 i2s2m0_mclk: i2s2m0-mclk { 962 rockchip,pins = 963 <1 21 RK_FUNC_1 &pcfg_pull_none>; 964 }; 965 966 i2s2m0_sclk: i2s2m0-sclk { 967 rockchip,pins = 968 <1 22 RK_FUNC_1 &pcfg_pull_none>; 969 }; 970 971 i2s2m0_lrckrx: i2s2m0-lrckrx { 972 rockchip,pins = 973 <1 26 RK_FUNC_1 &pcfg_pull_none>; 974 }; 975 976 i2s2m0_lrcktx: i2s2m0-lrcktx { 977 rockchip,pins = 978 <1 23 RK_FUNC_1 &pcfg_pull_none>; 979 }; 980 981 i2s2m0_sdi: i2s2m0-sdi { 982 rockchip,pins = 983 <1 24 RK_FUNC_1 &pcfg_pull_none>; 984 }; 985 986 i2s2m0_sdo: i2s2m0-sdo { 987 rockchip,pins = 988 <1 25 RK_FUNC_1 &pcfg_pull_none>; 989 }; 990 991 i2s2m0_sleep: i2s2m0-sleep { 992 rockchip,pins = 993 <1 21 RK_FUNC_GPIO &pcfg_input_high>, 994 <1 22 RK_FUNC_GPIO &pcfg_input_high>, 995 <1 26 RK_FUNC_GPIO &pcfg_input_high>, 996 <1 23 RK_FUNC_GPIO &pcfg_input_high>, 997 <1 24 RK_FUNC_GPIO &pcfg_input_high>, 998 <1 25 RK_FUNC_GPIO &pcfg_input_high>; 999 }; 1000 }; 1001 1002 i2s2-1 { 1003 i2s2m1_mclk: i2s2m1-mclk { 1004 rockchip,pins = 1005 <1 21 RK_FUNC_1 &pcfg_pull_none>; 1006 }; 1007 1008 i2s2m1_sclk: i2s2m1-sclk { 1009 rockchip,pins = 1010 <3 0 RK_FUNC_6 &pcfg_pull_none>; 1011 }; 1012 1013 i2s2m1_lrckrx: i2sm1-lrckrx { 1014 rockchip,pins = 1015 <3 8 RK_FUNC_6 &pcfg_pull_none>; 1016 }; 1017 1018 i2s2m1_lrcktx: i2s2m1-lrcktx { 1019 rockchip,pins = 1020 <3 8 RK_FUNC_4 &pcfg_pull_none>; 1021 }; 1022 1023 i2s2m1_sdi: i2s2m1-sdi { 1024 rockchip,pins = 1025 <3 2 RK_FUNC_6 &pcfg_pull_none>; 1026 }; 1027 1028 i2s2m1_sdo: i2s2m1-sdo { 1029 rockchip,pins = 1030 <3 1 RK_FUNC_6 &pcfg_pull_none>; 1031 }; 1032 1033 i2s2m1_sleep: i2s2m1-sleep { 1034 rockchip,pins = 1035 <1 21 RK_FUNC_GPIO &pcfg_input_high>, 1036 <3 0 RK_FUNC_GPIO &pcfg_input_high>, 1037 <3 8 RK_FUNC_GPIO &pcfg_input_high>, 1038 <3 2 RK_FUNC_GPIO &pcfg_input_high>, 1039 <3 1 RK_FUNC_GPIO &pcfg_input_high>; 1040 }; 1041 }; 1042 1043 spdif-0 { 1044 spdifm0_tx: spdifm0-tx { 1045 rockchip,pins = 1046 <0 27 RK_FUNC_1 &pcfg_pull_none>; 1047 }; 1048 }; 1049 1050 spdif-1 { 1051 spdifm1_tx: spdifm1-tx { 1052 rockchip,pins = 1053 <2 17 RK_FUNC_2 &pcfg_pull_none>; 1054 }; 1055 }; 1056 1057 spdif-2 { 1058 spdifm2_tx: spdifm2-tx { 1059 rockchip,pins = 1060 <0 2 RK_FUNC_2 &pcfg_pull_none>; 1061 }; 1062 }; 1063 1064 sdmmc0-0 { 1065 sdmmc0m0_pwren: sdmmc0m0-pwren { 1066 rockchip,pins = 1067 <2 7 RK_FUNC_1 &pcfg_pull_up_4ma>; 1068 }; 1069 1070 sdmmc0m0_gpio: sdmmc0m0-gpio { 1071 rockchip,pins = 1072 <2 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1073 }; 1074 }; 1075 1076 sdmmc0-1 { 1077 sdmmc0m1_pwren: sdmmc0m1-pwren { 1078 rockchip,pins = 1079 <0 30 RK_FUNC_3 &pcfg_pull_up_4ma>; 1080 }; 1081 1082 sdmmc0m1_gpio: sdmmc0m1-gpio { 1083 rockchip,pins = 1084 <0 30 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1085 }; 1086 }; 1087 1088 sdmmc0 { 1089 sdmmc0_clk: sdmmc0-clk { 1090 rockchip,pins = 1091 <1 6 RK_FUNC_1 &pcfg_pull_none_4ma>; 1092 }; 1093 1094 sdmmc0_cmd: sdmmc0-cmd { 1095 rockchip,pins = 1096 <1 4 RK_FUNC_1 &pcfg_pull_up_4ma>; 1097 }; 1098 1099 sdmmc0_dectn: sdmmc0-dectn { 1100 rockchip,pins = 1101 <1 5 RK_FUNC_1 &pcfg_pull_up_4ma>; 1102 }; 1103 1104 sdmmc0_wrprt: sdmmc0-wrprt { 1105 rockchip,pins = 1106 <1 7 RK_FUNC_1 &pcfg_pull_up_4ma>; 1107 }; 1108 1109 sdmmc0_bus1: sdmmc0-bus1 { 1110 rockchip,pins = 1111 <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>; 1112 }; 1113 1114 sdmmc0_bus4: sdmmc0-bus4 { 1115 rockchip,pins = 1116 <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>, 1117 <1 1 RK_FUNC_1 &pcfg_pull_up_4ma>, 1118 <1 2 RK_FUNC_1 &pcfg_pull_up_4ma>, 1119 <1 3 RK_FUNC_1 &pcfg_pull_up_4ma>; 1120 }; 1121 1122 sdmmc0_gpio: sdmmc0-gpio { 1123 rockchip,pins = 1124 <1 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1125 <1 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1126 <1 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1127 <1 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1128 <1 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1129 <1 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1130 <1 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1131 <1 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1132 }; 1133 }; 1134 1135 sdmmc0ext { 1136 sdmmc0ext_clk: sdmmc0ext-clk { 1137 rockchip,pins = 1138 <3 2 RK_FUNC_3 &pcfg_pull_none_4ma>; 1139 }; 1140 1141 sdmmc0ext_cmd: sdmmc0ext-cmd { 1142 rockchip,pins = 1143 <3 0 RK_FUNC_3 &pcfg_pull_up_4ma>; 1144 }; 1145 1146 sdmmc0ext_wrprt: sdmmc0ext-wrprt { 1147 rockchip,pins = 1148 <3 3 RK_FUNC_3 &pcfg_pull_up_4ma>; 1149 }; 1150 1151 sdmmc0ext_dectn: sdmmc0ext-dectn { 1152 rockchip,pins = 1153 <3 1 RK_FUNC_3 &pcfg_pull_up_4ma>; 1154 }; 1155 1156 sdmmc0ext_bus1: sdmmc0ext-bus1 { 1157 rockchip,pins = 1158 <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>; 1159 }; 1160 1161 sdmmc0ext_bus4: sdmmc0ext-bus4 { 1162 rockchip,pins = 1163 <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>, 1164 <3 5 RK_FUNC_3 &pcfg_pull_up_4ma>, 1165 <3 6 RK_FUNC_3 &pcfg_pull_up_4ma>, 1166 <3 7 RK_FUNC_3 &pcfg_pull_up_4ma>; 1167 }; 1168 1169 sdmmc0ext_gpio: sdmmc0ext-gpio { 1170 rockchip,pins = 1171 <3 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1172 <3 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1173 <3 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1174 <3 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1175 <3 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1176 <3 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1177 <3 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1178 <3 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1179 }; 1180 }; 1181 1182 sdmmc1 { 1183 sdmmc1_clk: sdmmc1-clk { 1184 rockchip,pins = 1185 <1 12 RK_FUNC_1 &pcfg_pull_none_8ma>; 1186 }; 1187 1188 sdmmc1_cmd: sdmmc1-cmd { 1189 rockchip,pins = 1190 <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>; 1191 }; 1192 1193 sdmmc1_pwren: sdmmc1-pwren { 1194 rockchip,pins = 1195 <1 18 RK_FUNC_1 &pcfg_pull_up_8ma>; 1196 }; 1197 1198 sdmmc1_wrprt: sdmmc1-wrprt { 1199 rockchip,pins = 1200 <1 20 RK_FUNC_1 &pcfg_pull_up_8ma>; 1201 }; 1202 1203 sdmmc1_dectn: sdmmc1-dectn { 1204 rockchip,pins = 1205 <1 19 RK_FUNC_1 &pcfg_pull_up_8ma>; 1206 }; 1207 1208 sdmmc1_bus1: sdmmc1-bus1 { 1209 rockchip,pins = 1210 <1 14 RK_FUNC_1 &pcfg_pull_up_8ma>; 1211 }; 1212 1213 sdmmc1_bus4: sdmmc1-bus4 { 1214 rockchip,pins = 1215 <1 12 RK_FUNC_1 &pcfg_pull_up_8ma>, 1216 <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>, 1217 <1 16 RK_FUNC_1 &pcfg_pull_up_8ma>, 1218 <1 17 RK_FUNC_1 &pcfg_pull_up_8ma>; 1219 }; 1220 1221 sdmmc1_gpio: sdmmc1-gpio { 1222 rockchip,pins = 1223 <1 12 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1224 <1 13 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1225 <1 14 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1226 <1 15 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1227 <1 16 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1228 <1 17 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1229 <1 18 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1230 <1 19 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1231 <1 20 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1232 }; 1233 }; 1234 1235 emmc { 1236 emmc_clk: emmc-clk { 1237 rockchip,pins = 1238 <3 21 RK_FUNC_2 &pcfg_pull_none_12ma>; 1239 }; 1240 1241 emmc_cmd: emmc-cmd { 1242 rockchip,pins = 1243 <3 19 RK_FUNC_2 &pcfg_pull_up_12ma>; 1244 }; 1245 1246 emmc_pwren: emmc-pwren { 1247 rockchip,pins = 1248 <3 22 RK_FUNC_2 &pcfg_pull_none>; 1249 }; 1250 1251 emmc_rstnout: emmc-rstnout { 1252 rockchip,pins = 1253 <3 20 RK_FUNC_2 &pcfg_pull_none>; 1254 }; 1255 1256 emmc_bus1: emmc-bus1 { 1257 rockchip,pins = 1258 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>; 1259 }; 1260 1261 emmc_bus4: emmc-bus4 { 1262 rockchip,pins = 1263 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>, 1264 <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>, 1265 <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>, 1266 <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>; 1267 }; 1268 1269 emmc_bus8: emmc-bus8 { 1270 rockchip,pins = 1271 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>, 1272 <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>, 1273 <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>, 1274 <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>, 1275 <2 31 RK_FUNC_2 &pcfg_pull_up_12ma>, 1276 <3 16 RK_FUNC_2 &pcfg_pull_up_12ma>, 1277 <3 17 RK_FUNC_2 &pcfg_pull_up_12ma>, 1278 <3 18 RK_FUNC_2 &pcfg_pull_up_12ma>; 1279 }; 1280 }; 1281 1282 pwm0 { 1283 pwm0_pin: pwm0-pin { 1284 rockchip,pins = 1285 <2 4 RK_FUNC_1 &pcfg_pull_none>; 1286 }; 1287 }; 1288 1289 pwm1 { 1290 pwm1_pin: pwm1-pin { 1291 rockchip,pins = 1292 <2 5 RK_FUNC_1 &pcfg_pull_none>; 1293 }; 1294 }; 1295 1296 pwm2 { 1297 pwm2_pin: pwm2-pin { 1298 rockchip,pins = 1299 <2 6 RK_FUNC_1 &pcfg_pull_none>; 1300 }; 1301 }; 1302 1303 pwmir { 1304 pwmir_pin: pwmir-pin { 1305 rockchip,pins = 1306 <2 2 RK_FUNC_1 &pcfg_pull_none>; 1307 }; 1308 }; 1309 1310 gmac-0 { 1311 rgmiim0_pins: rgmiim0-pins { 1312 rockchip,pins = 1313 /* mac_txclk */ 1314 <0 8 RK_FUNC_1 &pcfg_pull_none_12ma>, 1315 /* mac_rxclk */ 1316 <0 10 RK_FUNC_1 &pcfg_pull_none>, 1317 /* mac_mdio */ 1318 <0 11 RK_FUNC_1 &pcfg_pull_none>, 1319 /* mac_txen */ 1320 <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>, 1321 /* mac_clk */ 1322 <0 24 RK_FUNC_1 &pcfg_pull_none>, 1323 /* mac_rxdv */ 1324 <0 25 RK_FUNC_1 &pcfg_pull_none>, 1325 /* mac_mdc */ 1326 <0 19 RK_FUNC_1 &pcfg_pull_none>, 1327 /* mac_rxd1 */ 1328 <0 14 RK_FUNC_1 &pcfg_pull_none>, 1329 /* mac_rxd0 */ 1330 <0 15 RK_FUNC_1 &pcfg_pull_none>, 1331 /* mac_txd1 */ 1332 <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>, 1333 /* mac_txd0 */ 1334 <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>, 1335 /* mac_rxd3 */ 1336 <0 20 RK_FUNC_1 &pcfg_pull_none>, 1337 /* mac_rxd2 */ 1338 <0 21 RK_FUNC_1 &pcfg_pull_none>, 1339 /* mac_txd3 */ 1340 <0 23 RK_FUNC_1 &pcfg_pull_none_12ma>, 1341 /* mac_txd2 */ 1342 <0 22 RK_FUNC_1 &pcfg_pull_none_12ma>; 1343 }; 1344 1345 rmiim0_pins: rmiim0-pins { 1346 rockchip,pins = 1347 /* mac_mdio */ 1348 <0 11 RK_FUNC_1 &pcfg_pull_none>, 1349 /* mac_txen */ 1350 <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>, 1351 /* mac_clk */ 1352 <0 24 RK_FUNC_1 &pcfg_pull_none>, 1353 /* mac_rxer */ 1354 <0 13 RK_FUNC_1 &pcfg_pull_none>, 1355 /* mac_rxdv */ 1356 <0 25 RK_FUNC_1 &pcfg_pull_none>, 1357 /* mac_mdc */ 1358 <0 19 RK_FUNC_1 &pcfg_pull_none>, 1359 /* mac_rxd1 */ 1360 <0 14 RK_FUNC_1 &pcfg_pull_none>, 1361 /* mac_rxd0 */ 1362 <0 15 RK_FUNC_1 &pcfg_pull_none>, 1363 /* mac_txd1 */ 1364 <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>, 1365 /* mac_txd0 */ 1366 <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>; 1367 }; 1368 }; 1369 1370 gmac-1 { 1371 rgmiim1_pins: rgmiim1-pins { 1372 rockchip,pins = 1373 /* mac_txclk */ 1374 <1 12 RK_FUNC_2 &pcfg_pull_none_12ma>, 1375 /* mac_rxclk */ 1376 <1 13 RK_FUNC_2 &pcfg_pull_none_2ma>, 1377 /* mac_mdio */ 1378 <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>, 1379 /* mac_txen */ 1380 <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>, 1381 /* mac_clk */ 1382 <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>, 1383 /* mac_rxdv */ 1384 <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>, 1385 /* mac_mdc */ 1386 <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>, 1387 /* mac_rxd1 */ 1388 <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>, 1389 /* mac_rxd0 */ 1390 <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>, 1391 /* mac_txd1 */ 1392 <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>, 1393 /* mac_txd0 */ 1394 <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>, 1395 /* mac_rxd3 */ 1396 <1 14 RK_FUNC_2 &pcfg_pull_none_2ma>, 1397 /* mac_rxd2 */ 1398 <1 15 RK_FUNC_2 &pcfg_pull_none_2ma>, 1399 /* mac_txd3 */ 1400 <1 16 RK_FUNC_2 &pcfg_pull_none_12ma>, 1401 /* mac_txd2 */ 1402 <1 17 RK_FUNC_2 &pcfg_pull_none_12ma>, 1403 1404 /* mac_txclk */ 1405 <0 8 RK_FUNC_1 &pcfg_pull_none>, 1406 /* mac_txen */ 1407 <0 12 RK_FUNC_1 &pcfg_pull_none>, 1408 /* mac_clk */ 1409 <0 24 RK_FUNC_1 &pcfg_pull_none>, 1410 /* mac_txd1 */ 1411 <0 16 RK_FUNC_1 &pcfg_pull_none>, 1412 /* mac_txd0 */ 1413 <0 17 RK_FUNC_1 &pcfg_pull_none>, 1414 /* mac_txd3 */ 1415 <0 23 RK_FUNC_1 &pcfg_pull_none>, 1416 /* mac_txd2 */ 1417 <0 22 RK_FUNC_1 &pcfg_pull_none>; 1418 }; 1419 1420 rmiim1_pins: rmiim1-pins { 1421 rockchip,pins = 1422 /* mac_mdio */ 1423 <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>, 1424 /* mac_txen */ 1425 <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>, 1426 /* mac_clk */ 1427 <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>, 1428 /* mac_rxer */ 1429 <1 24 RK_FUNC_2 &pcfg_pull_none_2ma>, 1430 /* mac_rxdv */ 1431 <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>, 1432 /* mac_mdc */ 1433 <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>, 1434 /* mac_rxd1 */ 1435 <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>, 1436 /* mac_rxd0 */ 1437 <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>, 1438 /* mac_txd1 */ 1439 <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>, 1440 /* mac_txd0 */ 1441 <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>, 1442 1443 /* mac_mdio */ 1444 <0 11 RK_FUNC_1 &pcfg_pull_none>, 1445 /* mac_txen */ 1446 <0 12 RK_FUNC_1 &pcfg_pull_none>, 1447 /* mac_clk */ 1448 <0 24 RK_FUNC_1 &pcfg_pull_none>, 1449 /* mac_mdc */ 1450 <0 19 RK_FUNC_1 &pcfg_pull_none>, 1451 /* mac_txd1 */ 1452 <0 16 RK_FUNC_1 &pcfg_pull_none>, 1453 /* mac_txd0 */ 1454 <0 17 RK_FUNC_1 &pcfg_pull_none>; 1455 }; 1456 }; 1457 1458 gmac2phy { 1459 fephyled_speed100: fephyled-speed100 { 1460 rockchip,pins = 1461 <0 31 RK_FUNC_1 &pcfg_pull_none>; 1462 }; 1463 1464 fephyled_speed10: fephyled-speed10 { 1465 rockchip,pins = 1466 <0 30 RK_FUNC_1 &pcfg_pull_none>; 1467 }; 1468 1469 fephyled_duplex: fephyled-duplex { 1470 rockchip,pins = 1471 <0 30 RK_FUNC_2 &pcfg_pull_none>; 1472 }; 1473 1474 fephyled_rxm0: fephyled-rxm0 { 1475 rockchip,pins = 1476 <0 29 RK_FUNC_1 &pcfg_pull_none>; 1477 }; 1478 1479 fephyled_txm0: fephyled-txm0 { 1480 rockchip,pins = 1481 <0 29 RK_FUNC_2 &pcfg_pull_none>; 1482 }; 1483 1484 fephyled_linkm0: fephyled-linkm0 { 1485 rockchip,pins = 1486 <0 28 RK_FUNC_1 &pcfg_pull_none>; 1487 }; 1488 1489 fephyled_rxm1: fephyled-rxm1 { 1490 rockchip,pins = 1491 <2 25 RK_FUNC_2 &pcfg_pull_none>; 1492 }; 1493 1494 fephyled_txm1: fephyled-txm1 { 1495 rockchip,pins = 1496 <2 25 RK_FUNC_3 &pcfg_pull_none>; 1497 }; 1498 1499 fephyled_linkm1: fephyled-linkm1 { 1500 rockchip,pins = 1501 <2 24 RK_FUNC_2 &pcfg_pull_none>; 1502 }; 1503 }; 1504 1505 tsadc_pin { 1506 tsadc_int: tsadc-int { 1507 rockchip,pins = 1508 <2 13 RK_FUNC_2 &pcfg_pull_none>; 1509 }; 1510 tsadc_gpio: tsadc-gpio { 1511 rockchip,pins = 1512 <2 13 RK_FUNC_GPIO &pcfg_pull_none>; 1513 }; 1514 }; 1515 1516 hdmi_pin { 1517 hdmi_cec: hdmi-cec { 1518 rockchip,pins = 1519 <0 3 RK_FUNC_1 &pcfg_pull_none>; 1520 }; 1521 1522 hdmi_hpd: hdmi-hpd { 1523 rockchip,pins = 1524 <0 4 RK_FUNC_1 &pcfg_pull_down>; 1525 }; 1526 }; 1527 1528 cif-0 { 1529 dvp_d2d9_m0:dvp-d2d9-m0 { 1530 rockchip,pins = 1531 /* cif_d0 */ 1532 <3 4 RK_FUNC_2 &pcfg_pull_none>, 1533 /* cif_d1 */ 1534 <3 5 RK_FUNC_2 &pcfg_pull_none>, 1535 /* cif_d2 */ 1536 <3 6 RK_FUNC_2 &pcfg_pull_none>, 1537 /* cif_d3 */ 1538 <3 7 RK_FUNC_2 &pcfg_pull_none>, 1539 /* cif_d4 */ 1540 <3 8 RK_FUNC_2 &pcfg_pull_none>, 1541 /* cif_d5m0 */ 1542 <3 9 RK_FUNC_2 &pcfg_pull_none>, 1543 /* cif_d6m0 */ 1544 <3 10 RK_FUNC_2 &pcfg_pull_none>, 1545 /* cif_d7m0 */ 1546 <3 11 RK_FUNC_2 &pcfg_pull_none>, 1547 /* cif_href */ 1548 <3 1 RK_FUNC_2 &pcfg_pull_none>, 1549 /* cif_vsync */ 1550 <3 0 RK_FUNC_2 &pcfg_pull_none>, 1551 /* cif_clkoutm0 */ 1552 <3 3 RK_FUNC_2 &pcfg_pull_none>, 1553 /* cif_clkin */ 1554 <3 2 RK_FUNC_2 &pcfg_pull_none>; 1555 }; 1556 }; 1557 1558 cif-1 { 1559 dvp_d2d9_m1:dvp-d2d9-m1 { 1560 rockchip,pins = 1561 /* cif_d0 */ 1562 <3 4 RK_FUNC_2 &pcfg_pull_none>, 1563 /* cif_d1 */ 1564 <3 5 RK_FUNC_2 &pcfg_pull_none>, 1565 /* cif_d2 */ 1566 <3 6 RK_FUNC_2 &pcfg_pull_none>, 1567 /* cif_d3 */ 1568 <3 7 RK_FUNC_2 &pcfg_pull_none>, 1569 /* cif_d4 */ 1570 <3 8 RK_FUNC_2 &pcfg_pull_none>, 1571 /* cif_d5m1 */ 1572 <2 16 RK_FUNC_4 &pcfg_pull_none>, 1573 /* cif_d6m1 */ 1574 <2 17 RK_FUNC_4 &pcfg_pull_none>, 1575 /* cif_d7m1 */ 1576 <2 18 RK_FUNC_4 &pcfg_pull_none>, 1577 /* cif_href */ 1578 <3 1 RK_FUNC_2 &pcfg_pull_none>, 1579 /* cif_vsync */ 1580 <3 0 RK_FUNC_2 &pcfg_pull_none>, 1581 /* cif_clkoutm1 */ 1582 <2 15 RK_FUNC_4 &pcfg_pull_none>, 1583 /* cif_clkin */ 1584 <3 2 RK_FUNC_2 &pcfg_pull_none>; 1585 }; 1586 }; 1587 }; 1588}; 1589