1 /* 2 * Copyright (C) 2017 Rockchip Electronics Co., Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ASM_ARCH_SDRAM_COMMON_H 8 #define _ASM_ARCH_SDRAM_COMMON_H 9 10 enum { 11 DDR4 = 0, 12 DDR2 = 2, 13 DDR3 = 3, 14 LPDDR2 = 5, 15 LPDDR3 = 6, 16 LPDDR4 = 7, 17 UNUSED = 0xFF 18 }; 19 20 /* 21 * sys_reg bitfield struct 22 * [31] row_3_4_ch1 23 * [30] row_3_4_ch0 24 * [29:28] chinfo 25 * [27] rank_ch1 26 * [26:25] col_ch1 27 * [24] bk_ch1 28 * [23:22] low bits of cs0_row_ch1 29 * [21:20] low bits of cs1_row_ch1 30 * [19:18] bw_ch1 31 * [17:16] dbw_ch1; 32 * [15:13] ddrtype 33 * [12] channelnum 34 * [11] rank_ch0 35 * [10:9] col_ch0, 36 * [8] bk_ch0 37 * [7:6] low bits of cs0_row_ch0 38 * [5:4] low bits of cs1_row_ch0 39 * [3:2] bw_ch0 40 * [1:0] dbw_ch0 41 * 42 * sys_reg1 bitfield struct 43 * [7] high bit of cs0_row_ch1 44 * [6] high bit of cs1_row_ch1 45 * [5] high bit of cs0_row_ch0 46 * [4] high bit of cs1_row_ch0 47 * [3:2] cs1_col_ch1 48 * [1:0] cs1_col_ch0 49 */ 50 #define SYS_REG_DDRTYPE_SHIFT 13 51 #define SYS_REG_DDRTYPE_MASK 7 52 #define SYS_REG_NUM_CH_SHIFT 12 53 #define SYS_REG_NUM_CH_MASK 1 54 #define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch)) 55 #define SYS_REG_ROW_3_4_MASK 1 56 #define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch)) 57 #define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16) 58 #define SYS_REG_RANK_MASK 1 59 #define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16) 60 #define SYS_REG_COL_MASK 3 61 #define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16) 62 #define SYS_REG_BK_MASK 1 63 #define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) 64 #define SYS_REG_CS0_ROW_MASK 3 65 #define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) 66 #define SYS_REG_CS1_ROW_MASK 3 67 #define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16) 68 #define SYS_REG_BW_MASK 3 69 #define SYS_REG_DBW_SHIFT(ch) ((ch) * 16) 70 #define SYS_REG_DBW_MASK 3 71 72 #define SYS_REG1_VERSION_SHIFT 28 73 #define SYS_REG1_VERSION_MASK 0xf 74 #define SYS_REG1_EXTEND_CS0_ROW_SHIFT(ch) (5 + (ch) * 2) 75 #define SYS_REG1_EXTEND_CS0_ROW_MASK 1 76 #define SYS_REG1_EXTEND_CS1_ROW_SHIFT(ch) (4 + (ch) * 2) 77 #define SYS_REG1_EXTEND_CS1_ROW_MASK 1 78 #define SYS_REG1_CS1_COL_SHIFT(ch) (0 + (ch) * 2) 79 #define SYS_REG1_CS1_COL_MASK 3 80 81 #define BROM_BOOTSOURCE_ID_ADDR (CONFIG_ROCKCHIP_IRAM_START_ADDR + 0x10) 82 83 /* Get sdram size decode from reg */ 84 size_t rockchip_sdram_size(phys_addr_t reg); 85 86 /* Called by U-Boot board_init_r for Rockchip SoCs */ 87 int dram_init(void); 88 89 /* Write ddr param to a known place for trustos */ 90 int rockchip_setup_ddr_param(struct ram_info *info); 91 92 #endif 93