1 /* 2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <common.h> 8 #include <bitfield.h> 9 #include <clk-uclass.h> 10 #include <dm.h> 11 #include <errno.h> 12 #include <syscon.h> 13 #include <asm/arch/clock.h> 14 #include <asm/arch/cru_px30.h> 15 #include <asm/arch/hardware.h> 16 #include <asm/io.h> 17 #include <dm/lists.h> 18 #include <dt-bindings/clock/px30-cru.h> 19 20 DECLARE_GLOBAL_DATA_PTR; 21 22 enum { 23 VCO_MAX_HZ = 3200U * 1000000, 24 VCO_MIN_HZ = 800 * 1000000, 25 OUTPUT_MAX_HZ = 3200U * 1000000, 26 OUTPUT_MIN_HZ = 24 * 1000000, 27 }; 28 29 #define PX30_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \ 30 _postdiv2, _dsmpd, _frac) \ 31 { \ 32 .rate = _rate##U, \ 33 .fbdiv = _fbdiv, \ 34 .postdiv1 = _postdiv1, \ 35 .refdiv = _refdiv, \ 36 .postdiv2 = _postdiv2, \ 37 .dsmpd = _dsmpd, \ 38 .frac = _frac, \ 39 } 40 41 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) 42 43 #define PX30_CLK_DUMP(_id, _name, _iscru) \ 44 { \ 45 .id = _id, \ 46 .name = _name, \ 47 .is_cru = _iscru, \ 48 } 49 50 static struct pll_rate_table px30_pll_rates[] = { 51 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ 52 PX30_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), 53 PX30_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0), 54 PX30_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0), 55 PX30_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0), 56 PX30_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0), 57 PX30_PLL_RATE(600000000, 1, 75, 3, 1, 1, 0), 58 }; 59 60 static const struct px30_clk_info clks_dump[] = { 61 PX30_CLK_DUMP(PLL_APLL, "apll", true), 62 PX30_CLK_DUMP(PLL_DPLL, "dpll", true), 63 PX30_CLK_DUMP(PLL_CPLL, "cpll", true), 64 PX30_CLK_DUMP(PLL_NPLL, "npll", true), 65 PX30_CLK_DUMP(PLL_GPLL, "gpll", false), 66 PX30_CLK_DUMP(ACLK_BUS_PRE, "aclk_bus", true), 67 PX30_CLK_DUMP(HCLK_BUS_PRE, "hclk_bus", true), 68 PX30_CLK_DUMP(PCLK_BUS_PRE, "pclk_bus", true), 69 PX30_CLK_DUMP(ACLK_PERI_PRE, "aclk_peri", true), 70 PX30_CLK_DUMP(HCLK_PERI_PRE, "hclk_peri", true), 71 PX30_CLK_DUMP(PCLK_PMU_PRE, "pclk_pmu", false), 72 }; 73 74 static u8 pll_mode_shift[PLL_COUNT] = { 75 APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT, 76 NPLL_MODE_SHIFT, GPLL_MODE_SHIFT 77 }; 78 static u32 pll_mode_mask[PLL_COUNT] = { 79 APLL_MODE_MASK, DPLL_MODE_MASK, CPLL_MODE_MASK, 80 NPLL_MODE_MASK, GPLL_MODE_MASK 81 }; 82 83 static struct pll_rate_table auto_table; 84 85 static struct pll_rate_table *pll_clk_set_by_auto(u32 drate) 86 { 87 struct pll_rate_table *rate = &auto_table; 88 u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0; 89 u32 postdiv1, postdiv2 = 1; 90 u32 fref_khz; 91 u32 diff_khz, best_diff_khz; 92 const u32 max_refdiv = 63, max_fbdiv = 3200, min_fbdiv = 16; 93 const u32 max_postdiv1 = 7, max_postdiv2 = 7; 94 u32 vco_khz; 95 u32 rate_khz = drate / KHz; 96 97 if (!drate) { 98 printf("%s: the frequency can't be 0 Hz\n", __func__); 99 return NULL; 100 } 101 102 postdiv1 = DIV_ROUND_UP(VCO_MIN_HZ / 1000, rate_khz); 103 if (postdiv1 > max_postdiv1) { 104 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1); 105 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2); 106 } 107 108 vco_khz = rate_khz * postdiv1 * postdiv2; 109 110 if (vco_khz < (VCO_MIN_HZ / KHz) || vco_khz > (VCO_MAX_HZ / KHz) || 111 postdiv2 > max_postdiv2) { 112 printf("%s: Cannot find out a supported VCO for Freq (%uHz)\n", 113 __func__, rate_khz); 114 return NULL; 115 } 116 117 rate->postdiv1 = postdiv1; 118 rate->postdiv2 = postdiv2; 119 120 best_diff_khz = vco_khz; 121 for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) { 122 fref_khz = ref_khz / refdiv; 123 124 fbdiv = vco_khz / fref_khz; 125 if ((fbdiv >= max_fbdiv) || (fbdiv <= min_fbdiv)) 126 continue; 127 diff_khz = vco_khz - fbdiv * fref_khz; 128 if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) { 129 fbdiv++; 130 diff_khz = fref_khz - diff_khz; 131 } 132 133 if (diff_khz >= best_diff_khz) 134 continue; 135 136 best_diff_khz = diff_khz; 137 rate->refdiv = refdiv; 138 rate->fbdiv = fbdiv; 139 } 140 141 if (best_diff_khz > 4 * (MHz / KHz)) { 142 printf("%s: Failed to match output frequency %u bestis %u Hz\n", 143 __func__, rate_khz, 144 best_diff_khz * KHz); 145 return NULL; 146 } 147 148 return rate; 149 } 150 151 static const struct pll_rate_table *get_pll_settings(unsigned long rate) 152 { 153 unsigned int rate_count = ARRAY_SIZE(px30_pll_rates); 154 int i; 155 156 for (i = 0; i < rate_count; i++) { 157 if (rate == px30_pll_rates[i].rate) 158 return &px30_pll_rates[i]; 159 } 160 161 return pll_clk_set_by_auto(rate); 162 } 163 164 /* 165 * How to calculate the PLL(from TRM V0.3 Part 1 Page 63): 166 * Formulas also embedded within the Fractional PLL Verilog model: 167 * If DSMPD = 1 (DSM is disabled, "integer mode") 168 * FOUTVCO = FREF / REFDIV * FBDIV 169 * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2 170 * Where: 171 * FOUTVCO = Fractional PLL non-divided output frequency 172 * FOUTPOSTDIV = Fractional PLL divided output frequency 173 * (output of second post divider) 174 * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input) 175 * REFDIV = Fractional PLL input reference clock divider 176 * FBDIV = Integer value programmed into feedback divide 177 * 178 */ 179 static int rkclk_set_pll(struct px30_pll *pll, unsigned int *mode, 180 enum px30_pll_id pll_id, 181 unsigned long drate) 182 { 183 const struct pll_rate_table *rate; 184 uint vco_hz, output_hz; 185 186 rate = get_pll_settings(drate); 187 if (!rate) { 188 printf("%s unsupport rate\n", __func__); 189 return -EINVAL; 190 } 191 192 /* All PLLs have same VCO and output frequency range restrictions. */ 193 vco_hz = OSC_HZ / 1000 * rate->fbdiv / rate->refdiv * 1000; 194 output_hz = vco_hz / rate->postdiv1 / rate->postdiv2; 195 196 debug("PLL at %p: fb=%d, ref=%d, pst1=%d, pst2=%d, vco=%u Hz, output=%u Hz\n", 197 pll, rate->fbdiv, rate->refdiv, rate->postdiv1, 198 rate->postdiv2, vco_hz, output_hz); 199 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && 200 output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ); 201 202 /* 203 * When power on or changing PLL setting, 204 * we must force PLL into slow mode to ensure output stable clock. 205 */ 206 rk_clrsetreg(mode, pll_mode_mask[pll_id], 207 PLLMUX_FROM_XIN24M << pll_mode_shift[pll_id]); 208 209 /* use integer mode */ 210 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); 211 /* Power down */ 212 rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT); 213 214 rk_clrsetreg(&pll->con0, 215 PLL_POSTDIV1_MASK | PLL_FBDIV_MASK, 216 (rate->postdiv1 << PLL_POSTDIV1_SHIFT) | rate->fbdiv); 217 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, 218 (rate->postdiv2 << PLL_POSTDIV2_SHIFT | 219 rate->refdiv << PLL_REFDIV_SHIFT)); 220 221 /* Power Up */ 222 rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT); 223 224 /* waiting for pll lock */ 225 while (!(readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))) 226 udelay(1); 227 228 rk_clrsetreg(mode, pll_mode_mask[pll_id], 229 PLLMUX_FROM_PLL << pll_mode_shift[pll_id]); 230 231 return 0; 232 } 233 234 static uint32_t rkclk_pll_get_rate(struct px30_pll *pll, unsigned int *mode, 235 enum px30_pll_id pll_id) 236 { 237 u32 refdiv, fbdiv, postdiv1, postdiv2; 238 u32 con, shift, mask; 239 240 con = readl(mode); 241 shift = pll_mode_shift[pll_id]; 242 mask = pll_mode_mask[pll_id]; 243 244 switch ((con & mask) >> shift) { 245 case PLLMUX_FROM_XIN24M: 246 return OSC_HZ; 247 case PLLMUX_FROM_PLL: 248 /* normal mode */ 249 con = readl(&pll->con0); 250 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; 251 fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT; 252 con = readl(&pll->con1); 253 postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; 254 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; 255 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; 256 case PLLMUX_FROM_RTC32K: 257 default: 258 return 32768; 259 } 260 } 261 262 static ulong px30_i2c_get_clk(struct px30_clk_priv *priv, ulong clk_id) 263 { 264 struct px30_cru *cru = priv->cru; 265 u32 div, con; 266 267 switch (clk_id) { 268 case SCLK_I2C0: 269 con = readl(&cru->clksel_con[49]); 270 div = con >> CLK_I2C0_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; 271 break; 272 case SCLK_I2C1: 273 con = readl(&cru->clksel_con[49]); 274 div = con >> CLK_I2C1_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; 275 break; 276 case SCLK_I2C2: 277 con = readl(&cru->clksel_con[50]); 278 div = con >> CLK_I2C2_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; 279 break; 280 case SCLK_I2C3: 281 con = readl(&cru->clksel_con[50]); 282 div = con >> CLK_I2C3_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; 283 break; 284 default: 285 printf("do not support this i2c bus\n"); 286 return -EINVAL; 287 } 288 289 return DIV_TO_RATE(priv->gpll_hz, div); 290 } 291 292 static ulong px30_i2c_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz) 293 { 294 struct px30_cru *cru = priv->cru; 295 int src_clk_div; 296 297 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 298 assert(src_clk_div - 1 < 127); 299 300 switch (clk_id) { 301 case SCLK_I2C0: 302 rk_clrsetreg(&cru->clksel_con[49], 303 CLK_I2C_DIV_CON_MASK << CLK_I2C0_DIV_CON_SHIFT | 304 CLK_I2C_PLL_SEL_MASK << CLK_I2C0_PLL_SEL_SHIFT, 305 (src_clk_div - 1) << CLK_I2C0_DIV_CON_SHIFT | 306 CLK_I2C_PLL_SEL_GPLL << CLK_I2C0_PLL_SEL_SHIFT); 307 break; 308 case SCLK_I2C1: 309 rk_clrsetreg(&cru->clksel_con[49], 310 CLK_I2C_DIV_CON_MASK << CLK_I2C1_DIV_CON_SHIFT | 311 CLK_I2C_PLL_SEL_MASK << CLK_I2C1_PLL_SEL_SHIFT, 312 (src_clk_div - 1) << CLK_I2C1_DIV_CON_SHIFT | 313 CLK_I2C_PLL_SEL_GPLL << CLK_I2C1_PLL_SEL_SHIFT); 314 break; 315 case SCLK_I2C2: 316 rk_clrsetreg(&cru->clksel_con[50], 317 CLK_I2C_DIV_CON_MASK << CLK_I2C2_DIV_CON_SHIFT | 318 CLK_I2C_PLL_SEL_MASK << CLK_I2C2_PLL_SEL_SHIFT, 319 (src_clk_div - 1) << CLK_I2C2_DIV_CON_SHIFT | 320 CLK_I2C_PLL_SEL_GPLL << CLK_I2C2_PLL_SEL_SHIFT); 321 break; 322 case SCLK_I2C3: 323 rk_clrsetreg(&cru->clksel_con[50], 324 CLK_I2C_DIV_CON_MASK << CLK_I2C3_DIV_CON_SHIFT | 325 CLK_I2C_PLL_SEL_MASK << CLK_I2C3_PLL_SEL_SHIFT, 326 (src_clk_div - 1) << CLK_I2C3_DIV_CON_SHIFT | 327 CLK_I2C_PLL_SEL_GPLL << CLK_I2C3_PLL_SEL_SHIFT); 328 break; 329 default: 330 printf("do not support this i2c bus\n"); 331 return -EINVAL; 332 } 333 334 return px30_i2c_get_clk(priv, clk_id); 335 } 336 337 static ulong px30_nandc_get_clk(struct px30_clk_priv *priv) 338 { 339 struct px30_cru *cru = priv->cru; 340 u32 div, con; 341 342 con = readl(&cru->clksel_con[15]); 343 div = (con & NANDC_DIV_MASK) >> NANDC_DIV_SHIFT; 344 345 return DIV_TO_RATE(priv->gpll_hz, div) / 2; 346 } 347 348 static ulong px30_nandc_set_clk(struct px30_clk_priv *priv, 349 ulong set_rate) 350 { 351 struct px30_cru *cru = priv->cru; 352 int src_clk_div; 353 354 /* Select nandc source from GPLL by default */ 355 /* nandc clock defaulg div 2 internal, need provide double in cru */ 356 src_clk_div = DIV_ROUND_UP(priv->gpll_hz / 2, set_rate); 357 assert(src_clk_div - 1 < 31); 358 359 rk_clrsetreg(&cru->clksel_con[15], 360 NANDC_CLK_SEL_MASK | NANDC_PLL_MASK | 361 NANDC_DIV_MASK, 362 NANDC_CLK_SEL_NANDC << NANDC_CLK_SEL_SHIFT | 363 NANDC_SEL_GPLL << NANDC_PLL_SHIFT | 364 (src_clk_div - 1) << NANDC_DIV_SHIFT); 365 366 return px30_nandc_get_clk(priv); 367 } 368 369 static ulong px30_mmc_get_clk(struct px30_clk_priv *priv, uint clk_id) 370 { 371 struct px30_cru *cru = priv->cru; 372 u32 div, con, con_id; 373 374 switch (clk_id) { 375 case HCLK_SDMMC: 376 case SCLK_SDMMC: 377 con_id = 16; 378 break; 379 case HCLK_EMMC: 380 case SCLK_EMMC: 381 case SCLK_EMMC_SAMPLE: 382 con_id = 20; 383 break; 384 default: 385 return -EINVAL; 386 } 387 388 con = readl(&cru->clksel_con[con_id]); 389 div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT; 390 391 if ((con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT 392 == EMMC_SEL_24M) 393 return DIV_TO_RATE(OSC_HZ, div) / 2; 394 else 395 return DIV_TO_RATE(priv->gpll_hz, div) / 2; 396 397 } 398 399 static ulong px30_mmc_set_clk(struct px30_clk_priv *priv, 400 ulong clk_id, ulong set_rate) 401 { 402 struct px30_cru *cru = priv->cru; 403 int src_clk_div; 404 u32 con_id; 405 406 switch (clk_id) { 407 case HCLK_SDMMC: 408 case SCLK_SDMMC: 409 con_id = 16; 410 break; 411 case HCLK_EMMC: 412 case SCLK_EMMC: 413 con_id = 20; 414 break; 415 default: 416 return -EINVAL; 417 } 418 419 /* Select clk_sdmmc/emmc source from GPLL by default */ 420 /* mmc clock defaulg div 2 internal, need provide double in cru */ 421 src_clk_div = DIV_ROUND_UP(priv->gpll_hz / 2, set_rate); 422 423 if (src_clk_div > 127) { 424 /* use 24MHz source for 400KHz clock */ 425 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate); 426 rk_clrsetreg(&cru->clksel_con[con_id], 427 EMMC_PLL_MASK | EMMC_DIV_MASK, 428 EMMC_SEL_24M << EMMC_PLL_SHIFT | 429 (src_clk_div - 1) << EMMC_DIV_SHIFT); 430 } else { 431 rk_clrsetreg(&cru->clksel_con[con_id], 432 EMMC_PLL_MASK | EMMC_DIV_MASK, 433 EMMC_SEL_GPLL << EMMC_PLL_SHIFT | 434 (src_clk_div - 1) << EMMC_DIV_SHIFT); 435 } 436 rk_clrsetreg(&cru->clksel_con[con_id +1], EMMC_CLK_SEL_MASK, 437 EMMC_CLK_SEL_EMMC); 438 439 return px30_mmc_get_clk(priv, clk_id); 440 } 441 442 static ulong px30_pwm_get_clk(struct px30_clk_priv *priv, ulong clk_id) 443 { 444 struct px30_cru *cru = priv->cru; 445 u32 div, con; 446 447 switch (clk_id) { 448 case SCLK_PWM0: 449 con = readl(&cru->clksel_con[52]); 450 div = con >> CLK_PWM0_DIV_CON_SHIFT & CLK_PWM_DIV_CON_MASK; 451 break; 452 case SCLK_PWM1: 453 con = readl(&cru->clksel_con[52]); 454 div = con >> CLK_PWM1_DIV_CON_SHIFT & CLK_PWM_DIV_CON_MASK; 455 break; 456 default: 457 printf("do not support this pwm bus\n"); 458 return -EINVAL; 459 } 460 461 return DIV_TO_RATE(priv->gpll_hz, div); 462 } 463 464 static ulong px30_pwm_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz) 465 { 466 struct px30_cru *cru = priv->cru; 467 int src_clk_div; 468 469 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 470 assert(src_clk_div - 1 < 127); 471 472 switch (clk_id) { 473 case SCLK_PWM0: 474 rk_clrsetreg(&cru->clksel_con[52], 475 CLK_PWM_DIV_CON_MASK << CLK_PWM0_DIV_CON_SHIFT | 476 CLK_PWM_PLL_SEL_MASK << CLK_PWM0_PLL_SEL_SHIFT, 477 (src_clk_div - 1) << CLK_PWM0_DIV_CON_SHIFT | 478 CLK_PWM_PLL_SEL_GPLL << CLK_PWM0_PLL_SEL_SHIFT); 479 break; 480 case SCLK_PWM1: 481 rk_clrsetreg(&cru->clksel_con[52], 482 CLK_PWM_DIV_CON_MASK << CLK_PWM1_DIV_CON_SHIFT | 483 CLK_PWM_PLL_SEL_MASK << CLK_PWM1_PLL_SEL_SHIFT, 484 (src_clk_div - 1) << CLK_PWM1_DIV_CON_SHIFT | 485 CLK_PWM_PLL_SEL_GPLL << CLK_PWM1_PLL_SEL_SHIFT); 486 break; 487 default: 488 printf("do not support this pwm bus\n"); 489 return -EINVAL; 490 } 491 492 return px30_pwm_get_clk(priv, clk_id); 493 } 494 495 static ulong px30_saradc_get_clk(struct px30_clk_priv *priv) 496 { 497 struct px30_cru *cru = priv->cru; 498 u32 div, con; 499 500 con = readl(&cru->clksel_con[55]); 501 div = con >> CLK_SARADC_DIV_CON_SHIFT & CLK_SARADC_DIV_CON_MASK; 502 503 return DIV_TO_RATE(OSC_HZ, div); 504 } 505 506 static ulong px30_saradc_set_clk(struct px30_clk_priv *priv, uint hz) 507 { 508 struct px30_cru *cru = priv->cru; 509 int src_clk_div; 510 511 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz); 512 assert(src_clk_div - 1 < 2047); 513 514 rk_clrsetreg(&cru->clksel_con[55], 515 CLK_SARADC_DIV_CON_MASK, 516 (src_clk_div - 1) << CLK_SARADC_DIV_CON_SHIFT); 517 518 return px30_saradc_get_clk(priv); 519 } 520 521 static ulong px30_spi_get_clk(struct px30_clk_priv *priv, ulong clk_id) 522 { 523 struct px30_cru *cru = priv->cru; 524 u32 div, con; 525 526 switch (clk_id) { 527 case SCLK_SPI0: 528 con = readl(&cru->clksel_con[53]); 529 div = con >> CLK_SPI0_DIV_CON_SHIFT & CLK_SPI_DIV_CON_MASK; 530 break; 531 case SCLK_SPI1: 532 con = readl(&cru->clksel_con[53]); 533 div = con >> CLK_SPI1_DIV_CON_SHIFT & CLK_SPI_DIV_CON_MASK; 534 break; 535 default: 536 printf("do not support this pwm bus\n"); 537 return -EINVAL; 538 } 539 540 return DIV_TO_RATE(priv->gpll_hz, div); 541 } 542 543 static ulong px30_spi_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz) 544 { 545 struct px30_cru *cru = priv->cru; 546 int src_clk_div; 547 548 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 549 assert(src_clk_div - 1 < 127); 550 551 switch (clk_id) { 552 case SCLK_SPI0: 553 rk_clrsetreg(&cru->clksel_con[53], 554 CLK_SPI_DIV_CON_MASK << CLK_SPI0_DIV_CON_SHIFT | 555 CLK_SPI_PLL_SEL_MASK << CLK_SPI0_PLL_SEL_SHIFT, 556 (src_clk_div - 1) << CLK_SPI0_DIV_CON_SHIFT | 557 CLK_SPI_PLL_SEL_GPLL << CLK_SPI0_PLL_SEL_SHIFT); 558 break; 559 case SCLK_SPI1: 560 rk_clrsetreg(&cru->clksel_con[53], 561 CLK_SPI_DIV_CON_MASK << CLK_SPI1_DIV_CON_SHIFT | 562 CLK_SPI_PLL_SEL_MASK << CLK_SPI1_PLL_SEL_SHIFT, 563 (src_clk_div - 1) << CLK_SPI1_DIV_CON_SHIFT | 564 CLK_SPI_PLL_SEL_GPLL << CLK_SPI1_PLL_SEL_SHIFT); 565 break; 566 default: 567 printf("do not support this pwm bus\n"); 568 return -EINVAL; 569 } 570 571 return px30_spi_get_clk(priv, clk_id); 572 } 573 574 static ulong px30_vop_get_clk(struct px30_clk_priv *priv, ulong clk_id) 575 { 576 struct px30_cru *cru = priv->cru; 577 u32 div, con, parent; 578 579 switch (clk_id) { 580 case ACLK_VOPB: 581 con = readl(&cru->clksel_con[3]); 582 div = con & ACLK_VO_DIV_MASK; 583 parent = priv->gpll_hz; 584 break; 585 case DCLK_VOPB: 586 con = readl(&cru->clksel_con[5]); 587 div = con & DCLK_VOPB_DIV_MASK; 588 parent = rkclk_pll_get_rate(&cru->pll[CPLL], &cru->mode, CPLL); 589 break; 590 default: 591 return -ENOENT; 592 } 593 594 return DIV_TO_RATE(parent, div); 595 } 596 597 static ulong px30_vop_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz) 598 { 599 struct px30_cru *cru = priv->cru; 600 int src_clk_div; 601 602 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 603 assert(src_clk_div - 1 < 31); 604 605 switch (clk_id) { 606 case ACLK_VOPB: 607 rk_clrsetreg(&cru->clksel_con[3], 608 ACLK_VO_PLL_MASK | ACLK_VO_DIV_MASK, 609 ACLK_VO_SEL_GPLL << ACLK_VO_PLL_SHIFT | 610 (src_clk_div - 1) << ACLK_VO_DIV_SHIFT); 611 break; 612 case DCLK_VOPB: 613 /* 614 * vopb dclk source from cpll, and equals to 615 * cpll(means div == 1) 616 */ 617 rkclk_set_pll(&cru->pll[CPLL], &cru->mode, CPLL, hz); 618 619 rk_clrsetreg(&cru->clksel_con[5], 620 DCLK_VOPB_SEL_MASK | DCLK_VOPB_PLL_SEL_MASK | 621 DCLK_VOPB_DIV_MASK, 622 DCLK_VOPB_SEL_DIVOUT << DCLK_VOPB_SEL_SHIFT | 623 DCLK_VOPB_PLL_SEL_CPLL << DCLK_VOPB_PLL_SEL_SHIFT | 624 (1 - 1) << DCLK_VOPB_DIV_SHIFT); 625 break; 626 default: 627 printf("do not support this vop freq\n"); 628 return -EINVAL; 629 } 630 631 return px30_vop_get_clk(priv, clk_id); 632 } 633 634 static ulong px30_bus_get_clk(struct px30_clk_priv *priv, ulong clk_id) 635 { 636 struct px30_cru *cru = priv->cru; 637 u32 div, con, parent; 638 639 switch (clk_id) { 640 case ACLK_BUS_PRE: 641 con = readl(&cru->clksel_con[23]); 642 div = (con & BUS_ACLK_DIV_MASK) >> BUS_ACLK_DIV_SHIFT; 643 parent = priv->gpll_hz; 644 break; 645 case HCLK_BUS_PRE: 646 con = readl(&cru->clksel_con[24]); 647 div = (con & BUS_HCLK_DIV_MASK) >> BUS_HCLK_DIV_SHIFT; 648 parent = priv->gpll_hz; 649 break; 650 case PCLK_BUS_PRE: 651 parent = px30_bus_get_clk(priv, ACLK_BUS_PRE); 652 con = readl(&cru->clksel_con[24]); 653 div = (con & BUS_PCLK_DIV_MASK) >> BUS_PCLK_DIV_SHIFT; 654 break; 655 default: 656 return -ENOENT; 657 } 658 659 return DIV_TO_RATE(parent, div); 660 } 661 662 static ulong px30_bus_set_clk(struct px30_clk_priv *priv, ulong clk_id, 663 ulong hz) 664 { 665 struct px30_cru *cru = priv->cru; 666 int src_clk_div; 667 668 /* 669 * select gpll as pd_bus bus clock source and 670 * set up dependent divisors for PCLK/HCLK and ACLK clocks. 671 */ 672 switch (clk_id) { 673 case ACLK_BUS_PRE: 674 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 675 assert(src_clk_div - 1 < 31); 676 rk_clrsetreg(&cru->clksel_con[23], 677 BUS_PLL_SEL_MASK | BUS_ACLK_DIV_MASK, 678 BUS_PLL_SEL_GPLL << BUS_PLL_SEL_SHIFT | 679 (src_clk_div - 1) << BUS_ACLK_DIV_SHIFT); 680 break; 681 case HCLK_BUS_PRE: 682 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 683 assert(src_clk_div - 1 < 31); 684 rk_clrsetreg(&cru->clksel_con[24], 685 BUS_PLL_SEL_MASK | BUS_HCLK_DIV_MASK, 686 BUS_PLL_SEL_GPLL << BUS_PLL_SEL_SHIFT | 687 (src_clk_div - 1) << BUS_HCLK_DIV_SHIFT); 688 break; 689 case PCLK_BUS_PRE: 690 src_clk_div = 691 DIV_ROUND_UP(px30_bus_get_clk(priv, ACLK_BUS_PRE), hz); 692 assert(src_clk_div - 1 < 3); 693 rk_clrsetreg(&cru->clksel_con[24], 694 BUS_PCLK_DIV_MASK, 695 (src_clk_div - 1) << BUS_PCLK_DIV_SHIFT); 696 break; 697 default: 698 printf("do not support this bus freq\n"); 699 return -EINVAL; 700 } 701 702 return px30_bus_get_clk(priv, clk_id); 703 } 704 705 static ulong px30_peri_get_clk(struct px30_clk_priv *priv, ulong clk_id) 706 { 707 struct px30_cru *cru = priv->cru; 708 u32 div, con, parent; 709 710 switch (clk_id) { 711 case ACLK_PERI_PRE: 712 con = readl(&cru->clksel_con[14]); 713 div = (con & PERI_ACLK_DIV_MASK) >> PERI_ACLK_DIV_SHIFT; 714 parent = priv->gpll_hz; 715 break; 716 case HCLK_PERI_PRE: 717 con = readl(&cru->clksel_con[14]); 718 div = (con & PERI_HCLK_DIV_MASK) >> PERI_HCLK_DIV_SHIFT; 719 parent = priv->gpll_hz; 720 break; 721 default: 722 return -ENOENT; 723 } 724 725 return DIV_TO_RATE(parent, div); 726 } 727 728 static ulong px30_peri_set_clk(struct px30_clk_priv *priv, ulong clk_id, 729 ulong hz) 730 { 731 struct px30_cru *cru = priv->cru; 732 int src_clk_div; 733 734 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 735 assert(src_clk_div - 1 < 31); 736 737 /* 738 * select gpll as pd_peri bus clock source and 739 * set up dependent divisors for HCLK and ACLK clocks. 740 */ 741 switch (clk_id) { 742 case ACLK_PERI_PRE: 743 rk_clrsetreg(&cru->clksel_con[14], 744 PERI_PLL_SEL_MASK | PERI_ACLK_DIV_MASK, 745 PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT | 746 (src_clk_div - 1) << PERI_ACLK_DIV_SHIFT); 747 break; 748 case HCLK_PERI_PRE: 749 rk_clrsetreg(&cru->clksel_con[14], 750 PERI_PLL_SEL_MASK | PERI_HCLK_DIV_MASK, 751 PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT | 752 (src_clk_div - 1) << PERI_HCLK_DIV_SHIFT); 753 break; 754 default: 755 printf("do not support this peri freq\n"); 756 return -EINVAL; 757 } 758 759 return px30_peri_get_clk(priv, clk_id); 760 } 761 762 static int px30_clk_get_gpll_rate(ulong *rate) 763 { 764 struct udevice *pmucru_dev; 765 struct px30_pmuclk_priv *priv; 766 struct px30_pmucru *pmucru; 767 int ret; 768 769 ret = uclass_get_device_by_driver(UCLASS_CLK, 770 DM_GET_DRIVER(rockchip_px30_pmucru), 771 &pmucru_dev); 772 if (ret) { 773 printf("%s: could not find pmucru device\n", __func__); 774 return ret; 775 } 776 priv = dev_get_priv(pmucru_dev); 777 pmucru = priv->pmucru; 778 *rate = rkclk_pll_get_rate(&pmucru->pll, &pmucru->pmu_mode, GPLL); 779 780 return 0; 781 } 782 783 static ulong px30_clk_get_pll_rate(struct px30_clk_priv *priv, 784 enum px30_pll_id pll_id) 785 { 786 struct px30_cru *cru = priv->cru; 787 788 return rkclk_pll_get_rate(&cru->pll[pll_id], &cru->mode, pll_id); 789 } 790 791 static ulong px30_clk_get_rate(struct clk *clk) 792 { 793 struct px30_clk_priv *priv = dev_get_priv(clk->dev); 794 ulong rate = 0; 795 int ret; 796 797 if (!priv->gpll_hz) { 798 ret = px30_clk_get_gpll_rate(&priv->gpll_hz); 799 if (ret) { 800 printf("%s failed to get gpll rate\n", __func__); 801 return ret; 802 } 803 debug("%s gpll=%lu\n", __func__, priv->gpll_hz); 804 } 805 806 debug("%s %ld\n", __func__, clk->id); 807 switch (clk->id) { 808 case PLL_APLL: 809 rate = px30_clk_get_pll_rate(priv, APLL); 810 break; 811 case PLL_DPLL: 812 rate = px30_clk_get_pll_rate(priv, DPLL); 813 break; 814 case PLL_CPLL: 815 rate = px30_clk_get_pll_rate(priv, CPLL); 816 break; 817 case PLL_NPLL: 818 rate = px30_clk_get_pll_rate(priv, NPLL); 819 break; 820 case HCLK_SDMMC: 821 case HCLK_EMMC: 822 case SCLK_SDMMC: 823 case SCLK_EMMC: 824 case SCLK_EMMC_SAMPLE: 825 rate = px30_mmc_get_clk(priv, clk->id); 826 break; 827 case SCLK_I2C0: 828 case SCLK_I2C1: 829 case SCLK_I2C2: 830 case SCLK_I2C3: 831 rate = px30_i2c_get_clk(priv, clk->id); 832 break; 833 case SCLK_PWM0: 834 case SCLK_PWM1: 835 rate = px30_pwm_get_clk(priv, clk->id); 836 break; 837 case SCLK_SARADC: 838 rate = px30_saradc_get_clk(priv); 839 break; 840 case SCLK_SPI0: 841 case SCLK_SPI1: 842 rate = px30_spi_get_clk(priv, clk->id); 843 break; 844 case ACLK_VOPB: 845 case DCLK_VOPB: 846 rate = px30_vop_get_clk(priv, clk->id); 847 break; 848 case ACLK_BUS_PRE: 849 case HCLK_BUS_PRE: 850 case PCLK_BUS_PRE: 851 rate = px30_bus_get_clk(priv, clk->id); 852 break; 853 case ACLK_PERI_PRE: 854 case HCLK_PERI_PRE: 855 rate = px30_peri_get_clk(priv, clk->id); 856 break; 857 default: 858 return -ENOENT; 859 } 860 861 return rate; 862 } 863 864 static ulong px30_clk_set_rate(struct clk *clk, ulong rate) 865 { 866 struct px30_clk_priv *priv = dev_get_priv(clk->dev); 867 ulong ret = 0; 868 869 if (!priv->gpll_hz) { 870 ret = px30_clk_get_gpll_rate(&priv->gpll_hz); 871 if (ret) { 872 printf("%s failed to get gpll rate\n", __func__); 873 return ret; 874 } 875 debug("%s gpll=%lu\n", __func__, priv->gpll_hz); 876 } 877 878 debug("%s %ld %ld\n", __func__, clk->id, rate); 879 switch (clk->id) { 880 case 0 ... 15: 881 return 0; 882 case HCLK_SDMMC: 883 case HCLK_EMMC: 884 case SCLK_SDMMC: 885 case SCLK_EMMC: 886 ret = px30_mmc_set_clk(priv, clk->id, rate); 887 break; 888 case SCLK_I2C0: 889 case SCLK_I2C1: 890 case SCLK_I2C2: 891 case SCLK_I2C3: 892 ret = px30_i2c_set_clk(priv, clk->id, rate); 893 break; 894 case SCLK_PWM0: 895 case SCLK_PWM1: 896 ret = px30_pwm_set_clk(priv, clk->id, rate); 897 break; 898 case SCLK_SARADC: 899 ret = px30_saradc_set_clk(priv, rate); 900 break; 901 case SCLK_SPI0: 902 case SCLK_SPI1: 903 ret = px30_spi_set_clk(priv, clk->id, rate); 904 break; 905 case ACLK_VOPB: 906 case DCLK_VOPB: 907 ret = px30_vop_set_clk(priv, clk->id, rate); 908 break; 909 case ACLK_BUS_PRE: 910 case HCLK_BUS_PRE: 911 case PCLK_BUS_PRE: 912 ret = px30_bus_set_clk(priv, clk->id, rate); 913 break; 914 case ACLK_PERI_PRE: 915 case HCLK_PERI_PRE: 916 ret = px30_peri_set_clk(priv, clk->id, rate); 917 break; 918 default: 919 return -ENOENT; 920 } 921 922 return ret; 923 } 924 925 #define ROCKCHIP_MMC_DELAY_SEL BIT(10) 926 #define ROCKCHIP_MMC_DEGREE_MASK 0x3 927 #define ROCKCHIP_MMC_DELAYNUM_OFFSET 2 928 #define ROCKCHIP_MMC_DELAYNUM_MASK (0xff << ROCKCHIP_MMC_DELAYNUM_OFFSET) 929 930 #define PSECS_PER_SEC 1000000000000LL 931 /* 932 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to 933 * simplify calculations. So 45degs could be anywhere between 33deg and 57.8deg. 934 */ 935 #define ROCKCHIP_MMC_DELAY_ELEMENT_PSEC 60 936 937 int rockchip_mmc_get_phase(struct clk *clk) 938 { 939 struct px30_clk_priv *priv = dev_get_priv(clk->dev); 940 struct px30_cru *cru = priv->cru; 941 u32 raw_value, delay_num; 942 u16 degrees = 0; 943 ulong rate; 944 945 rate = px30_clk_get_rate(clk); 946 947 if (rate < 0) 948 return rate; 949 950 if (clk->id == SCLK_EMMC_SAMPLE) 951 raw_value = readl(&cru->emmc_con[1]); 952 else 953 raw_value = readl(&cru->sdmmc_con[1]); 954 955 raw_value >>= 1; 956 degrees = (raw_value & ROCKCHIP_MMC_DEGREE_MASK) * 90; 957 958 if (raw_value & ROCKCHIP_MMC_DELAY_SEL) { 959 /* degrees/delaynum * 10000 */ 960 unsigned long factor = (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10) * 961 36 * (rate / 1000000); 962 963 delay_num = (raw_value & ROCKCHIP_MMC_DELAYNUM_MASK); 964 delay_num >>= ROCKCHIP_MMC_DELAYNUM_OFFSET; 965 degrees += DIV_ROUND_CLOSEST(delay_num * factor, 10000); 966 } 967 968 return degrees % 360; 969 } 970 971 int rockchip_mmc_set_phase(struct clk *clk, u32 degrees) 972 { 973 struct px30_clk_priv *priv = dev_get_priv(clk->dev); 974 struct px30_cru *cru = priv->cru; 975 u8 nineties, remainder, delay_num; 976 u32 raw_value, delay; 977 ulong rate; 978 979 rate = px30_clk_get_rate(clk); 980 981 if (rate < 0) 982 return rate; 983 984 nineties = degrees / 90; 985 remainder = (degrees % 90); 986 987 /* 988 * Convert to delay; do a little extra work to make sure we 989 * don't overflow 32-bit / 64-bit numbers. 990 */ 991 delay = 10000000; /* PSECS_PER_SEC / 10000 / 10 */ 992 delay *= remainder; 993 delay = DIV_ROUND_CLOSEST(delay, (rate / 1000) * 36 * 994 (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10)); 995 996 delay_num = (u8)min_t(u32, delay, 255); 997 998 raw_value = delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0; 999 raw_value |= delay_num << ROCKCHIP_MMC_DELAYNUM_OFFSET; 1000 raw_value |= nineties; 1001 1002 raw_value <<= 1; 1003 if (clk->id == SCLK_EMMC_SAMPLE) 1004 writel(raw_value | 0xffff0000, &cru->emmc_con[1]); 1005 else 1006 writel(raw_value | 0xffff0000, &cru->sdmmc_con[1]); 1007 1008 debug("mmc set_phase(%d) delay_nums=%u reg=%#x actual_degrees=%d\n", 1009 degrees, delay_num, raw_value, rockchip_mmc_get_phase(clk)); 1010 1011 return 0; 1012 } 1013 1014 static int px30_clk_get_phase(struct clk *clk) 1015 { 1016 int ret; 1017 debug("%s %ld\n", __func__, clk->id); 1018 switch (clk->id) { 1019 case SCLK_EMMC_SAMPLE: 1020 case SCLK_SDMMC_SAMPLE: 1021 ret = rockchip_mmc_get_phase(clk); 1022 break; 1023 default: 1024 return -ENOENT; 1025 } 1026 1027 return ret; 1028 } 1029 1030 static int px30_clk_set_phase(struct clk *clk, int degrees) 1031 { 1032 int ret; 1033 1034 debug("%s %ld\n", __func__, clk->id); 1035 switch (clk->id) { 1036 case SCLK_EMMC_SAMPLE: 1037 case SCLK_SDMMC_SAMPLE: 1038 ret = rockchip_mmc_set_phase(clk, degrees); 1039 break; 1040 default: 1041 return -ENOENT; 1042 } 1043 1044 return ret; 1045 } 1046 1047 static struct clk_ops px30_clk_ops = { 1048 .get_rate = px30_clk_get_rate, 1049 .set_rate = px30_clk_set_rate, 1050 .get_phase = px30_clk_get_phase, 1051 .set_phase = px30_clk_set_phase, 1052 }; 1053 1054 static int px30_clk_probe(struct udevice *dev) 1055 { 1056 struct px30_clk_priv *priv = dev_get_priv(dev); 1057 struct px30_cru *cru = priv->cru; 1058 u32 aclk_div, pclk_div; 1059 1060 /* init pll */ 1061 rkclk_set_pll(&cru->pll[APLL], &cru->mode, APLL, APLL_HZ); 1062 /* 1063 * select apll as cpu/core clock pll source and 1064 * set up dependent divisors for PERI and ACLK clocks. 1065 * core hz : apll = 1:1 1066 */ 1067 aclk_div = APLL_HZ / CORE_ACLK_HZ - 1; 1068 pclk_div = APLL_HZ / CORE_DBG_HZ - 1; 1069 1070 rk_clrsetreg(&cru->clksel_con[0], 1071 CORE_ACLK_DIV_MASK | CORE_DBG_DIV_MASK | 1072 CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK, 1073 aclk_div << CORE_ACLK_DIV_SHIFT | 1074 pclk_div << CORE_DBG_DIV_SHIFT | 1075 CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT | 1076 0 << CORE_DIV_CON_SHIFT); 1077 1078 return 0; 1079 } 1080 1081 static int px30_clk_ofdata_to_platdata(struct udevice *dev) 1082 { 1083 struct px30_clk_priv *priv = dev_get_priv(dev); 1084 1085 priv->cru = dev_read_addr_ptr(dev); 1086 1087 return 0; 1088 } 1089 1090 static int px30_clk_bind(struct udevice *dev) 1091 { 1092 int ret; 1093 struct udevice *sys_child, *sf_child; 1094 struct sysreset_reg *priv; 1095 struct softreset_reg *sf_priv; 1096 1097 /* The reset driver does not have a device node, so bind it here */ 1098 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", 1099 &sys_child); 1100 if (ret) { 1101 debug("Warning: No sysreset driver: ret=%d\n", ret); 1102 } else { 1103 priv = malloc(sizeof(struct sysreset_reg)); 1104 priv->glb_srst_fst_value = offsetof(struct px30_cru, 1105 glb_srst_fst); 1106 priv->glb_srst_snd_value = offsetof(struct px30_cru, 1107 glb_srst_snd); 1108 sys_child->priv = priv; 1109 } 1110 1111 ret = device_bind_driver_to_node(dev, "rockchip_reset", "reset", 1112 dev_ofnode(dev), &sf_child); 1113 if (ret) { 1114 debug("Warning: No rockchip reset driver: ret=%d\n", ret); 1115 } else { 1116 sf_priv = malloc(sizeof(struct softreset_reg)); 1117 sf_priv->sf_reset_offset = offsetof(struct px30_cru, 1118 softrst_con[0]); 1119 sf_priv->sf_reset_num = 12; 1120 sf_child->priv = sf_priv; 1121 } 1122 1123 return 0; 1124 } 1125 1126 static const struct udevice_id px30_clk_ids[] = { 1127 { .compatible = "rockchip,px30-cru" }, 1128 { } 1129 }; 1130 1131 U_BOOT_DRIVER(rockchip_px30_cru) = { 1132 .name = "rockchip_px30_cru", 1133 .id = UCLASS_CLK, 1134 .of_match = px30_clk_ids, 1135 .priv_auto_alloc_size = sizeof(struct px30_clk_priv), 1136 .ofdata_to_platdata = px30_clk_ofdata_to_platdata, 1137 .ops = &px30_clk_ops, 1138 .bind = px30_clk_bind, 1139 .probe = px30_clk_probe, 1140 }; 1141 1142 static ulong px30_pclk_pmu_get_pmuclk(struct px30_pmuclk_priv *priv) 1143 { 1144 struct px30_pmucru *pmucru = priv->pmucru; 1145 u32 div, con; 1146 1147 con = readl(&pmucru->pmu_clksel_con[0]); 1148 div = (con & CLK_PMU_PCLK_DIV_MASK) >> CLK_PMU_PCLK_DIV_SHIFT; 1149 1150 return DIV_TO_RATE(priv->gpll_hz, div); 1151 } 1152 1153 static ulong px30_pclk_pmu_set_pmuclk(struct px30_pmuclk_priv *priv, ulong hz) 1154 { 1155 struct px30_pmucru *pmucru = priv->pmucru; 1156 int src_clk_div; 1157 1158 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 1159 assert(src_clk_div - 1 < 31); 1160 1161 rk_clrsetreg(&pmucru->pmu_clksel_con[0], 1162 CLK_PMU_PCLK_DIV_MASK, 1163 (src_clk_div - 1) << CLK_PMU_PCLK_DIV_SHIFT); 1164 1165 return px30_pclk_pmu_get_pmuclk(priv); 1166 } 1167 1168 static ulong px30_gpll_get_pmuclk(struct px30_pmuclk_priv *priv) 1169 { 1170 struct px30_pmucru *pmucru = priv->pmucru; 1171 1172 return rkclk_pll_get_rate(&pmucru->pll, &pmucru->pmu_mode, GPLL); 1173 } 1174 1175 static ulong px30_gpll_set_pmuclk(struct px30_pmuclk_priv *priv, ulong hz) 1176 { 1177 struct udevice *cru_dev; 1178 struct px30_clk_priv *cru_priv; 1179 struct px30_pmucru *pmucru = priv->pmucru; 1180 u32 div; 1181 ulong emmc_rate, sdmmc_rate, nandc_rate; 1182 int ret; 1183 1184 priv->gpll_hz = px30_gpll_get_pmuclk(priv); 1185 1186 ret = uclass_get_device_by_name(UCLASS_CLK, 1187 "clock-controller@ff2b0000", 1188 &cru_dev); 1189 if (ret) { 1190 printf("%s failed to get cru device\n", __func__); 1191 return ret; 1192 } 1193 cru_priv = dev_get_priv(cru_dev); 1194 cru_priv->gpll_hz = priv->gpll_hz; 1195 1196 div = DIV_ROUND_UP(hz, priv->gpll_hz); 1197 1198 /* 1199 * avoid bus and peri clock rate too large, reduce rate first. 1200 * they will be assigned by clk_set_defaults. 1201 */ 1202 px30_bus_set_clk(cru_priv, ACLK_BUS_PRE, 1203 px30_bus_get_clk(cru_priv, ACLK_BUS_PRE) / div); 1204 px30_bus_set_clk(cru_priv, HCLK_BUS_PRE, 1205 px30_bus_get_clk(cru_priv, HCLK_BUS_PRE) / div); 1206 px30_bus_set_clk(cru_priv, PCLK_BUS_PRE, 1207 px30_bus_get_clk(cru_priv, PCLK_BUS_PRE) / div); 1208 px30_peri_set_clk(cru_priv, ACLK_PERI_PRE, 1209 px30_bus_get_clk(cru_priv, ACLK_PERI_PRE) / div); 1210 px30_peri_set_clk(cru_priv, HCLK_PERI_PRE, 1211 px30_bus_get_clk(cru_priv, HCLK_PERI_PRE) / div); 1212 px30_pclk_pmu_set_pmuclk(priv, px30_pclk_pmu_get_pmuclk(priv) / div); 1213 1214 /* 1215 * save emmc, sdmmc and nandc clock rate, 1216 * nandc clock rate should less than or equal to 150Mhz. 1217 */ 1218 emmc_rate = px30_mmc_get_clk(cru_priv, SCLK_EMMC); 1219 sdmmc_rate = px30_mmc_get_clk(cru_priv, SCLK_SDMMC); 1220 nandc_rate = px30_nandc_get_clk(cru_priv); 1221 debug("%s emmc=%lu, sdmmc=%lu, nandc=%lu\n", __func__, emmc_rate, 1222 sdmmc_rate, nandc_rate); 1223 1224 rkclk_set_pll(&pmucru->pll, &pmucru->pmu_mode, GPLL, hz); 1225 priv->gpll_hz = px30_gpll_get_pmuclk(priv); 1226 cru_priv->gpll_hz = priv->gpll_hz; 1227 1228 /* restore emmc, sdmmc and nandc clock rate */ 1229 px30_mmc_set_clk(cru_priv, SCLK_EMMC, emmc_rate); 1230 px30_mmc_set_clk(cru_priv, SCLK_SDMMC, sdmmc_rate); 1231 px30_nandc_set_clk(cru_priv, nandc_rate); 1232 1233 return priv->gpll_hz; 1234 } 1235 1236 static ulong px30_pmuclk_get_rate(struct clk *clk) 1237 { 1238 struct px30_pmuclk_priv *priv = dev_get_priv(clk->dev); 1239 ulong rate = 0; 1240 1241 debug("%s %ld\n", __func__, clk->id); 1242 switch (clk->id) { 1243 case PLL_GPLL: 1244 rate = px30_gpll_get_pmuclk(priv); 1245 break; 1246 case PCLK_PMU_PRE: 1247 rate = px30_pclk_pmu_get_pmuclk(priv); 1248 break; 1249 default: 1250 return -ENOENT; 1251 } 1252 1253 return rate; 1254 } 1255 1256 static ulong px30_pmuclk_set_rate(struct clk *clk, ulong rate) 1257 { 1258 struct px30_pmuclk_priv *priv = dev_get_priv(clk->dev); 1259 ulong ret = 0; 1260 1261 debug("%s %ld %ld\n", __func__, clk->id, rate); 1262 switch (clk->id) { 1263 case PLL_GPLL: 1264 ret = px30_gpll_set_pmuclk(priv, rate); 1265 break; 1266 case PCLK_PMU_PRE: 1267 ret = px30_pclk_pmu_set_pmuclk(priv, rate); 1268 break; 1269 default: 1270 return -ENOENT; 1271 } 1272 1273 return ret; 1274 } 1275 1276 static struct clk_ops px30_pmuclk_ops = { 1277 .get_rate = px30_pmuclk_get_rate, 1278 .set_rate = px30_pmuclk_set_rate, 1279 }; 1280 1281 static int px30_pmuclk_probe(struct udevice *dev) 1282 { 1283 return 0; 1284 } 1285 1286 static int px30_pmuclk_ofdata_to_platdata(struct udevice *dev) 1287 { 1288 struct px30_pmuclk_priv *priv = dev_get_priv(dev); 1289 1290 priv->pmucru = dev_read_addr_ptr(dev); 1291 1292 return 0; 1293 } 1294 1295 static const struct udevice_id px30_pmuclk_ids[] = { 1296 { .compatible = "rockchip,px30-pmucru" }, 1297 { } 1298 }; 1299 1300 U_BOOT_DRIVER(rockchip_px30_pmucru) = { 1301 .name = "rockchip_px30_pmucru", 1302 .id = UCLASS_CLK, 1303 .of_match = px30_pmuclk_ids, 1304 .priv_auto_alloc_size = sizeof(struct px30_pmuclk_priv), 1305 .ofdata_to_platdata = px30_pmuclk_ofdata_to_platdata, 1306 .ops = &px30_pmuclk_ops, 1307 .probe = px30_pmuclk_probe, 1308 }; 1309 1310 /** 1311 * soc_clk_dump() - Print clock frequencies 1312 * Returns zero on success 1313 * 1314 * Implementation for the clk dump command. 1315 */ 1316 int soc_clk_dump(void) 1317 { 1318 struct udevice *cru_dev, *pmucru_dev; 1319 const struct px30_clk_info *clk_dump; 1320 struct clk clk; 1321 unsigned long clk_count = ARRAY_SIZE(clks_dump); 1322 unsigned long rate; 1323 int i, ret; 1324 1325 ret = uclass_get_device_by_driver(UCLASS_CLK, 1326 DM_GET_DRIVER(rockchip_px30_cru), 1327 &cru_dev); 1328 if (ret) { 1329 printf("%s failed to get cru device\n", __func__); 1330 return ret; 1331 } 1332 1333 ret = uclass_get_device_by_driver(UCLASS_CLK, 1334 DM_GET_DRIVER(rockchip_px30_pmucru), 1335 &pmucru_dev); 1336 if (ret) { 1337 printf("%s failed to get pmucru device\n", __func__); 1338 return ret; 1339 } 1340 1341 printf("CLK:"); 1342 for (i = 0; i < clk_count; i++) { 1343 clk_dump = &clks_dump[i]; 1344 if (clk_dump->name) { 1345 clk.id = clk_dump->id; 1346 if (clk_dump->is_cru) 1347 ret = clk_request(cru_dev, &clk); 1348 else 1349 ret = clk_request(pmucru_dev, &clk); 1350 if (ret < 0) 1351 return ret; 1352 1353 rate = clk_get_rate(&clk); 1354 clk_free(&clk); 1355 if (i == 0) { 1356 if (rate < 0) 1357 printf("%10s%20s\n", clk_dump->name, 1358 "unknown"); 1359 else 1360 printf("%10s%20lu Hz\n", clk_dump->name, 1361 rate); 1362 } else { 1363 if (rate < 0) 1364 printf("%14s%20s\n", clk_dump->name, 1365 "unknown"); 1366 else 1367 printf("%14s%20lu Hz\n", clk_dump->name, 1368 rate); 1369 } 1370 } 1371 } 1372 1373 return 0; 1374 } 1375