1/* 2 * SPDX-License-Identifier: GPL-2.0+ 3 */ 4 5#include <dt-bindings/gpio/gpio.h> 6#include <dt-bindings/interrupt-controller/irq.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/pinctrl/rockchip.h> 9#include <dt-bindings/clock/rk3288-cru.h> 10#include <dt-bindings/power-domain/rk3288.h> 11#include <dt-bindings/thermal/thermal.h> 12#include <dt-bindings/video/rk3288.h> 13#include "skeleton.dtsi" 14 15/ { 16 compatible = "rockchip,rk3288"; 17 18 interrupt-parent = <&gic>; 19 aliases { 20 gpio0 = &gpio0; 21 gpio1 = &gpio1; 22 gpio2 = &gpio2; 23 gpio3 = &gpio3; 24 gpio4 = &gpio4; 25 gpio5 = &gpio5; 26 gpio6 = &gpio6; 27 gpio7 = &gpio7; 28 gpio8 = &gpio8; 29 i2c0 = &i2c0; 30 i2c1 = &i2c1; 31 i2c2 = &i2c2; 32 i2c3 = &i2c3; 33 i2c4 = &i2c4; 34 i2c5 = &i2c5; 35 mmc0 = &emmc; 36 mmc1 = &sdmmc; 37 mmc2 = &sdio0; 38 mmc3 = &sdio1; 39 mshc0 = &emmc; 40 mshc1 = &sdmmc; 41 mshc2 = &sdio0; 42 mshc3 = &sdio1; 43 serial0 = &uart0; 44 serial1 = &uart1; 45 serial2 = &uart2; 46 serial3 = &uart3; 47 serial4 = &uart4; 48 spi0 = &spi0; 49 spi1 = &spi1; 50 spi2 = &spi2; 51 }; 52 53 cpus { 54 #address-cells = <1>; 55 #size-cells = <0>; 56 enable-method = "rockchip,rk3066-smp"; 57 rockchip,pmu = <&pmu>; 58 59 cpu0: cpu@500 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a12"; 62 reg = <0x500>; 63 operating-points = < 64 /* KHz uV */ 65 1800000 1400000 66 1704000 1350000 67 1608000 1300000 68 1512000 1250000 69 1416000 1200000 70 1200000 1100000 71 1008000 1050000 72 816000 1000000 73 696000 950000 74 600000 900000 75 408000 900000 76 216000 900000 77 126000 900000 78 >; 79 #cooling-cells = <2>; /* min followed by max */ 80 clock-latency = <40000>; 81 clocks = <&cru ARMCLK>; 82 resets = <&cru SRST_CORE0>; 83 }; 84 cpu@501 { 85 device_type = "cpu"; 86 compatible = "arm,cortex-a12"; 87 reg = <0x501>; 88 resets = <&cru SRST_CORE1>; 89 }; 90 cpu@502 { 91 device_type = "cpu"; 92 compatible = "arm,cortex-a12"; 93 reg = <0x502>; 94 resets = <&cru SRST_CORE2>; 95 }; 96 cpu@503 { 97 device_type = "cpu"; 98 compatible = "arm,cortex-a12"; 99 reg = <0x503>; 100 resets = <&cru SRST_CORE3>; 101 }; 102 }; 103 104 amba { 105 compatible = "arm,amba-bus"; 106 #address-cells = <1>; 107 #size-cells = <1>; 108 ranges; 109 110 dmac_peri: dma-controller@ff250000 { 111 compatible = "arm,pl330", "arm,primecell"; 112 broken-no-flushp; 113 reg = <0xff250000 0x4000>; 114 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 115 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 116 #dma-cells = <1>; 117 clocks = <&cru ACLK_DMAC2>; 118 clock-names = "apb_pclk"; 119 }; 120 121 dmac_bus_ns: dma-controller@ff600000 { 122 compatible = "arm,pl330", "arm,primecell"; 123 broken-no-flushp; 124 reg = <0xff600000 0x4000>; 125 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 126 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 127 #dma-cells = <1>; 128 clocks = <&cru ACLK_DMAC1>; 129 clock-names = "apb_pclk"; 130 status = "disabled"; 131 }; 132 133 dmac_bus_s: dma-controller@ffb20000 { 134 compatible = "arm,pl330", "arm,primecell"; 135 broken-no-flushp; 136 reg = <0xffb20000 0x4000>; 137 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 139 #dma-cells = <1>; 140 clocks = <&cru ACLK_DMAC1>; 141 clock-names = "apb_pclk"; 142 }; 143 }; 144 145 xin24m: oscillator { 146 compatible = "fixed-clock"; 147 clock-frequency = <24000000>; 148 clock-output-names = "xin24m"; 149 #clock-cells = <0>; 150 }; 151 152 timer { 153 arm,use-physical-timer; 154 compatible = "arm,armv7-timer"; 155 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 156 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 157 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 158 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 159 clock-frequency = <24000000>; 160 always-on; 161 }; 162 163 display_subsystem: display-subsystem { 164 compatible = "rockchip,display-subsystem"; 165 ports = <&vopl_out>, <&vopb_out>; 166 status = "disabled"; 167 168 route { 169 route_hdmi: route-hdmi { 170 status = "disabled"; 171 logo,uboot = "logo.bmp"; 172 logo,kernel = "logo_kernel.bmp"; 173 logo,mode = "center"; 174 charge_logo,mode = "center"; 175 connect = <&vopb_out_hdmi>; 176 }; 177 178 route_edp: route-edp { 179 status = "disabled"; 180 logo,uboot = "logo.bmp"; 181 logo,kernel = "logo_kernel.bmp"; 182 logo,mode = "center"; 183 charge_logo,mode = "center"; 184 connect = <&vopl_out_edp>; 185 }; 186 }; 187 }; 188 189 sdmmc: dwmmc@ff0c0000 { 190 compatible = "rockchip,rk3288-dw-mshc"; 191 max-frequency = <150000000>; 192 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 193 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 194 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 195 fifo-depth = <0x100>; 196 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 197 reg = <0xff0c0000 0x4000>; 198 status = "disabled"; 199 }; 200 201 sdio0: dwmmc@ff0d0000 { 202 compatible = "rockchip,rk3288-dw-mshc"; 203 max-frequency = <150000000>; 204 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, 205 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>; 206 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 207 fifo-depth = <0x100>; 208 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 209 reg = <0xff0d0000 0x4000>; 210 status = "disabled"; 211 }; 212 213 sdio1: dwmmc@ff0e0000 { 214 compatible = "rockchip,rk3288-dw-mshc"; 215 max-frequency = <150000000>; 216 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>, 217 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>; 218 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 219 fifo-depth = <0x100>; 220 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 221 reg = <0xff0e0000 0x4000>; 222 status = "disabled"; 223 }; 224 225 emmc: dwmmc@ff0f0000 { 226 compatible = "rockchip,rk3288-dw-mshc"; 227 max-frequency = <150000000>; 228 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 229 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 230 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 231 fifo-depth = <0x100>; 232 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 233 reg = <0xff0f0000 0x4000>; 234 status = "disabled"; 235 }; 236 237 saradc: saradc@ff100000 { 238 compatible = "rockchip,saradc"; 239 reg = <0xff100000 0x100>; 240 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 241 #io-channel-cells = <1>; 242 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 243 clock-names = "saradc", "apb_pclk"; 244 status = "disabled"; 245 }; 246 247 spi0: spi@ff110000 { 248 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; 249 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 250 clock-names = "spiclk", "apb_pclk"; 251 dmas = <&dmac_peri 11>, <&dmac_peri 12>; 252 dma-names = "tx", "rx"; 253 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 254 pinctrl-names = "default"; 255 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 256 reg = <0xff110000 0x1000>; 257 #address-cells = <1>; 258 #size-cells = <0>; 259 status = "disabled"; 260 }; 261 262 spi1: spi@ff120000 { 263 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; 264 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 265 clock-names = "spiclk", "apb_pclk"; 266 dmas = <&dmac_peri 13>, <&dmac_peri 14>; 267 dma-names = "tx", "rx"; 268 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 269 pinctrl-names = "default"; 270 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 271 reg = <0xff120000 0x1000>; 272 #address-cells = <1>; 273 #size-cells = <0>; 274 status = "disabled"; 275 }; 276 277 spi2: spi@ff130000 { 278 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; 279 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 280 clock-names = "spiclk", "apb_pclk"; 281 dmas = <&dmac_peri 15>, <&dmac_peri 16>; 282 dma-names = "tx", "rx"; 283 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 284 pinctrl-names = "default"; 285 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 286 reg = <0xff130000 0x1000>; 287 #address-cells = <1>; 288 #size-cells = <0>; 289 status = "disabled"; 290 }; 291 292 i2c1: i2c@ff140000 { 293 compatible = "rockchip,rk3288-i2c"; 294 reg = <0xff140000 0x1000>; 295 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 296 #address-cells = <1>; 297 #size-cells = <0>; 298 clock-names = "i2c"; 299 clocks = <&cru PCLK_I2C1>; 300 pinctrl-names = "default"; 301 pinctrl-0 = <&i2c1_xfer>; 302 status = "disabled"; 303 }; 304 305 i2c3: i2c@ff150000 { 306 compatible = "rockchip,rk3288-i2c"; 307 reg = <0xff150000 0x1000>; 308 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 309 #address-cells = <1>; 310 #size-cells = <0>; 311 clock-names = "i2c"; 312 clocks = <&cru PCLK_I2C3>; 313 pinctrl-names = "default"; 314 pinctrl-0 = <&i2c3_xfer>; 315 status = "disabled"; 316 }; 317 318 i2c4: i2c@ff160000 { 319 compatible = "rockchip,rk3288-i2c"; 320 reg = <0xff160000 0x1000>; 321 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 322 #address-cells = <1>; 323 #size-cells = <0>; 324 clock-names = "i2c"; 325 clocks = <&cru PCLK_I2C4>; 326 pinctrl-names = "default"; 327 pinctrl-0 = <&i2c4_xfer>; 328 status = "disabled"; 329 }; 330 331 i2c5: i2c@ff170000 { 332 compatible = "rockchip,rk3288-i2c"; 333 reg = <0xff170000 0x1000>; 334 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 335 #address-cells = <1>; 336 #size-cells = <0>; 337 clock-names = "i2c"; 338 clocks = <&cru PCLK_I2C5>; 339 pinctrl-names = "default"; 340 pinctrl-0 = <&i2c5_xfer>; 341 status = "disabled"; 342 }; 343 uart0: serial@ff180000 { 344 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 345 reg = <0xff180000 0x100>; 346 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 347 reg-shift = <2>; 348 reg-io-width = <4>; 349 clock-frequency = <24000000>; 350 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 351 clock-names = "baudclk", "apb_pclk"; 352 pinctrl-names = "default"; 353 pinctrl-0 = <&uart0_xfer>; 354 status = "disabled"; 355 }; 356 357 uart1: serial@ff190000 { 358 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 359 reg = <0xff190000 0x100>; 360 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 361 reg-shift = <2>; 362 reg-io-width = <4>; 363 clock-frequency = <24000000>; 364 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 365 clock-names = "baudclk", "apb_pclk"; 366 pinctrl-names = "default"; 367 pinctrl-0 = <&uart1_xfer>; 368 status = "disabled"; 369 }; 370 371 uart2: serial@ff690000 { 372 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 373 reg = <0xff690000 0x100>; 374 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 375 reg-shift = <2>; 376 reg-io-width = <4>; 377 clock-frequency = <24000000>; 378 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 379 clock-names = "baudclk", "apb_pclk"; 380 pinctrl-names = "default"; 381 pinctrl-0 = <&uart2_xfer>; 382 status = "disabled"; 383 }; 384 uart3: serial@ff1b0000 { 385 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 386 reg = <0xff1b0000 0x100>; 387 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 388 reg-shift = <2>; 389 reg-io-width = <4>; 390 clock-frequency = <24000000>; 391 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 392 clock-names = "baudclk", "apb_pclk"; 393 pinctrl-names = "default"; 394 pinctrl-0 = <&uart3_xfer>; 395 status = "disabled"; 396 }; 397 398 uart4: serial@ff1c0000 { 399 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 400 reg = <0xff1c0000 0x100>; 401 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 402 reg-shift = <2>; 403 reg-io-width = <4>; 404 clock-frequency = <24000000>; 405 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 406 clock-names = "baudclk", "apb_pclk"; 407 pinctrl-names = "default"; 408 pinctrl-0 = <&uart4_xfer>; 409 status = "disabled"; 410 }; 411 thermal: thermal-zones { 412 #include "rk3288-thermal.dtsi" 413 }; 414 415 tsadc: tsadc@ff280000 { 416 compatible = "rockchip,rk3288-tsadc"; 417 reg = <0xff280000 0x100>; 418 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 419 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 420 clock-names = "tsadc", "apb_pclk"; 421 resets = <&cru SRST_TSADC>; 422 reset-names = "tsadc-apb"; 423 pinctrl-names = "otp_out"; 424 pinctrl-0 = <&otp_out>; 425 #thermal-sensor-cells = <1>; 426 hw-shut-temp = <125000>; 427 status = "disabled"; 428 }; 429 430 gmac: ethernet@ff290000 { 431 compatible = "rockchip,rk3288-gmac"; 432 reg = <0xff290000 0x10000>; 433 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 434 interrupt-names = "macirq"; 435 rockchip,grf = <&grf>; 436 clocks = <&cru SCLK_MAC>, 437 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, 438 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>, 439 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; 440 clock-names = "stmmaceth", 441 "mac_clk_rx", "mac_clk_tx", 442 "clk_mac_ref", "clk_mac_refout", 443 "aclk_mac", "pclk_mac"; 444 }; 445 446 usb_host0_ehci: usb@ff500000 { 447 compatible = "generic-ehci"; 448 reg = <0xff500000 0x100>; 449 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 450 clocks = <&cru HCLK_USBHOST0>; 451 clock-names = "usbhost"; 452 phys = <&usbphy1>; 453 phy-names = "usb"; 454 status = "disabled"; 455 }; 456 457 /* NOTE: ohci@ff520000 doesn't actually work on hardware */ 458 459 usb_host1: usb@ff540000 { 460 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", 461 "snps,dwc2"; 462 reg = <0xff540000 0x40000>; 463 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 464 clocks = <&cru HCLK_USBHOST1>; 465 clock-names = "otg"; 466 phys = <&usbphy2>; 467 phy-names = "usb2-phy"; 468 status = "disabled"; 469 }; 470 471 usb_otg: usb@ff580000 { 472 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", 473 "snps,dwc2"; 474 reg = <0xff580000 0x40000>; 475 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 476 clocks = <&cru HCLK_OTG0>; 477 clock-names = "otg"; 478 dr_mode = "otg"; 479 phys = <&usbphy0>; 480 phy-names = "usb2-phy"; 481 status = "disabled"; 482 }; 483 484 usb_hsic: usb@ff5c0000 { 485 compatible = "generic-ehci"; 486 reg = <0xff5c0000 0x100>; 487 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 488 clocks = <&cru HCLK_HSIC>; 489 clock-names = "usbhost"; 490 status = "disabled"; 491 }; 492 493 dmc: dmc@ff610000 { 494 compatible = "rockchip,rk3288-dmc", "syscon"; 495 rockchip,cru = <&cru>; 496 rockchip,grf = <&grf>; 497 rockchip,pmu = <&pmu>; 498 rockchip,sgrf = <&sgrf>; 499 rockchip,noc = <&noc>; 500 reg = <0xff610000 0x3fc 501 0xff620000 0x294 502 0xff630000 0x3fc 503 0xff640000 0x294>; 504 rockchip,sram = <&ddr_sram>; 505 clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>, 506 <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>, 507 <&cru ARMCLK>; 508 clock-names = "pclk_ddrupctl0", "pclk_publ0", 509 "pclk_ddrupctl1", "pclk_publ1", 510 "arm_clk"; 511 }; 512 513 i2c0: i2c@ff650000 { 514 compatible = "rockchip,rk3288-i2c"; 515 reg = <0xff650000 0x1000>; 516 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 517 #address-cells = <1>; 518 #size-cells = <0>; 519 clock-names = "i2c"; 520 clocks = <&cru PCLK_I2C0>; 521 pinctrl-names = "default"; 522 pinctrl-0 = <&i2c0_xfer>; 523 status = "disabled"; 524 }; 525 526 i2c2: i2c@ff660000 { 527 compatible = "rockchip,rk3288-i2c"; 528 reg = <0xff660000 0x1000>; 529 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 530 #address-cells = <1>; 531 #size-cells = <0>; 532 clock-names = "i2c"; 533 clocks = <&cru PCLK_I2C2>; 534 pinctrl-names = "default"; 535 pinctrl-0 = <&i2c2_xfer>; 536 status = "disabled"; 537 }; 538 539 pwm0: pwm@ff680000 { 540 compatible = "rockchip,rk3288-pwm"; 541 reg = <0xff680000 0x10>; 542 #pwm-cells = <3>; 543 pinctrl-names = "active"; 544 pinctrl-0 = <&pwm0_pin>; 545 clocks = <&cru PCLK_PWM>; 546 clock-names = "pwm"; 547 rockchip,grf = <&grf>; 548 status = "disabled"; 549 }; 550 551 pwm1: pwm@ff680010 { 552 compatible = "rockchip,rk3288-pwm"; 553 reg = <0xff680010 0x10>; 554 #pwm-cells = <3>; 555 pinctrl-names = "active"; 556 pinctrl-0 = <&pwm1_pin>; 557 clocks = <&cru PCLK_PWM>; 558 clock-names = "pwm"; 559 rockchip,grf = <&grf>; 560 status = "disabled"; 561 }; 562 563 pwm2: pwm@ff680020 { 564 compatible = "rockchip,rk3288-pwm"; 565 reg = <0xff680020 0x10>; 566 #pwm-cells = <3>; 567 pinctrl-names = "active"; 568 pinctrl-0 = <&pwm2_pin>; 569 clocks = <&cru PCLK_PWM>; 570 clock-names = "pwm"; 571 rockchip,grf = <&grf>; 572 status = "disabled"; 573 }; 574 575 pwm3: pwm@ff680030 { 576 compatible = "rockchip,rk3288-pwm"; 577 reg = <0xff680030 0x10>; 578 #pwm-cells = <2>; 579 pinctrl-names = "active"; 580 pinctrl-0 = <&pwm3_pin>; 581 clocks = <&cru PCLK_PWM>; 582 clock-names = "pwm"; 583 rockchip,grf = <&grf>; 584 status = "disabled"; 585 }; 586 587 bus_intmem@ff700000 { 588 compatible = "mmio-sram"; 589 reg = <0xff700000 0x18000>; 590 #address-cells = <1>; 591 #size-cells = <1>; 592 ranges = <0 0xff700000 0x18000>; 593 smp-sram@0 { 594 compatible = "rockchip,rk3066-smp-sram"; 595 reg = <0x00 0x10>; 596 }; 597 ddr_sram: ddr-sram@1000 { 598 compatible = "rockchip,rk3288-ddr-sram"; 599 reg = <0x1000 0x4000>; 600 }; 601 }; 602 603 sram@ff720000 { 604 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram"; 605 reg = <0xff720000 0x1000>; 606 }; 607 608 pmu: power-management@ff730000 { 609 compatible = "rockchip,rk3288-pmu", "syscon"; 610 reg = <0xff730000 0x100>; 611 }; 612 613 sgrf: syscon@ff740000 { 614 compatible = "rockchip,rk3288-sgrf", "syscon"; 615 reg = <0xff740000 0x1000>; 616 }; 617 618 cru: clock-controller@ff760000 { 619 compatible = "rockchip,rk3288-cru"; 620 reg = <0xff760000 0x1000>; 621 rockchip,grf = <&grf>; 622 #clock-cells = <1>; 623 #reset-cells = <1>; 624 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>, 625 <&cru PLL_NPLL>, <&cru ACLK_CPU>, 626 <&cru HCLK_CPU>, <&cru PCLK_CPU>, 627 <&cru ACLK_PERI>, <&cru HCLK_PERI>, 628 <&cru PCLK_PERI>; 629 assigned-clock-rates = <594000000>, <400000000>, 630 <500000000>, <300000000>, 631 <150000000>, <75000000>, 632 <300000000>, <150000000>, 633 <75000000>; 634 }; 635 636 grf: syscon@ff770000 { 637 compatible = "rockchip,rk3288-grf", "syscon"; 638 reg = <0xff770000 0x1000>; 639 }; 640 641 wdt: watchdog@ff800000 { 642 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt"; 643 reg = <0xff800000 0x100>; 644 clocks = <&cru PCLK_WDT>; 645 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 646 status = "disabled"; 647 }; 648 649 spdif: sound@ff88b0000 { 650 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif"; 651 reg = <0xff8b0000 0x10000>; 652 #sound-dai-cells = <0>; 653 clock-names = "hclk", "mclk"; 654 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>; 655 dmas = <&dmac_bus_s 3>; 656 dma-names = "tx"; 657 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 658 pinctrl-names = "default"; 659 pinctrl-0 = <&spdif_tx>; 660 rockchip,grf = <&grf>; 661 status = "disabled"; 662 }; 663 664 i2s: i2s@ff890000 { 665 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s"; 666 reg = <0xff890000 0x10000>; 667 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 668 #address-cells = <1>; 669 #size-cells = <0>; 670 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>; 671 dma-names = "tx", "rx"; 672 clock-names = "i2s_hclk", "i2s_clk"; 673 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; 674 pinctrl-names = "default"; 675 pinctrl-0 = <&i2s0_bus>; 676 status = "disabled"; 677 }; 678 679 vopb: vop@ff930000 { 680 compatible = "rockchip,rk3288-vop-big"; 681 reg = <0xff930000 0x19c>; 682 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 683 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; 684 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 685 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; 686 reset-names = "axi", "ahb", "dclk"; 687 iommus = <&vopb_mmu>; 688 power-domains = <&power RK3288_PD_VIO>; 689 status = "disabled"; 690 vopb_out: port { 691 #address-cells = <1>; 692 #size-cells = <0>; 693 vopb_out_edp: endpoint@0 { 694 reg = <0>; 695 remote-endpoint = <&edp_in_vopb>; 696 }; 697 vopb_out_hdmi: endpoint@1 { 698 reg = <1>; 699 remote-endpoint = <&hdmi_in_vopb>; 700 }; 701 vopb_out_lvds: endpoint@2 { 702 reg = <2>; 703 remote-endpoint = <&lvds_in_vopb>; 704 }; 705 vopb_out_mipi: endpoint@3 { 706 reg = <3>; 707 remote-endpoint = <&mipi_in_vopb>; 708 }; 709 710 }; 711 }; 712 713 vopb_mmu: iommu@ff930300 { 714 compatible = "rockchip,iommu"; 715 reg = <0xff930300 0x100>; 716 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 717 interrupt-names = "vopb_mmu"; 718 power-domains = <&power RK3288_PD_VIO>; 719 #iommu-cells = <0>; 720 status = "disabled"; 721 }; 722 723 vopl: vop@ff940000 { 724 compatible = "rockchip,rk3288-vop-lit"; 725 reg = <0xff940000 0x19c>; 726 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 727 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; 728 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 729 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>; 730 reset-names = "axi", "ahb", "dclk"; 731 iommus = <&vopl_mmu>; 732 power-domains = <&power RK3288_PD_VIO>; 733 status = "disabled"; 734 vopl_out: port { 735 #address-cells = <1>; 736 #size-cells = <0>; 737 vopl_out_edp: endpoint@0 { 738 reg = <0>; 739 remote-endpoint = <&edp_in_vopl>; 740 }; 741 vopl_out_hdmi: endpoint@1 { 742 reg = <1>; 743 remote-endpoint = <&hdmi_in_vopl>; 744 }; 745 vopl_out_lvds: endpoint@2 { 746 reg = <2>; 747 remote-endpoint = <&lvds_in_vopl>; 748 }; 749 vopl_out_mipi: endpoint@3 { 750 reg = <3>; 751 remote-endpoint = <&mipi_in_vopl>; 752 }; 753 754 }; 755 }; 756 757 vopl_mmu: iommu@ff940300 { 758 compatible = "rockchip,iommu"; 759 reg = <0xff940300 0x100>; 760 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 761 interrupt-names = "vopl_mmu"; 762 power-domains = <&power RK3288_PD_VIO>; 763 #iommu-cells = <0>; 764 status = "disabled"; 765 }; 766 767 edp: edp@ff970000 { 768 compatible = "rockchip,rk3288-dp"; 769 reg = <0xff970000 0x4000>; 770 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 771 clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>; 772 rockchip,grf = <&grf>; 773 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp"; 774 resets = <&cru 111>; 775 reset-names = "edp"; 776 power-domains = <&power RK3288_PD_VIO>; 777 status = "disabled"; 778 ports { 779 #address-cells = <1>; 780 #size-cells = <0>; 781 782 edp_in: port { 783 #address-cells = <1>; 784 #size-cells = <0>; 785 edp_in_vopb: endpoint@0 { 786 reg = <0>; 787 remote-endpoint = <&vopb_out_edp>; 788 }; 789 edp_in_vopl: endpoint@1 { 790 reg = <1>; 791 remote-endpoint = <&vopl_out_edp>; 792 }; 793 }; 794 }; 795 }; 796 797 hdmi: hdmi@ff980000 { 798 compatible = "rockchip,rk3288-dw-hdmi"; 799 reg = <0xff980000 0x20000>; 800 reg-io-width = <4>; 801 ddc-i2c-bus = <&i2c5>; 802 rockchip,grf = <&grf>; 803 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 804 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>; 805 clock-names = "iahb", "isfr"; 806 status = "disabled"; 807 ports { 808 hdmi_in: port { 809 #address-cells = <1>; 810 #size-cells = <0>; 811 hdmi_in_vopb: endpoint@0 { 812 reg = <0>; 813 remote-endpoint = <&vopb_out_hdmi>; 814 }; 815 hdmi_in_vopl: endpoint@1 { 816 reg = <1>; 817 remote-endpoint = <&vopl_out_hdmi>; 818 }; 819 }; 820 }; 821 }; 822 823 lvds: lvds@ff96c000 { 824 compatible = "rockchip,rk3288-lvds"; 825 reg = <0xff96c000 0x4000>; 826 clocks = <&cru PCLK_LVDS_PHY>; 827 clock-names = "pclk_lvds"; 828 pinctrl-names = "default"; 829 pinctrl-0 = <&lcdc0_ctl>; 830 rockchip,grf = <&grf>; 831 status = "disabled"; 832 ports { 833 #address-cells = <1>; 834 #size-cells = <0>; 835 lvds_in: port@0 { 836 reg = <0>; 837 #address-cells = <1>; 838 #size-cells = <0>; 839 lvds_in_vopb: endpoint@0 { 840 reg = <0>; 841 remote-endpoint = <&vopb_out_lvds>; 842 }; 843 lvds_in_vopl: endpoint@1 { 844 reg = <1>; 845 remote-endpoint = <&vopl_out_lvds>; 846 }; 847 }; 848 }; 849 }; 850 851 mipi_dsi0: mipi@ff960000 { 852 compatible = "rockchip,rk3288_mipi_dsi"; 853 reg = <0xff960000 0x4000>; 854 clocks = <&cru PCLK_MIPI_DSI0>; 855 clock-names = "pclk_mipi"; 856 /*pinctrl-names = "default"; 857 pinctrl-0 = <&lcdc0_ctl>;*/ 858 rockchip,grf = <&grf>; 859 #address-cells = <1>; 860 #size-cells = <0>; 861 status = "disabled"; 862 ports { 863 #address-cells = <1>; 864 #size-cells = <0>; 865 reg = <1>; 866 mipi_in: port { 867 #address-cells = <1>; 868 #size-cells = <0>; 869 mipi_in_vopb: endpoint@0 { 870 reg = <0>; 871 remote-endpoint = <&vopb_out_mipi>; 872 }; 873 mipi_in_vopl: endpoint@1 { 874 reg = <1>; 875 remote-endpoint = <&vopl_out_mipi>; 876 }; 877 }; 878 }; 879 }; 880 881 hdmi_audio: hdmi_audio { 882 compatible = "rockchip,rk3288-hdmi-audio"; 883 i2s-controller = <&i2s>; 884 status = "disable"; 885 }; 886 887 vpu: video-codec@ff9a0000 { 888 compatible = "rockchip,rk3288-vpu"; 889 reg = <0xff9a0000 0x800>; 890 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 891 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 892 interrupt-names = "vepu", "vdpu"; 893 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 894 clock-names = "aclk_vcodec", "hclk_vcodec"; 895 power-domains = <&power RK3288_PD_VIDEO>; 896 iommus = <&vpu_mmu>; 897 }; 898 899 vpu_mmu: iommu@ff9a0800 { 900 compatible = "rockchip,iommu"; 901 reg = <0xff9a0800 0x100>; 902 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 903 interrupt-names = "vpu_mmu"; 904 power-domains = <&power RK3288_PD_VIDEO>; 905 #iommu-cells = <0>; 906 }; 907 908 gpu: gpu@ffa30000 { 909 compatible = "arm,malit764", 910 "arm,malit76x", 911 "arm,malit7xx", 912 "arm,mali-midgard"; 913 reg = <0xffa30000 0x10000>; 914 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 915 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 916 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 917 interrupt-names = "JOB", "MMU", "GPU"; 918 clocks = <&cru ACLK_GPU>; 919 clock-names = "aclk_gpu"; 920 operating-points = < 921 /* KHz uV */ 922 100000 950000 923 200000 950000 924 300000 1000000 925 400000 1100000 926 /* 500000 1200000 - See crosbug.com/p/33857 */ 927 600000 1250000 928 >; 929 power-domains = <&power RK3288_PD_GPU>; 930 status = "disabled"; 931 }; 932 933 noc: syscon@ffac0000 { 934 compatible = "rockchip,rk3288-noc", "syscon"; 935 reg = <0xffac0000 0x2000>; 936 }; 937 938 efuse: efuse@ffb40000 { 939 compatible = "rockchip,rk3288-efuse"; 940 reg = <0xffb40000 0x10000>; 941 status = "disabled"; 942 }; 943 944 gic: interrupt-controller@ffc01000 { 945 compatible = "arm,gic-400"; 946 interrupt-controller; 947 #interrupt-cells = <3>; 948 #address-cells = <0>; 949 950 reg = <0xffc01000 0x1000>, 951 <0xffc02000 0x1000>, 952 <0xffc04000 0x2000>, 953 <0xffc06000 0x2000>; 954 interrupts = <GIC_PPI 9 0xf04>; 955 }; 956 957 cpuidle: cpuidle { 958 compatible = "rockchip,rk3288-cpuidle"; 959 }; 960 961 usbphy: phy { 962 compatible = "rockchip,rk3288-usb-phy"; 963 rockchip,grf = <&grf>; 964 #address-cells = <1>; 965 #size-cells = <0>; 966 status = "disabled"; 967 968 usbphy0: usb-phy0 { 969 #phy-cells = <0>; 970 reg = <0x320>; 971 clocks = <&cru SCLK_OTGPHY0>; 972 clock-names = "phyclk"; 973 }; 974 975 usbphy1: usb-phy1 { 976 #phy-cells = <0>; 977 reg = <0x334>; 978 clocks = <&cru SCLK_OTGPHY1>; 979 clock-names = "phyclk"; 980 }; 981 982 usbphy2: usb-phy2 { 983 #phy-cells = <0>; 984 reg = <0x348>; 985 clocks = <&cru SCLK_OTGPHY2>; 986 clock-names = "phyclk"; 987 }; 988 }; 989 990 pinctrl: pinctrl { 991 compatible = "rockchip,rk3288-pinctrl"; 992 rockchip,grf = <&grf>; 993 rockchip,pmu = <&pmu>; 994 #address-cells = <1>; 995 #size-cells = <1>; 996 ranges; 997 998 gpio0: gpio0@ff750000 { 999 compatible = "rockchip,gpio-bank"; 1000 reg = <0xff750000 0x100>; 1001 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1002 clocks = <&cru PCLK_GPIO0>; 1003 1004 gpio-controller; 1005 #gpio-cells = <2>; 1006 1007 interrupt-controller; 1008 #interrupt-cells = <2>; 1009 }; 1010 1011 gpio1: gpio1@ff780000 { 1012 compatible = "rockchip,gpio-bank"; 1013 reg = <0xff780000 0x100>; 1014 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1015 clocks = <&cru PCLK_GPIO1>; 1016 1017 gpio-controller; 1018 #gpio-cells = <2>; 1019 1020 interrupt-controller; 1021 #interrupt-cells = <2>; 1022 }; 1023 1024 gpio2: gpio2@ff790000 { 1025 compatible = "rockchip,gpio-bank"; 1026 reg = <0xff790000 0x100>; 1027 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1028 clocks = <&cru PCLK_GPIO2>; 1029 1030 gpio-controller; 1031 #gpio-cells = <2>; 1032 1033 interrupt-controller; 1034 #interrupt-cells = <2>; 1035 }; 1036 1037 gpio3: gpio3@ff7a0000 { 1038 compatible = "rockchip,gpio-bank"; 1039 reg = <0xff7a0000 0x100>; 1040 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1041 clocks = <&cru PCLK_GPIO3>; 1042 1043 gpio-controller; 1044 #gpio-cells = <2>; 1045 1046 interrupt-controller; 1047 #interrupt-cells = <2>; 1048 }; 1049 1050 gpio4: gpio4@ff7b0000 { 1051 compatible = "rockchip,gpio-bank"; 1052 reg = <0xff7b0000 0x100>; 1053 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1054 clocks = <&cru PCLK_GPIO4>; 1055 1056 gpio-controller; 1057 #gpio-cells = <2>; 1058 1059 interrupt-controller; 1060 #interrupt-cells = <2>; 1061 }; 1062 1063 gpio5: gpio5@ff7c0000 { 1064 compatible = "rockchip,gpio-bank"; 1065 reg = <0xff7c0000 0x100>; 1066 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1067 clocks = <&cru PCLK_GPIO5>; 1068 1069 gpio-controller; 1070 #gpio-cells = <2>; 1071 1072 interrupt-controller; 1073 #interrupt-cells = <2>; 1074 }; 1075 1076 gpio6: gpio6@ff7d0000 { 1077 compatible = "rockchip,gpio-bank"; 1078 reg = <0xff7d0000 0x100>; 1079 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1080 clocks = <&cru PCLK_GPIO6>; 1081 1082 gpio-controller; 1083 #gpio-cells = <2>; 1084 1085 interrupt-controller; 1086 #interrupt-cells = <2>; 1087 }; 1088 1089 gpio7: gpio7@ff7e0000 { 1090 compatible = "rockchip,gpio-bank"; 1091 reg = <0xff7e0000 0x100>; 1092 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1093 clocks = <&cru PCLK_GPIO7>; 1094 1095 gpio-controller; 1096 #gpio-cells = <2>; 1097 1098 interrupt-controller; 1099 #interrupt-cells = <2>; 1100 }; 1101 1102 gpio8: gpio8@ff7f0000 { 1103 compatible = "rockchip,gpio-bank"; 1104 reg = <0xff7f0000 0x100>; 1105 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 1106 clocks = <&cru PCLK_GPIO8>; 1107 1108 gpio-controller; 1109 #gpio-cells = <2>; 1110 1111 interrupt-controller; 1112 #interrupt-cells = <2>; 1113 }; 1114 1115 pcfg_pull_up: pcfg-pull-up { 1116 bias-pull-up; 1117 }; 1118 1119 pcfg_pull_down: pcfg-pull-down { 1120 bias-pull-down; 1121 }; 1122 1123 pcfg_pull_none: pcfg-pull-none { 1124 bias-disable; 1125 }; 1126 1127 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1128 bias-disable; 1129 drive-strength = <12>; 1130 }; 1131 1132 sleep { 1133 global_pwroff: global-pwroff { 1134 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>; 1135 }; 1136 1137 ddrio_pwroff: ddrio-pwroff { 1138 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>; 1139 }; 1140 1141 ddr0_retention: ddr0-retention { 1142 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>; 1143 }; 1144 1145 ddr1_retention: ddr1-retention { 1146 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>; 1147 }; 1148 }; 1149 1150 i2c0 { 1151 i2c0_xfer: i2c0-xfer { 1152 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>, 1153 <0 16 RK_FUNC_1 &pcfg_pull_none>; 1154 }; 1155 }; 1156 1157 i2c1 { 1158 i2c1_xfer: i2c1-xfer { 1159 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>, 1160 <8 5 RK_FUNC_1 &pcfg_pull_none>; 1161 }; 1162 }; 1163 1164 i2c2 { 1165 i2c2_xfer: i2c2-xfer { 1166 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>, 1167 <6 10 RK_FUNC_1 &pcfg_pull_none>; 1168 }; 1169 }; 1170 1171 i2c3 { 1172 i2c3_xfer: i2c3-xfer { 1173 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>, 1174 <2 17 RK_FUNC_1 &pcfg_pull_none>; 1175 }; 1176 }; 1177 1178 i2c4 { 1179 i2c4_xfer: i2c4-xfer { 1180 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>, 1181 <7 18 RK_FUNC_1 &pcfg_pull_none>; 1182 }; 1183 }; 1184 1185 i2c5 { 1186 i2c5_xfer: i2c5-xfer { 1187 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>, 1188 <7 20 RK_FUNC_1 &pcfg_pull_none>; 1189 }; 1190 }; 1191 1192 i2s0 { 1193 i2s0_bus: i2s0-bus { 1194 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>, 1195 <6 1 RK_FUNC_1 &pcfg_pull_none>, 1196 <6 2 RK_FUNC_1 &pcfg_pull_none>, 1197 <6 3 RK_FUNC_1 &pcfg_pull_none>, 1198 <6 4 RK_FUNC_1 &pcfg_pull_none>, 1199 <6 8 RK_FUNC_1 &pcfg_pull_none>; 1200 }; 1201 }; 1202 1203 lcdc0 { 1204 lcdc0_ctl: lcdc0-ctl { 1205 rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>, 1206 <1 25 RK_FUNC_1 &pcfg_pull_none>, 1207 <1 26 RK_FUNC_1 &pcfg_pull_none>, 1208 <1 27 RK_FUNC_1 &pcfg_pull_none>; 1209 }; 1210 }; 1211 1212 sdmmc { 1213 sdmmc_clk: sdmmc-clk { 1214 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>; 1215 }; 1216 1217 sdmmc_cmd: sdmmc-cmd { 1218 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>; 1219 }; 1220 1221 sdmmc_cd: sdmcc-cd { 1222 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>; 1223 }; 1224 1225 sdmmc_bus1: sdmmc-bus1 { 1226 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>; 1227 }; 1228 1229 sdmmc_bus4: sdmmc-bus4 { 1230 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>, 1231 <6 17 RK_FUNC_1 &pcfg_pull_up>, 1232 <6 18 RK_FUNC_1 &pcfg_pull_up>, 1233 <6 19 RK_FUNC_1 &pcfg_pull_up>; 1234 }; 1235 }; 1236 1237 sdio0 { 1238 sdio0_bus1: sdio0-bus1 { 1239 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>; 1240 }; 1241 1242 sdio0_bus4: sdio0-bus4 { 1243 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>, 1244 <4 21 RK_FUNC_1 &pcfg_pull_up>, 1245 <4 22 RK_FUNC_1 &pcfg_pull_up>, 1246 <4 23 RK_FUNC_1 &pcfg_pull_up>; 1247 }; 1248 1249 sdio0_cmd: sdio0-cmd { 1250 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>; 1251 }; 1252 1253 sdio0_clk: sdio0-clk { 1254 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>; 1255 }; 1256 1257 sdio0_cd: sdio0-cd { 1258 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>; 1259 }; 1260 1261 sdio0_wp: sdio0-wp { 1262 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>; 1263 }; 1264 1265 sdio0_pwr: sdio0-pwr { 1266 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>; 1267 }; 1268 1269 sdio0_bkpwr: sdio0-bkpwr { 1270 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>; 1271 }; 1272 1273 sdio0_int: sdio0-int { 1274 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>; 1275 }; 1276 }; 1277 1278 sdio1 { 1279 sdio1_bus1: sdio1-bus1 { 1280 rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>; 1281 }; 1282 1283 sdio1_bus4: sdio1-bus4 { 1284 rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>, 1285 <3 25 RK_FUNC_4 &pcfg_pull_up>, 1286 <3 26 RK_FUNC_4 &pcfg_pull_up>, 1287 <3 27 RK_FUNC_4 &pcfg_pull_up>; 1288 }; 1289 1290 sdio1_cd: sdio1-cd { 1291 rockchip,pins = <3 28 RK_FUNC_4 &pcfg_pull_up>; 1292 }; 1293 1294 sdio1_wp: sdio1-wp { 1295 rockchip,pins = <3 29 RK_FUNC_4 &pcfg_pull_up>; 1296 }; 1297 1298 sdio1_bkpwr: sdio1-bkpwr { 1299 rockchip,pins = <3 30 RK_FUNC_4 &pcfg_pull_up>; 1300 }; 1301 1302 sdio1_int: sdio1-int { 1303 rockchip,pins = <3 31 RK_FUNC_4 &pcfg_pull_up>; 1304 }; 1305 1306 sdio1_cmd: sdio1-cmd { 1307 rockchip,pins = <4 6 RK_FUNC_4 &pcfg_pull_up>; 1308 }; 1309 1310 sdio1_clk: sdio1-clk { 1311 rockchip,pins = <4 7 RK_FUNC_4 &pcfg_pull_none>; 1312 }; 1313 1314 sdio1_pwr: sdio1-pwr { 1315 rockchip,pins = <4 9 RK_FUNC_4 &pcfg_pull_up>; 1316 }; 1317 }; 1318 1319 emmc { 1320 emmc_clk: emmc-clk { 1321 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>; 1322 }; 1323 1324 emmc_cmd: emmc-cmd { 1325 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>; 1326 }; 1327 1328 emmc_pwr: emmc-pwr { 1329 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>; 1330 }; 1331 1332 emmc_bus1: emmc-bus1 { 1333 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>; 1334 }; 1335 1336 emmc_bus4: emmc-bus4 { 1337 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>, 1338 <3 1 RK_FUNC_2 &pcfg_pull_up>, 1339 <3 2 RK_FUNC_2 &pcfg_pull_up>, 1340 <3 3 RK_FUNC_2 &pcfg_pull_up>; 1341 }; 1342 1343 emmc_bus8: emmc-bus8 { 1344 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>, 1345 <3 1 RK_FUNC_2 &pcfg_pull_up>, 1346 <3 2 RK_FUNC_2 &pcfg_pull_up>, 1347 <3 3 RK_FUNC_2 &pcfg_pull_up>, 1348 <3 4 RK_FUNC_2 &pcfg_pull_up>, 1349 <3 5 RK_FUNC_2 &pcfg_pull_up>, 1350 <3 6 RK_FUNC_2 &pcfg_pull_up>, 1351 <3 7 RK_FUNC_2 &pcfg_pull_up>; 1352 }; 1353 }; 1354 1355 spi0 { 1356 spi0_clk: spi0-clk { 1357 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>; 1358 }; 1359 spi0_cs0: spi0-cs0 { 1360 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>; 1361 }; 1362 spi0_tx: spi0-tx { 1363 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>; 1364 }; 1365 spi0_rx: spi0-rx { 1366 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>; 1367 }; 1368 spi0_cs1: spi0-cs1 { 1369 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>; 1370 }; 1371 }; 1372 spi1 { 1373 spi1_clk: spi1-clk { 1374 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>; 1375 }; 1376 spi1_cs0: spi1-cs0 { 1377 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>; 1378 }; 1379 spi1_rx: spi1-rx { 1380 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>; 1381 }; 1382 spi1_tx: spi1-tx { 1383 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>; 1384 }; 1385 }; 1386 1387 spi2 { 1388 spi2_cs1: spi2-cs1 { 1389 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>; 1390 }; 1391 spi2_clk: spi2-clk { 1392 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>; 1393 }; 1394 spi2_cs0: spi2-cs0 { 1395 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>; 1396 }; 1397 spi2_rx: spi2-rx { 1398 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>; 1399 }; 1400 spi2_tx: spi2-tx { 1401 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>; 1402 }; 1403 }; 1404 1405 uart0 { 1406 uart0_xfer: uart0-xfer { 1407 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>, 1408 <4 17 RK_FUNC_1 &pcfg_pull_none>; 1409 }; 1410 1411 uart0_cts: uart0-cts { 1412 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>; 1413 }; 1414 1415 uart0_rts: uart0-rts { 1416 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>; 1417 }; 1418 }; 1419 1420 uart1 { 1421 uart1_xfer: uart1-xfer { 1422 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>, 1423 <5 9 RK_FUNC_1 &pcfg_pull_none>; 1424 }; 1425 1426 uart1_cts: uart1-cts { 1427 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>; 1428 }; 1429 1430 uart1_rts: uart1-rts { 1431 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>; 1432 }; 1433 }; 1434 1435 uart2 { 1436 uart2_xfer: uart2-xfer { 1437 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>, 1438 <7 23 RK_FUNC_1 &pcfg_pull_none>; 1439 }; 1440 /* no rts / cts for uart2 */ 1441 }; 1442 1443 uart3 { 1444 uart3_xfer: uart3-xfer { 1445 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>, 1446 <7 8 RK_FUNC_1 &pcfg_pull_none>; 1447 }; 1448 1449 uart3_cts: uart3-cts { 1450 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>; 1451 }; 1452 1453 uart3_rts: uart3-rts { 1454 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>; 1455 }; 1456 }; 1457 1458 uart4 { 1459 uart4_xfer: uart4-xfer { 1460 rockchip,pins = <5 12 3 &pcfg_pull_up>, 1461 <5 13 3 &pcfg_pull_none>; 1462 }; 1463 1464 uart4_cts: uart4-cts { 1465 rockchip,pins = <5 14 3 &pcfg_pull_none>; 1466 }; 1467 1468 uart4_rts: uart4-rts { 1469 rockchip,pins = <5 15 3 &pcfg_pull_none>; 1470 }; 1471 }; 1472 1473 tsadc { 1474 otp_out: otp-out { 1475 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>; 1476 }; 1477 }; 1478 1479 pwm0 { 1480 pwm0_pin: pwm0-pin { 1481 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>; 1482 }; 1483 }; 1484 1485 pwm1 { 1486 pwm1_pin: pwm1-pin { 1487 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>; 1488 }; 1489 }; 1490 1491 pwm2 { 1492 pwm2_pin: pwm2-pin { 1493 rockchip,pins = <7 22 RK_FUNC_3 &pcfg_pull_none>; 1494 }; 1495 }; 1496 1497 pwm3 { 1498 pwm3_pin: pwm3-pin { 1499 rockchip,pins = <7 23 RK_FUNC_3 &pcfg_pull_none>; 1500 }; 1501 }; 1502 1503 gmac { 1504 rgmii_pins: rgmii-pins { 1505 rockchip,pins = <3 30 3 &pcfg_pull_none>, 1506 <3 31 3 &pcfg_pull_none>, 1507 <3 26 3 &pcfg_pull_none>, 1508 <3 27 3 &pcfg_pull_none>, 1509 <3 28 3 &pcfg_pull_none_12ma>, 1510 <3 29 3 &pcfg_pull_none_12ma>, 1511 <3 24 3 &pcfg_pull_none_12ma>, 1512 <3 25 3 &pcfg_pull_none_12ma>, 1513 <4 0 3 &pcfg_pull_none>, 1514 <4 5 3 &pcfg_pull_none>, 1515 <4 6 3 &pcfg_pull_none>, 1516 <4 9 3 &pcfg_pull_none_12ma>, 1517 <4 4 3 &pcfg_pull_none_12ma>, 1518 <4 1 3 &pcfg_pull_none>, 1519 <4 3 3 &pcfg_pull_none>; 1520 }; 1521 1522 rmii_pins: rmii-pins { 1523 rockchip,pins = <3 30 3 &pcfg_pull_none>, 1524 <3 31 3 &pcfg_pull_none>, 1525 <3 28 3 &pcfg_pull_none>, 1526 <3 29 3 &pcfg_pull_none>, 1527 <4 0 3 &pcfg_pull_none>, 1528 <4 5 3 &pcfg_pull_none>, 1529 <4 4 3 &pcfg_pull_none>, 1530 <4 1 3 &pcfg_pull_none>, 1531 <4 2 3 &pcfg_pull_none>, 1532 <4 3 3 &pcfg_pull_none>; 1533 }; 1534 }; 1535 1536 spdif { 1537 spdif_tx: spdif-tx { 1538 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>; 1539 }; 1540 }; 1541 }; 1542 1543 power: power-controller { 1544 compatible = "rockchip,rk3288-power-controller"; 1545 #power-domain-cells = <1>; 1546 rockchip,pmu = <&pmu>; 1547 #address-cells = <1>; 1548 #size-cells = <0>; 1549 1550 pd_gpu { 1551 reg = <RK3288_PD_GPU>; 1552 clocks = <&cru ACLK_GPU>; 1553 }; 1554 1555 pd_hevc { 1556 reg = <RK3288_PD_HEVC>; 1557 clocks = <&cru ACLK_HEVC>, 1558 <&cru SCLK_HEVC_CABAC>, 1559 <&cru SCLK_HEVC_CORE>, 1560 <&cru HCLK_HEVC>; 1561 }; 1562 1563 pd_vio { 1564 reg = <RK3288_PD_VIO>; 1565 clocks = <&cru ACLK_IEP>, 1566 <&cru ACLK_ISP>, 1567 <&cru ACLK_RGA>, 1568 <&cru ACLK_VIP>, 1569 <&cru ACLK_VOP0>, 1570 <&cru ACLK_VOP1>, 1571 <&cru DCLK_VOP0>, 1572 <&cru DCLK_VOP1>, 1573 <&cru HCLK_IEP>, 1574 <&cru HCLK_ISP>, 1575 <&cru HCLK_RGA>, 1576 <&cru HCLK_VIP>, 1577 <&cru HCLK_VOP0>, 1578 <&cru HCLK_VOP1>, 1579 <&cru PCLK_EDP_CTRL>, 1580 <&cru PCLK_HDMI_CTRL>, 1581 <&cru PCLK_LVDS_PHY>, 1582 <&cru PCLK_MIPI_CSI>, 1583 <&cru PCLK_MIPI_DSI0>, 1584 <&cru PCLK_MIPI_DSI1>, 1585 <&cru SCLK_EDP_24M>, 1586 <&cru SCLK_EDP>, 1587 <&cru SCLK_HDMI_CEC>, 1588 <&cru SCLK_HDMI_HDCP>, 1589 <&cru SCLK_ISP_JPE>, 1590 <&cru SCLK_ISP>, 1591 <&cru SCLK_RGA>; 1592 }; 1593 1594 pd_video { 1595 reg = <RK3288_PD_VIDEO>; 1596 clocks = <&cru ACLK_VCODEC>, 1597 <&cru HCLK_VCODEC>; 1598 }; 1599 }; 1600}; 1601
