1 /* 2 * (C) Copyright 2013 3 * David Feng <fenghua@phytium.com.cn> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <linux/compiler.h> 10 #include <efi_loader.h> 11 12 DECLARE_GLOBAL_DATA_PTR; 13 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_IRQ) 14 15 int interrupt_init(void) 16 { 17 return 0; 18 } 19 20 void enable_interrupts(void) 21 { 22 return; 23 } 24 25 int disable_interrupts(void) 26 { 27 return 0; 28 } 29 #endif 30 31 #if (!defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)) 32 #define REG_BITS(val, shift, mask) (((val) >> (shift)) & (mask)) 33 34 void show_regs(struct pt_regs *regs) 35 { 36 int i; 37 int el = current_el(); 38 const char *h_scr_name[] = { 39 [2] = "HCR_EL2", 40 [3] = "SCR_EL3", 41 }; 42 const char *esr_bits_ec[] = { 43 [0] = "EC[31:26] == 000000, Exception with an unknown reason", 44 [1] = "EC[31:26] == 000001, Exception from a WFI or WFE instruction", 45 [3] = "EC[31:26] == 000011, Exception from an MCR or MRC access", 46 [4] = "EC[31:26] == 000100, Exception from an MCRR or MRRC access", 47 [5] = "EC[31:26] == 000101, Exception from an MCR or MRC access", 48 [6] = "EC[31:26] == 000110, Exception from an LDC or STC access to CP14", 49 [7] = "EC[31:26] == 000111, Exception from an access to an Advanced SIMD or floating-point register, resulting from CPACR_EL1.FPEN or CPTR_ELx.TFP", 50 [8] = "EC[31:26] == 001000, Exception from an MCR or MRC access", 51 [12] = "EC[31:26] == 001100, Exception from an MCRR or MRRC access", 52 [14] = "EC[31:26] == 001110, Exception from an Illegal execution state, or a PC or SP alignment fault", 53 [10] = "EC[31:26] == 010001, Exception from HVC or SVC instruction execution", 54 [18] = "EC[31:26] == 010010, Exception from HVC or SVC instruction execution", 55 [19] = "EC[31:26] == 010011, Exception from SMC instruction execution in AArch32 state", 56 [21] = "EC[31:26] == 010101, Exception from HVC or SVC instruction execution", 57 [22] = "EC[31:26] == 010110, Exception from HVC or SVC instruction execution", 58 [23] = "EC[31:26] == 010111, Exception from SMC instruction execution in AArch64 state", 59 [24] = "EC[31:26] == 011000, Exception from MSR, MRS, or System instruction execution in AArch64 state", 60 [31] = "EC[31:26] == 011111, IMPLEMENTATION DEFINED exception to EL3", 61 [32] = "EC[31:26] == 100000, Exception from an Instruction abort", 62 [33] = "EC[31:26] == 100001, Exception from an Instruction abort", 63 [34] = "EC[31:26] == 100010, Exception from an Illegal execution state, or a PC or SP alignment fault", 64 [36] = "EC[31:26] == 100100, Exception from a Data abort, from lower exception level", 65 [37] = "EC[31:26] == 100101, Exception from a Data abort, from current exception level", 66 [38] = "EC[31:26] == 100110, Exception from an Illegal execution state, or a PC or SP alignment fault", 67 [40] = "EC[31:26] == 101000, Exception from a trapped Floating-point exception", 68 [44] = "EC[31:26] == 101100, Exception from a trapped Floating-point exception", 69 [47] = "EC[31:26] == 101111, SError interrupt", 70 [48] = "EC[31:26] == 110000, Exception from a Breakpoint or Vector Catch debug event", 71 [49] = "EC[31:26] == 110001, Exception from a Breakpoint or Vector Catch debug event", 72 [50] = "EC[31:26] == 110010, Exception from a Software Step debug event", 73 [51] = "EC[31:26] == 110011, Exception from a Software Step debug event", 74 [52] = "EC[31:26] == 110100, Exception from a Watchpoint debug event", 75 [53] = "EC[31:26] == 110101, Exception from a Watchpoint debug event", 76 [56] = "EC[31:26] == 111000, Exception from execution of a Software Breakpoint instructio", 77 }; 78 const char *esr_bits_il[] = { 79 "IL[25] == 0, 16-bit instruction trapped", 80 "IL[25] == 1, 32-bit instruction trapped", 81 }; 82 const char *daif_bits_f[] = { 83 "F[6] == 0, FIQ not masked", 84 "F[6] == 1, FIQ masked", 85 }; 86 const char *daif_bits_i[] = { 87 "I[7] == 0, IRQ not masked", 88 "I[7] == 1, IRQ masked", 89 }; 90 const char *daif_bits_a[] = { 91 "A[8] == 0, ABORT not masked", 92 "A[8] == 1, ABORT masked", 93 }; 94 const char *daif_bits_d[] = { 95 "D[9] == 0, DBG not masked", 96 "D[9] == 1, DBG masked", 97 }; 98 const char *spsr_bits_m_aarch32[] = { 99 [0] = "M[3:0] == 0000, User", 100 [1] = "M[3:0] == 0001, FIQ", 101 [2] = "M[3:0] == 0010, IRQ", 102 [3] = "M[3:0] == 0011, Supervisor", 103 [6] = "M[3:0] == 0110, Monitor", 104 [7] = "M[3:0] == 0111, Abort", 105 [10] = "M[3:0] == 1010, Hyp", 106 [11] = "M[3:0] == 1011, Undefined", 107 [15] = "M[3:0] == 1111, System", 108 }; 109 const char *spsr_bits_m_aarch64[] = { 110 [0] = "M[3:0] == 0000, EL0t", 111 [4] = "M[3:0] == 0100, EL1t", 112 [5] = "M[3:0] == 0101, EL1h", 113 [8] = "M[3:0] == 1000, EL2t", 114 [9] = "M[3:0] == 1001, EL2h", 115 [10] = "M[3:0] == 1100, EL3t", 116 [11] = "M[3:0] == 1101, EL3h", 117 }; 118 const char *spsr_bits_m[] = { 119 "M[4] == 0, Exception taken from AArch64", 120 "M[4] == 1, Exception taken from AArch32", 121 }; 122 const char *spsr_bits_f[] = { 123 "F[6] == 0, FIQ not masked", 124 "F[6] == 1, FIQ masked", 125 }; 126 const char *spsr_bits_i[] = { 127 "I[7] == 0, IRQ not masked", 128 "I[7] == 1, IRQ masked", 129 }; 130 const char *spsr_bits_a[] = { 131 "A[8] == 0, ABORT not masked", 132 "A[8] == 1, ABORT masked", 133 }; 134 const char *spsr_bits_d[] = { 135 "D[9] == 0, DBG not masked", 136 "D[9] == 1, DBG masked", 137 }; 138 const char *sctlr_bits_i[] = { 139 "I[12] == 0, Icache disabled", 140 "I[12] == 1, Icaches enabled", 141 }; 142 const char *sctlr_bits_c[] = { 143 "C[2] == 0, Dcache disabled", 144 "C[2] == 1, Dcache enabled", 145 }; 146 const char *sctlr_bits_m[] = { 147 "M[0] == 0, MMU disabled", 148 "M[0] == 1, MMU enabled", 149 }; 150 151 printf("* Relocate offset = %016lx\n", gd->reloc_off); 152 153 if (gd->flags & GD_FLG_RELOC) { 154 printf("* ELR(PC) = %016lx\n", regs->elr - gd->reloc_off); 155 printf("* LR = %016lx\n", regs->regs[30] - gd->reloc_off); 156 } else { 157 printf("* ELR(PC) = %016lx\n", regs->elr); 158 printf("* LR = %016lx\n", regs->regs[30]); 159 } 160 161 printf("* SP = %016lx\n", regs->sp); 162 printf("\n"); 163 164 /* 165 * System registers 166 */ 167 /* ESR_EL2 */ 168 printf("* ESR_EL%d = %016lx\n", el, regs->esr); 169 printf("\t%s\n", esr_bits_ec[REG_BITS(regs->esr, 26, 0x3f)]); 170 printf("\t%s\n", esr_bits_il[REG_BITS(regs->esr, 25, 0x01)]); 171 printf("\n"); 172 /* DAIF */ 173 printf("* DAIF = %016lx\n", regs->daif); 174 printf("\t%s\n", daif_bits_d[REG_BITS(regs->daif, 9, 0x1)]); 175 printf("\t%s\n", daif_bits_a[REG_BITS(regs->daif, 8, 0x1)]); 176 printf("\t%s\n", daif_bits_i[REG_BITS(regs->daif, 7, 0x1)]); 177 printf("\t%s\n", daif_bits_f[REG_BITS(regs->daif, 6, 0x1)]); 178 printf("\n"); 179 /* SPSR_ELx */ 180 printf("* SPSR_EL%d = %016lx\n", el, regs->spsr); 181 printf("\t%s\n", spsr_bits_d[REG_BITS(regs->spsr, 9, 0x1)]); 182 printf("\t%s\n", spsr_bits_a[REG_BITS(regs->spsr, 8, 0x1)]); 183 printf("\t%s\n", spsr_bits_i[REG_BITS(regs->spsr, 7, 0x1)]); 184 printf("\t%s\n", spsr_bits_f[REG_BITS(regs->spsr, 6, 0x1)]); 185 printf("\t%s\n", spsr_bits_m[REG_BITS(regs->spsr, 4, 0x1)]); 186 if (REG_BITS(regs->spsr, 4, 0x1)) 187 printf("\t%s\n", spsr_bits_m_aarch32[REG_BITS(regs->spsr, 0, 0xf)]); 188 else 189 printf("\t%s\n", spsr_bits_m_aarch64[REG_BITS(regs->spsr, 0, 0xf)]); 190 printf("\n"); 191 /* SCTLR_EL2 */ 192 printf("* SCTLR_EL%d = %016lx\n", el, regs->sctlr); 193 printf("\t%s\n", sctlr_bits_i[REG_BITS(regs->sctlr, 12, 0x1)]); 194 printf("\t%s\n", sctlr_bits_c[REG_BITS(regs->sctlr, 2, 0x1)]); 195 printf("\t%s\n", sctlr_bits_m[REG_BITS(regs->sctlr, 0, 0x1)]); 196 printf("\n"); 197 198 /* Other */ 199 if (el >= 2) 200 printf("* %s = %016lx\n", h_scr_name[el], regs->hcr); 201 printf("* VBAR_EL%d = %016lx\n", el, regs->vbar); 202 printf("* TTBR0_EL%d = %016lx\n", el, regs->ttbr0); 203 printf("\n"); 204 205 for (i = 0; i < 29; i += 2) 206 printf("x%-2d: %016lx x%-2d: %016lx\n", 207 i, regs->regs[i], i+1, regs->regs[i+1]); 208 printf("\n"); 209 } 210 211 #else 212 void show_regs(struct pt_regs *regs) 213 { 214 int i; 215 216 if (gd->flags & GD_FLG_RELOC) { 217 printf("ELR: %lx\n", regs->elr - gd->reloc_off); 218 printf("LR: %lx\n", regs->regs[30] - gd->reloc_off); 219 } else { 220 printf("ELR: %lx\n", regs->elr); 221 printf("LR: %lx\n", regs->regs[30]); 222 } 223 for (i = 0; i < 29; i += 2) 224 printf("x%-2d: %016lx x%-2d: %016lx\n", 225 i, regs->regs[i], i+1, regs->regs[i+1]); 226 printf("\n"); 227 } 228 #endif 229 230 /* 231 * do_bad_sync handles the impossible case in the Synchronous Abort vector. 232 */ 233 void do_bad_sync(struct pt_regs *pt_regs, unsigned int esr) 234 { 235 efi_restore_gd(); 236 printf("Bad mode in \"Synchronous Abort\" handler, esr 0x%08x\n", esr); 237 show_regs(pt_regs); 238 panic("Resetting CPU ...\n"); 239 } 240 241 /* 242 * do_bad_irq handles the impossible case in the Irq vector. 243 */ 244 void do_bad_irq(struct pt_regs *pt_regs, unsigned int esr) 245 { 246 efi_restore_gd(); 247 printf("Bad mode in \"Irq\" handler, esr 0x%08x\n", esr); 248 show_regs(pt_regs); 249 panic("Resetting CPU ...\n"); 250 } 251 252 /* 253 * do_bad_fiq handles the impossible case in the Fiq vector. 254 */ 255 void do_bad_fiq(struct pt_regs *pt_regs, unsigned int esr) 256 { 257 efi_restore_gd(); 258 printf("Bad mode in \"Fiq\" handler, esr 0x%08x\n", esr); 259 show_regs(pt_regs); 260 panic("Resetting CPU ...\n"); 261 } 262 263 /* 264 * do_bad_error handles the impossible case in the Error vector. 265 */ 266 void do_bad_error(struct pt_regs *pt_regs, unsigned int esr) 267 { 268 efi_restore_gd(); 269 printf("Bad mode in \"Error\" handler, esr 0x%08x\n", esr); 270 show_regs(pt_regs); 271 panic("Resetting CPU ...\n"); 272 } 273 274 /* 275 * do_sync handles the Synchronous Abort exception. 276 */ 277 void do_sync(struct pt_regs *pt_regs, unsigned int esr) 278 { 279 efi_restore_gd(); 280 printf("\"Synchronous Abort\" handler, esr 0x%08x\n", esr); 281 show_regs(pt_regs); 282 panic("Resetting CPU ...\n"); 283 } 284 285 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_IRQ) 286 /* 287 * do_irq handles the Irq exception. 288 */ 289 void do_irq(struct pt_regs *pt_regs, unsigned int esr) 290 { 291 efi_restore_gd(); 292 printf("\"Irq\" handler, esr 0x%08x\n", esr); 293 show_regs(pt_regs); 294 panic("Resetting CPU ...\n"); 295 } 296 #endif 297 298 /* 299 * do_fiq handles the Fiq exception. 300 */ 301 void do_fiq(struct pt_regs *pt_regs, unsigned int esr) 302 { 303 efi_restore_gd(); 304 printf("\"Fiq\" handler, esr 0x%08x\n", esr); 305 show_regs(pt_regs); 306 panic("Resetting CPU ...\n"); 307 } 308 309 /* 310 * do_error handles the Error exception. 311 * Errors are more likely to be processor specific, 312 * it is defined with weak attribute and can be redefined 313 * in processor specific code. 314 */ 315 void __weak do_error(struct pt_regs *pt_regs, unsigned int esr) 316 { 317 efi_restore_gd(); 318 printf("\"Error\" handler, esr 0x%08x\n", esr); 319 show_regs(pt_regs); 320 panic("Resetting CPU ...\n"); 321 } 322