1/* 2 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/clock/rk3228-cru.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 interrupt-parent = <&gic>; 19 20 aliases { 21 serial0 = &uart0; 22 serial1 = &uart1; 23 serial2 = &uart2; 24 mmc0 = &emmc; 25 mmc1 = &sdmmc; 26 }; 27 28 cpus { 29 #address-cells = <1>; 30 #size-cells = <0>; 31 32 cpu0: cpu@f00 { 33 device_type = "cpu"; 34 compatible = "arm,cortex-a7"; 35 reg = <0xf00>; 36 resets = <&cru SRST_CORE0>; 37 operating-points = < 38 /* KHz uV */ 39 816000 1000000 40 >; 41 #cooling-cells = <2>; /* min followed by max */ 42 clock-latency = <40000>; 43 clocks = <&cru ARMCLK>; 44 }; 45 46 cpu1: cpu@f01 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a7"; 49 reg = <0xf01>; 50 resets = <&cru SRST_CORE1>; 51 }; 52 53 cpu2: cpu@f02 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a7"; 56 reg = <0xf02>; 57 resets = <&cru SRST_CORE2>; 58 }; 59 60 cpu3: cpu@f03 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a7"; 63 reg = <0xf03>; 64 resets = <&cru SRST_CORE3>; 65 }; 66 }; 67 68 amba { 69 compatible = "simple-bus"; 70 #address-cells = <1>; 71 #size-cells = <1>; 72 ranges; 73 74 pdma: pdma@110f0000 { 75 compatible = "arm,pl330", "arm,primecell"; 76 reg = <0x110f0000 0x4000>; 77 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 79 #dma-cells = <1>; 80 clocks = <&cru ACLK_DMAC>; 81 clock-names = "apb_pclk"; 82 }; 83 }; 84 85 arm-pmu { 86 compatible = "arm,cortex-a7-pmu"; 87 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 88 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 89 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 90 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 91 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 92 }; 93 94 timer { 95 compatible = "arm,armv7-timer"; 96 arm,cpu-registers-not-fw-configured; 97 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 98 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 99 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 100 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 101 clock-frequency = <24000000>; 102 }; 103 104 xin24m: oscillator { 105 compatible = "fixed-clock"; 106 clock-frequency = <24000000>; 107 clock-output-names = "xin24m"; 108 #clock-cells = <0>; 109 }; 110 111 bus_intmem@10080000 { 112 compatible = "mmio-sram"; 113 reg = <0x10080000 0x9000>; 114 #address-cells = <1>; 115 #size-cells = <1>; 116 ranges = <0 0x10080000 0x9000>; 117 smp-sram@0 { 118 compatible = "rockchip,rk322x-smp-sram"; 119 reg = <0x00 0x10>; 120 }; 121 ddr_sram: ddr-sram@1000 { 122 compatible = "rockchip,rk322x-ddr-sram"; 123 reg = <0x1000 0x8000>; 124 }; 125 }; 126 127 i2s1: i2s1@100b0000 { 128 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; 129 reg = <0x100b0000 0x4000>; 130 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 131 #address-cells = <1>; 132 #size-cells = <0>; 133 clock-names = "i2s_clk", "i2s_hclk"; 134 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; 135 dmas = <&pdma 14>, <&pdma 15>; 136 dma-names = "tx", "rx"; 137 pinctrl-names = "default"; 138 pinctrl-0 = <&i2s1_bus>; 139 status = "disabled"; 140 }; 141 142 i2s0: i2s0@100c0000 { 143 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; 144 reg = <0x100c0000 0x4000>; 145 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 146 #address-cells = <1>; 147 #size-cells = <0>; 148 clock-names = "i2s_clk", "i2s_hclk"; 149 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; 150 dmas = <&pdma 11>, <&pdma 12>; 151 dma-names = "tx", "rx"; 152 status = "disabled"; 153 }; 154 155 i2s2: i2s2@100e0000 { 156 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; 157 reg = <0x100e0000 0x4000>; 158 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 159 #address-cells = <1>; 160 #size-cells = <0>; 161 clock-names = "i2s_clk", "i2s_hclk"; 162 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; 163 dmas = <&pdma 0>, <&pdma 1>; 164 dma-names = "tx", "rx"; 165 status = "disabled"; 166 }; 167 168 grf: syscon@11000000 { 169 u-boot,dm-pre-reloc; 170 compatible = "rockchip,rk3228-grf", "syscon"; 171 reg = <0x11000000 0x1000>; 172 #address-cells = <1>; 173 #size-cells = <1>; 174 175 u2phy0: usb2-phy@760 { 176 compatible = "rockchip,rk322x-usb2phy"; 177 reg = <0x0760 0x0c>; 178 status = "disabled"; 179 180 u2phy0_otg: otg-port { 181 #phy-cells = <0>; 182 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 185 interrupt-names = "otg-bvalid", "otg-id", 186 "linestate"; 187 status = "disabled"; 188 }; 189 190 u2phy0_host: host-port { 191 #phy-cells = <0>; 192 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 193 interrupt-names = "linestate"; 194 status = "disabled"; 195 }; 196 }; 197 198 u2phy1: usb2-phy@800 { 199 compatible = "rockchip,rk322x-usb2phy"; 200 reg = <0x0800 0x0c>; 201 status = "disabled"; 202 203 u2phy1_otg: otg-port { 204 #phy-cells = <0>; 205 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 206 interrupt-names = "linestate"; 207 status = "disabled"; 208 }; 209 210 u2phy1_host: host-port { 211 #phy-cells = <0>; 212 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 213 interrupt-names = "linestate"; 214 status = "disabled"; 215 }; 216 }; 217 }; 218 219 uart0: serial@11010000 { 220 compatible = "snps,dw-apb-uart"; 221 reg = <0x11010000 0x100>; 222 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 223 clock-frequency = <24000000>; 224 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 225 clock-names = "baudclk", "apb_pclk"; 226 pinctrl-names = "default"; 227 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 228 reg-shift = <2>; 229 reg-io-width = <4>; 230 status = "disabled"; 231 }; 232 233 uart1: serial@11020000 { 234 compatible = "snps,dw-apb-uart"; 235 reg = <0x11020000 0x100>; 236 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 237 clock-frequency = <24000000>; 238 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 239 clock-names = "baudclk", "apb_pclk"; 240 pinctrl-names = "default"; 241 pinctrl-0 = <&uart1_xfer>; 242 reg-shift = <2>; 243 reg-io-width = <4>; 244 status = "disabled"; 245 }; 246 247 uart2: serial@11030000 { 248 compatible = "snps,dw-apb-uart"; 249 reg = <0x11030000 0x100>; 250 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 251 clock-frequency = <24000000>; 252 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 253 clock-names = "baudclk", "apb_pclk"; 254 pinctrl-names = "default"; 255 pinctrl-0 = <&uart21_xfer>; 256 reg-shift = <2>; 257 reg-io-width = <4>; 258 status = "disabled"; 259 }; 260 261 efuse: efuse@11040000 { 262 compatible = "rockchip,rk322x-efuse"; 263 reg = <0x11040000 0x20>; 264 #address-cells = <1>; 265 #size-cells = <1>; 266 clocks = <&cru PCLK_EFUSE_256>; 267 clock-names = "pclk_efuse"; 268 269 /* Data cells */ 270 efuse_id: id@7 { 271 reg = <0x7 0x10>; 272 }; 273 cpu_leakage: cpu_leakage@17 { 274 reg = <0x17 0x1>; 275 }; 276 }; 277 278 i2c0: i2c@11050000 { 279 compatible = "rockchip,rk3228-i2c"; 280 reg = <0x11050000 0x1000>; 281 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 282 #address-cells = <1>; 283 #size-cells = <0>; 284 clock-names = "i2c"; 285 clocks = <&cru PCLK_I2C0>; 286 pinctrl-names = "default"; 287 pinctrl-0 = <&i2c0_xfer>; 288 status = "disabled"; 289 }; 290 291 i2c1: i2c@11060000 { 292 compatible = "rockchip,rk3228-i2c"; 293 reg = <0x11060000 0x1000>; 294 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 295 #address-cells = <1>; 296 #size-cells = <0>; 297 clock-names = "i2c"; 298 clocks = <&cru PCLK_I2C1>; 299 pinctrl-names = "default"; 300 pinctrl-0 = <&i2c1_xfer>; 301 status = "disabled"; 302 }; 303 304 i2c2: i2c@11070000 { 305 compatible = "rockchip,rk3228-i2c"; 306 reg = <0x11070000 0x1000>; 307 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 308 #address-cells = <1>; 309 #size-cells = <0>; 310 clock-names = "i2c"; 311 clocks = <&cru PCLK_I2C2>; 312 pinctrl-names = "default"; 313 pinctrl-0 = <&i2c2_xfer>; 314 status = "disabled"; 315 }; 316 317 i2c3: i2c@11080000 { 318 compatible = "rockchip,rk3228-i2c"; 319 reg = <0x11080000 0x1000>; 320 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 321 #address-cells = <1>; 322 #size-cells = <0>; 323 clock-names = "i2c"; 324 clocks = <&cru PCLK_I2C3>; 325 pinctrl-names = "default"; 326 pinctrl-0 = <&i2c3_xfer>; 327 status = "disabled"; 328 }; 329 330 pwm0: pwm@110b0000 { 331 compatible = "rockchip,rk3288-pwm"; 332 reg = <0x110b0000 0x10>; 333 #pwm-cells = <3>; 334 clocks = <&cru PCLK_PWM>; 335 clock-names = "pwm"; 336 pinctrl-names = "active"; 337 pinctrl-0 = <&pwm0_pin>; 338 status = "disabled"; 339 }; 340 341 pwm1: pwm@110b0010 { 342 compatible = "rockchip,rk3288-pwm"; 343 reg = <0x110b0010 0x10>; 344 #pwm-cells = <3>; 345 clocks = <&cru PCLK_PWM>; 346 clock-names = "pwm"; 347 pinctrl-names = "active"; 348 pinctrl-0 = <&pwm1_pin>; 349 status = "disabled"; 350 }; 351 352 pwm2: pwm@110b0020 { 353 compatible = "rockchip,rk3288-pwm"; 354 reg = <0x110b0020 0x10>; 355 #pwm-cells = <3>; 356 clocks = <&cru PCLK_PWM>; 357 clock-names = "pwm"; 358 pinctrl-names = "active"; 359 pinctrl-0 = <&pwm2_pin>; 360 status = "disabled"; 361 }; 362 363 pwm3: pwm@110b0030 { 364 compatible = "rockchip,rk3288-pwm"; 365 reg = <0x110b0030 0x10>; 366 #pwm-cells = <2>; 367 clocks = <&cru PCLK_PWM>; 368 clock-names = "pwm"; 369 pinctrl-names = "active"; 370 pinctrl-0 = <&pwm3_pin>; 371 status = "disabled"; 372 }; 373 374 timer: timer@110c0000 { 375 compatible = "rockchip,rk3288-timer"; 376 reg = <0x110c0000 0x20>; 377 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 378 clocks = <&xin24m>, <&cru PCLK_TIMER>; 379 clock-names = "timer", "pclk"; 380 }; 381 382 cru: clock-controller@110e0000 { 383 u-boot,dm-pre-reloc; 384 compatible = "rockchip,rk3228-cru"; 385 reg = <0x110e0000 0x1000>; 386 rockchip,grf = <&grf>; 387 #clock-cells = <1>; 388 #reset-cells = <1>; 389 assigned-clocks = <&cru PLL_GPLL>; 390 assigned-clock-rates = <594000000>; 391 }; 392 393 thermal-zones { 394 cpu_thermal: cpu-thermal { 395 polling-delay-passive = <100>; /* milliseconds */ 396 polling-delay = <5000>; /* milliseconds */ 397 398 thermal-sensors = <&tsadc 0>; 399 400 trips { 401 cpu_alert0: cpu_alert0 { 402 temperature = <70000>; /* millicelsius */ 403 hysteresis = <2000>; /* millicelsius */ 404 type = "passive"; 405 }; 406 cpu_alert1: cpu_alert1 { 407 temperature = <75000>; /* millicelsius */ 408 hysteresis = <2000>; /* millicelsius */ 409 type = "passive"; 410 }; 411 cpu_crit: cpu_crit { 412 temperature = <90000>; /* millicelsius */ 413 hysteresis = <2000>; /* millicelsius */ 414 type = "critical"; 415 }; 416 }; 417 418 cooling-maps { 419 map0 { 420 trip = <&cpu_alert0>; 421 cooling-device = 422 <&cpu0 THERMAL_NO_LIMIT 6>; 423 }; 424 map1 { 425 trip = <&cpu_alert1>; 426 cooling-device = 427 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 428 }; 429 }; 430 }; 431 }; 432 433 tsadc: tsadc@11150000 { 434 compatible = "rockchip,rk3228-tsadc"; 435 reg = <0x11150000 0x100>; 436 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 437 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 438 clock-names = "tsadc", "apb_pclk"; 439 resets = <&cru SRST_TSADC>; 440 reset-names = "tsadc-apb"; 441 pinctrl-names = "init", "default", "sleep"; 442 pinctrl-0 = <&otp_gpio>; 443 pinctrl-1 = <&otp_out>; 444 pinctrl-2 = <&otp_gpio>; 445 #thermal-sensor-cells = <0>; 446 rockchip,hw-tshut-temp = <95000>; 447 status = "disabled"; 448 }; 449 450 sdmmc: dwmmc@30000000 { 451 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; 452 reg = <0x30000000 0x4000>; 453 max-frequency = <150000000>; 454 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 455 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 456 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 457 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 458 fifo-depth = <0x100>; 459 pinctrl-names = "default"; 460 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; 461 status = "disabled"; 462 }; 463 464 sdio: dwmmc@30010000 { 465 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; 466 reg = <0x30010000 0x4000>; 467 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 468 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 469 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 470 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 471 fifo-depth = <0x100>; 472 pinctrl-names = "default"; 473 pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>; 474 status = "disabled"; 475 }; 476 477 emmc: dwmmc@30020000 { 478 compatible = "rockchip,rk3288-dw-mshc"; 479 reg = <0x30020000 0x4000>; 480 max-frequency = <150000000>; 481 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 482 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 483 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 484 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 485 bus-width = <8>; 486 default-sample-phase = <158>; 487 num-slots = <1>; 488 fifo-depth = <0x100>; 489 pinctrl-names = "default"; 490 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; 491 resets = <&cru SRST_EMMC>; 492 reset-names = "reset"; 493 status = "disabled"; 494 }; 495 496 usb20_otg: usb@30040000 { 497 compatible = "rockchip,rk3229-usb", "rockchip,rk3288-usb", 498 "snps,dwc2"; 499 reg = <0x30040000 0x40000>; 500 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 501 hnp-srp-disable; 502 dr_mode = "otg"; 503 phys = <&u2phy0_otg>; 504 phy-names = "usb2-phy"; 505 status = "disabled"; 506 }; 507 508 gmac: ethernet@30200000 { 509 compatible = "rockchip,rk3228-gmac"; 510 reg = <0x30200000 0x10000>; 511 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 512 interrupt-names = "macirq"; 513 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, 514 <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>, 515 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, 516 <&cru PCLK_GMAC>; 517 clock-names = "stmmaceth", "mac_clk_rx", 518 "mac_clk_tx", "clk_mac_ref", 519 "clk_mac_refout", "aclk_mac", 520 "pclk_mac"; 521 resets = <&cru SRST_GMAC>; 522 reset-names = "stmmaceth"; 523 rockchip,grf = <&grf>; 524 status = "disabled"; 525 }; 526 527 gic: interrupt-controller@32010000 { 528 compatible = "arm,gic-400"; 529 interrupt-controller; 530 #interrupt-cells = <3>; 531 #address-cells = <0>; 532 533 reg = <0x32011000 0x1000>, 534 <0x32012000 0x2000>, 535 <0x32014000 0x2000>, 536 <0x32016000 0x2000>; 537 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 538 }; 539 540 pinctrl: pinctrl { 541 compatible = "rockchip,rk3228-pinctrl"; 542 rockchip,grf = <&grf>; 543 #address-cells = <1>; 544 #size-cells = <1>; 545 ranges; 546 547 gpio0: gpio0@11110000 { 548 compatible = "rockchip,gpio-bank"; 549 reg = <0x11110000 0x100>; 550 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 551 clocks = <&cru PCLK_GPIO0>; 552 553 gpio-controller; 554 #gpio-cells = <2>; 555 556 interrupt-controller; 557 #interrupt-cells = <2>; 558 }; 559 560 gpio1: gpio1@11120000 { 561 compatible = "rockchip,gpio-bank"; 562 reg = <0x11120000 0x100>; 563 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 564 clocks = <&cru PCLK_GPIO1>; 565 566 gpio-controller; 567 #gpio-cells = <2>; 568 569 interrupt-controller; 570 #interrupt-cells = <2>; 571 }; 572 573 gpio2: gpio2@11130000 { 574 compatible = "rockchip,gpio-bank"; 575 reg = <0x11130000 0x100>; 576 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 577 clocks = <&cru PCLK_GPIO2>; 578 579 gpio-controller; 580 #gpio-cells = <2>; 581 582 interrupt-controller; 583 #interrupt-cells = <2>; 584 }; 585 586 gpio3: gpio3@11140000 { 587 compatible = "rockchip,gpio-bank"; 588 reg = <0x11140000 0x100>; 589 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 590 clocks = <&cru PCLK_GPIO3>; 591 592 gpio-controller; 593 #gpio-cells = <2>; 594 595 interrupt-controller; 596 #interrupt-cells = <2>; 597 }; 598 599 pcfg_pull_up: pcfg-pull-up { 600 bias-pull-up; 601 }; 602 603 pcfg_pull_down: pcfg-pull-down { 604 bias-pull-down; 605 }; 606 607 pcfg_pull_none: pcfg-pull-none { 608 bias-disable; 609 }; 610 611 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma { 612 drive-strength = <12>; 613 }; 614 615 sdmmc { 616 sdmmc_clk: sdmmc-clk { 617 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; 618 }; 619 620 sdmmc_cmd: sdmmc-cmd { 621 rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; 622 }; 623 624 sdmmc_bus4: sdmmc-bus4 { 625 rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 626 <1 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 627 <1 20 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 628 <1 21 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; 629 }; 630 }; 631 632 sdio { 633 sdio_clk: sdio-clk { 634 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; 635 }; 636 637 sdio_cmd: sdio-cmd { 638 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; 639 }; 640 641 sdio_bus4: sdio-bus4 { 642 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 643 <3 3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 644 <3 4 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 645 <3 5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; 646 }; 647 }; 648 649 emmc { 650 emmc_clk: emmc-clk { 651 rockchip,pins = <2 RK_PA7 RK_FUNC_2 &pcfg_pull_none>; 652 }; 653 654 emmc_cmd: emmc-cmd { 655 rockchip,pins = <1 RK_PC6 RK_FUNC_2 &pcfg_pull_none>; 656 }; 657 658 emmc_bus8: emmc-bus8 { 659 rockchip,pins = <1 RK_PD0 RK_FUNC_2 &pcfg_pull_none>, 660 <1 RK_PD1 RK_FUNC_2 &pcfg_pull_none>, 661 <1 RK_PD2 RK_FUNC_2 &pcfg_pull_none>, 662 <1 RK_PD3 RK_FUNC_2 &pcfg_pull_none>, 663 <1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>, 664 <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>, 665 <1 RK_PD6 RK_FUNC_2 &pcfg_pull_none>, 666 <1 RK_PD7 RK_FUNC_2 &pcfg_pull_none>; 667 }; 668 }; 669 670 gmac { 671 rgmii_pins: rgmii-pins { 672 rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, 673 <2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, 674 <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>, 675 <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 676 <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 677 <2 RK_PC6 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 678 <2 RK_PC7 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 679 <2 RK_PB1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 680 <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 681 <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, 682 <2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>, 683 <2 RK_PC5 RK_FUNC_2 &pcfg_pull_none>, 684 <2 RK_PC4 RK_FUNC_2 &pcfg_pull_none>, 685 <2 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, 686 <2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>; 687 }; 688 689 rmii_pins: rmii-pins { 690 rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, 691 <2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, 692 <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>, 693 <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 694 <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 695 <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 696 <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, 697 <2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>, 698 <2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, 699 <2 RK_PB7 RK_FUNC_1 &pcfg_pull_none>; 700 }; 701 702 phy_pins: phy-pins { 703 rockchip,pins = <2 RK_PB6 RK_FUNC_2 &pcfg_pull_none>, 704 <2 RK_PB0 RK_FUNC_2 &pcfg_pull_none>; 705 }; 706 }; 707 708 i2c0 { 709 i2c0_xfer: i2c0-xfer { 710 rockchip,pins = <0 RK_PA0 RK_FUNC_1 &pcfg_pull_none>, 711 <0 RK_PA1 RK_FUNC_1 &pcfg_pull_none>; 712 }; 713 }; 714 715 i2c1 { 716 i2c1_xfer: i2c1-xfer { 717 rockchip,pins = <0 RK_PA2 RK_FUNC_1 &pcfg_pull_none>, 718 <0 RK_PA3 RK_FUNC_1 &pcfg_pull_none>; 719 }; 720 }; 721 722 i2c2 { 723 i2c2_xfer: i2c2-xfer { 724 rockchip,pins = <2 RK_PC4 RK_FUNC_1 &pcfg_pull_none>, 725 <2 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; 726 }; 727 }; 728 729 i2c3 { 730 i2c3_xfer: i2c3-xfer { 731 rockchip,pins = <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, 732 <0 RK_PA7 RK_FUNC_1 &pcfg_pull_none>; 733 }; 734 }; 735 736 i2s1 { 737 i2s1_bus: i2s1-bus { 738 rockchip,pins = <0 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, 739 <0 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, 740 <0 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, 741 <0 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, 742 <0 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, 743 <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, 744 <1 RK_PA2 RK_FUNC_1 &pcfg_pull_none>, 745 <1 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, 746 <1 RK_PA5 RK_FUNC_1 &pcfg_pull_none>; 747 }; 748 }; 749 750 pwm0 { 751 pwm0_pin: pwm0-pin { 752 rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; 753 }; 754 }; 755 756 pwm1 { 757 pwm1_pin: pwm1-pin { 758 rockchip,pins = <0 RK_PD6 RK_FUNC_2 &pcfg_pull_none>; 759 }; 760 }; 761 762 pwm2 { 763 pwm2_pin: pwm2-pin { 764 rockchip,pins = <1 RK_PB4 RK_FUNC_2 &pcfg_pull_none>; 765 }; 766 }; 767 768 pwm3 { 769 pwm3_pin: pwm3-pin { 770 rockchip,pins = <1 RK_PB3 RK_FUNC_2 &pcfg_pull_none>; 771 }; 772 }; 773 774 tsadc { 775 otp_gpio: otp-gpio { 776 rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 777 }; 778 779 otp_out: otp-out { 780 rockchip,pins = <0 RK_PD0 RK_FUNC_2 &pcfg_pull_none>; 781 }; 782 }; 783 784 uart0 { 785 uart0_xfer: uart0-xfer { 786 rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_none>, 787 <2 RK_PD3 RK_FUNC_1 &pcfg_pull_none>; 788 }; 789 790 uart0_cts: uart0-cts { 791 rockchip,pins = <2 RK_PD5 RK_FUNC_1 &pcfg_pull_none>; 792 }; 793 794 uart0_rts: uart0-rts { 795 rockchip,pins = <0 RK_PC1 RK_FUNC_1 &pcfg_pull_none>; 796 }; 797 }; 798 799 uart1 { 800 uart1_xfer: uart1-xfer { 801 rockchip,pins = <1 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, 802 <1 RK_PB2 RK_FUNC_1 &pcfg_pull_none>; 803 }; 804 805 uart1_cts: uart1-cts { 806 rockchip,pins = <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>; 807 }; 808 809 uart1_rts: uart1-rts { 810 rockchip,pins = <1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>; 811 }; 812 }; 813 814 uart2 { 815 uart2_xfer: uart2-xfer { 816 rockchip,pins = <1 RK_PC2 RK_FUNC_2 &pcfg_pull_up>, 817 <1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>; 818 }; 819 820 uart2_cts: uart2-cts { 821 rockchip,pins = <0 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; 822 }; 823 824 uart2_rts: uart2-rts { 825 rockchip,pins = <0 RK_PD0 RK_FUNC_1 &pcfg_pull_none>; 826 }; 827 }; 828 829 uart2-1 { 830 uart21_xfer: uart21-xfer { 831 rockchip,pins = <1 10 RK_FUNC_2 &pcfg_pull_up>, 832 <1 9 RK_FUNC_2 &pcfg_pull_none>; 833 }; 834 }; 835 }; 836 837 dmc: dmc@11200000 { 838 u-boot,dm-pre-reloc; 839 compatible = "rockchip,rk3228-dmc", "syscon"; 840 rockchip,cru = <&cru>; 841 rockchip,grf = <&grf>; 842 rockchip,msch = <&service_msch>; 843 reg = <0x11200000 0x3fc 844 0x12000000 0x400>; 845 rockchip,sram = <&ddr_sram>; 846 }; 847 848 service_msch: syscon@31090000 { 849 u-boot,dm-pre-reloc; 850 compatible = "rockchip,rk3228-msch", "syscon"; 851 reg = <0x31090000 0x2000>; 852 }; 853}; 854