refactor(cpus): convert Rainier to use errata framework

This involves replacing:
* the reset_func with the standard cpu_reset_func_{start,end} to apply
errata automatically
* the <cpu>_errata_r

refactor(cpus): convert Rainier to use errata framework

This involves replacing:
* the reset_func with the standard cpu_reset_func_{start,end} to apply
errata automatically
* the <cpu>_errata_report with the errata_report_shim to report errata
automatically
as well as specifically related to single errata for this CPU:
* the prologue with the workaround_<type>_start to do the checks and
framework registration automatically
* the epilogue with the workaround_<type>_end
* the checker function with the check_erratum_<type> to make it more
descriptive

Change-Id: I31cacbbdd4caa12b32e2c65ec456b0ab6b1a9101
Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>

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refactor(cpus): convert QEMU Max to use the errata framework

This involves replacing:
* the <cpu>_errata_report with the errata_report_shim to report errata
automatically.

Change-Id: I78b65052dcfc1

refactor(cpus): convert QEMU Max to use the errata framework

This involves replacing:
* the <cpu>_errata_report with the errata_report_shim to report errata
automatically.

Change-Id: I78b65052dcfc1f29b7dec443bd0aaf67d0efb4eb
Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>

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docs: move common build option from Arm-specific to common file

Moved common build options from Arm-specific file to common build
file.

Change-Id: If74b6223972ae3a6c11d9f9d2fbd8d2ee008b6e5
Signed-o

docs: move common build option from Arm-specific to common file

Moved common build options from Arm-specific file to common build
file.

Change-Id: If74b6223972ae3a6c11d9f9d2fbd8d2ee008b6e5
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge "refactor(build): merge march32/64 directives" into integration

Merge "refactor(fdt-wrappers): fix for unit testing errors" into integration

chore(xilinx): reorder include files as per TF-A guidelines

This commit reorders the include files in accordance with the
guidelines provided by Trusted Firmware-A (TF-A).
The include files are rear

chore(xilinx): reorder include files as per TF-A guidelines

This commit reorders the include files in accordance with the
guidelines provided by Trusted Firmware-A (TF-A).
The include files are rearranged to ensure a consistent and
organized structure in the codebase, facilitating better
readability and maintainability.

https: //trustedfirmware-a.readthedocs.io/en/latest/process/coding-style.html#headers-and-inclusion
https://git.trustedfirmware.org/ci/tf-a-ci-scripts.git/tree/script/static-checks/

For example, to run header check:
/tf-a-ci-scripts/script/static-checks/check-include-order.py --tree ${PWD} > Includefileorder.txt

Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: Ia5802722e69859596b94f31ec40755adbf7d865b

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refactor(fdt-wrappers): fix for unit testing errors

As the unit testing project uses the host machine GCC version to
compile, it is marking non-casted references as errors. This patch adds
the prope

refactor(fdt-wrappers): fix for unit testing errors

As the unit testing project uses the host machine GCC version to
compile, it is marking non-casted references as errors. This patch adds
the proper casting, so it compiles correctly for both Arm platforms and
host machines for unit testing.

Change-Id: Iee96e9117301ba28b6f164aac2cd36dc0f8b6be8
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>

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Merge "refactor(cpus): add Cortex-A32 errata framework information" into integration

refactor(cpus): add Cortex-A32 errata framework information

Replace errata_report with errata_report_shim.

Signed-off-by: Kathleen Capella <kathleen.capella@arm.com>
Change-Id: I5a43b0985f070f88747

refactor(cpus): add Cortex-A32 errata framework information

Replace errata_report with errata_report_shim.

Signed-off-by: Kathleen Capella <kathleen.capella@arm.com>
Change-Id: I5a43b0985f070f887474120eb8f5f7c01ba4af5f

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Merge "chore(xilinx): follow kernel doc format for functional documentation" into integration

Merge "docs: move the Juno-specific build option to Arm build option file" into integration

Merge "feat(fvp): allow configurable FVP Trusted SRAM size" into integration

Merge changes from topic "RAS_REFACTORING" into integration

* changes:
feat(board/rdn2): enable base element RAM RAS support on RD-N2 platform
feat(plat/arm): add memory map entry for CPER memor

Merge changes from topic "RAS_REFACTORING" into integration

* changes:
feat(board/rdn2): enable base element RAM RAS support on RD-N2 platform
feat(plat/arm): add memory map entry for CPER memory region
feat(plat/arm): firmware first error handling support for base RAMs
feat(plat/arm): update common platform RAS implementation
feat(plat/sgi): remove RAS setup call from common code
refactor(plat/sgi): deprecate DMC-620 RAS support
fix(plat/common): register PLAT_SP_PRI only if not already registered
fix(plat/sgi): update PLAT_SP_PRI macro definition
fix(plat/arm): add RAS_FFH_SUPPORT check for RAS EHF priority

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docs: remove deprecated tc0 from list of supported FVPs

TC0 is now a deprecated platform so remove it from the list
of supported FVPs as well as throwing an error if it is attempted
to be built.

Si

docs: remove deprecated tc0 from list of supported FVPs

TC0 is now a deprecated platform so remove it from the list
of supported FVPs as well as throwing an error if it is attempted
to be built.

Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
Change-Id: Id013fcecbe20700611463ef9eab8cb3ae09071cc

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feat(board/rdn2): enable base element RAM RAS support on RD-N2 platform

To enable firmware first support for base element RAMs on RD-N2 platform
this patch adds following support
- Includes SDEI hea

feat(board/rdn2): enable base element RAM RAS support on RD-N2 platform

To enable firmware first support for base element RAMs on RD-N2 platform
this patch adds following support
- Includes SDEI header to enable SDEI feature on RD-N2 platform.
- Add TZC configuration for CPER memory region for RD-N2 platform
variants. This region is marked for non-secure access as OSPM and
firmware need to access this region.
- Defines all base element RAM errors for RD-N2 platform variants.
- Defines a platform RAS event map and respective RAS config data
structure.

Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@arm.com>
Change-Id: Ideaed598f4924f3b9836d4d7e9ef76b9b7580b48

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feat(plat/arm): add memory map entry for CPER memory region

In firmware-first error handling approach the firmware consumes the
hardware fault interrupt, processes the error and notifies the fault t

feat(plat/arm): add memory map entry for CPER memory region

In firmware-first error handling approach the firmware consumes the
hardware fault interrupt, processes the error and notifies the fault to
OSPM. Firmware also shares the error information with the OSPM using a
standard format called Common Platform Error Record (CPER). The CPER is
placed in reserved memory that is shared between OSPM and the firmware.
On RD-N2 platform variants carve out a reserved memory space for the
CPER buffer. This patch enables CPER memory map region on RD-N2 platform
variants.

Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@arm.com>
Change-Id: Ib2645c90d4dc975f57bb143795f61f74f4f81494

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feat(plat/arm): firmware first error handling support for base RAMs

RD-N2 platform variants support base element RAM. The RAMs implement
ECC that detects ECC 1/2-bit errors and reports them via inte

feat(plat/arm): firmware first error handling support for base RAMs

RD-N2 platform variants support base element RAM. The RAMs implement
ECC that detects ECC 1/2-bit errors and reports them via interrupts. The
error information is reported as part of error record frames defined for
base element RAMs.

This patch provides reference error handler implementation to handle
1/2-bit RAS errors that occur on base element RAM's. On error event the
error handler reads the error records information and forwards the event
to secure partition. Secure partition creates a CPER record from this
error information. Finally the handler notifies the OS about the RAS
error using the SDEI notification mechanism.

Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@arm.com>
Change-Id: Ic209c714de6cd2d4c845198b03724940a2e1c240

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feat(plat/arm): update common platform RAS implementation

Refactor the RAS implementation to be used as common platform RAS
implementation for all the platforms. As part of refactoring this patch
ex

feat(plat/arm): update common platform RAS implementation

Refactor the RAS implementation to be used as common platform RAS
implementation for all the platforms. As part of refactoring this patch
extends support to configure interrupt as PPI interrupt type in addition
to currently supported SPI interrupts.

This patch defines a RAS config data structure to be defined by each
platform. The RAS config data structure carries the event map and size
information. Each platform code during initialization phase must define
this RAS config and register it with common platform RAS module.

Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@arm.com>
Change-Id: I4019b31386a7e9c197bcc83bdca47876ee854d0f

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feat(plat/sgi): remove RAS setup call from common code

In preparation of refactoring the support for platform error handling,
remove the call to RAS platform setup call from SGI specific common
code

feat(plat/sgi): remove RAS setup call from common code

In preparation of refactoring the support for platform error handling,
remove the call to RAS platform setup call from SGI specific common
code. This function will be called from platform code after the
refactoring.

Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@arm.com>
Change-Id: If4a87e0adf166b1c99bf5999f2f89efa6c7c6afc

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refactor(plat/sgi): deprecate DMC-620 RAS support

Remove DMC-620 specific code from platform RAS implementation. DMC-620
RAS support is not supported on SGI and RD platforms. The rest of the
platfor

refactor(plat/sgi): deprecate DMC-620 RAS support

Remove DMC-620 specific code from platform RAS implementation. DMC-620
RAS support is not supported on SGI and RD platforms. The rest of the
platform specific code maintained will be reused for supporting RAS
error handling on RD-N2 and later platforms.

Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@arm.com>
Change-Id: Ic03ae0e3298628330c5f7c25bafb0131f7b9d5b6

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fix(plat/common): register PLAT_SP_PRI only if not already registered

Build fails when RAS and SPM are enabled together and when PLAT_SP_PRI
EHF priority is equal to PLAT_RAS_PRI EHF priority.

So a

fix(plat/common): register PLAT_SP_PRI only if not already registered

Build fails when RAS and SPM are enabled together and when PLAT_SP_PRI
EHF priority is equal to PLAT_RAS_PRI EHF priority.

So add checks to register SPM priority with the EHF framework only when
the priority is different from RAS priority or when RAS is not enabled
on the platform.

Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@arm.com>
Change-Id: Ie14f82d27c9835b24890cc4561a56821881cf0ec

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fix(plat/sgi): update PLAT_SP_PRI macro definition

PLAT_SP_PRI EHF priority is defined to be same as the PLAT_RAS_PRI EHF
priority. But PLAT_RAS_PRIORITY is defined only if RAS_FFH_SUPPORT is
enable

fix(plat/sgi): update PLAT_SP_PRI macro definition

PLAT_SP_PRI EHF priority is defined to be same as the PLAT_RAS_PRI EHF
priority. But PLAT_RAS_PRIORITY is defined only if RAS_FFH_SUPPORT is
enabled. This patch defines priority value for PLAT_SP_PRI if
RAS_FFH_SUPPORT is not enabled.

Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@arm.com>
Change-Id: Ib3747317d2ecc088fbbf1f5f283726a330454c93

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fix(plat/arm): add RAS_FFH_SUPPORT check for RAS EHF priority

Define RAS EHF priority only if RAS_FFH_SUPPORT is enabled.

Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@arm.com>
Change-Id: I01

fix(plat/arm): add RAS_FFH_SUPPORT check for RAS EHF priority

Define RAS EHF priority only if RAS_FFH_SUPPORT is enabled.

Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@arm.com>
Change-Id: I0183a0af510337c8dfb9d12427541fa6c91bb4a5

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chore(xilinx): follow kernel doc format for functional documentation

For TF-A, there is no format specified for functional documentation.
For AMD-Xilinx platforms, following kernel-doc format for th

chore(xilinx): follow kernel doc format for functional documentation

For TF-A, there is no format specified for functional documentation.
For AMD-Xilinx platforms, following kernel-doc format for the functional
documentation to make sure AMD-xilinx documentation is align with
actual code.

For example use kernel-doc from linux to call:
<linux>/scripts/kernel-doc -man -v 1 >/dev/null file...

Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: Idcc9def408b6c8da35b36f67ef82fc00890e998c

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refactor(build): merge march32/64 directives

Both march32-directive and march64-directive eventually generate the
same march option that will passed to compiler.

Merge this two separate directives

refactor(build): merge march32/64 directives

Both march32-directive and march64-directive eventually generate the
same march option that will passed to compiler.

Merge this two separate directives to a common one as march-directive.

Change-Id: I220d2b782eb3b54e13ffd5b6a581d0e6da68756a
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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