1/* 2 * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#include <arch.h> 7#include <asm_macros.S> 8#include <common/bl_common.h> 9#include <cortex_a73.h> 10#include <cpu_macros.S> 11#include <plat_macros.S> 12 13 /* --------------------------------------------- 14 * Disable L1 data cache 15 * --------------------------------------------- 16 */ 17func cortex_a73_disable_dcache 18 mrs x1, sctlr_el3 19 bic x1, x1, #SCTLR_C_BIT 20 msr sctlr_el3, x1 21 isb 22 ret 23endfunc cortex_a73_disable_dcache 24 25 /* --------------------------------------------- 26 * Disable intra-cluster coherency 27 * --------------------------------------------- 28 */ 29func cortex_a73_disable_smp 30 mrs x0, CORTEX_A73_CPUECTLR_EL1 31 bic x0, x0, #CORTEX_A73_CPUECTLR_SMP_BIT 32 msr CORTEX_A73_CPUECTLR_EL1, x0 33 isb 34 dsb sy 35 ret 36endfunc cortex_a73_disable_smp 37 38func check_smccc_arch_workaround_3 39 mov x0, #ERRATA_APPLIES 40 ret 41endfunc check_smccc_arch_workaround_3 42 43 /* --------------------------------------------------- 44 * Errata Workaround for Cortex A73 Errata #852427. 45 * This applies only to revision r0p0 of Cortex A73. 46 * Inputs: 47 * x0: variant[4:7] and revision[0:3] of current cpu. 48 * Shall clobber: x0-x17 49 * --------------------------------------------------- 50 */ 51func errata_a73_852427_wa 52 /* 53 * Compare x0 against revision r0p0 54 */ 55 mov x17, x30 56 bl check_errata_852427 57 cbz x0, 1f 58 mrs x1, CORTEX_A73_DIAGNOSTIC_REGISTER 59 orr x1, x1, #(1 << 12) 60 msr CORTEX_A73_DIAGNOSTIC_REGISTER, x1 61 isb 621: 63 ret x17 64endfunc errata_a73_852427_wa 65 66func check_errata_852427 67 mov x1, #0x00 68 b cpu_rev_var_ls 69endfunc check_errata_852427 70 71 /* --------------------------------------------------- 72 * Errata Workaround for Cortex A73 Errata #855423. 73 * This applies only to revision <= r0p1 of Cortex A73. 74 * Inputs: 75 * x0: variant[4:7] and revision[0:3] of current cpu. 76 * Shall clobber: x0-x17 77 * --------------------------------------------------- 78 */ 79func errata_a73_855423_wa 80 /* 81 * Compare x0 against revision r0p1 82 */ 83 mov x17, x30 84 bl check_errata_855423 85 cbz x0, 1f 86 mrs x1, CORTEX_A73_IMP_DEF_REG2 87 orr x1, x1, #(1 << 7) 88 msr CORTEX_A73_IMP_DEF_REG2, x1 89 isb 901: 91 ret x17 92endfunc errata_a73_855423_wa 93 94func check_errata_855423 95 mov x1, #0x01 96 b cpu_rev_var_ls 97endfunc check_errata_855423 98 99func check_errata_cve_2017_5715 100 cpu_check_csv2 x0, 1f 101#if WORKAROUND_CVE_2017_5715 102 mov x0, #ERRATA_APPLIES 103#else 104 mov x0, #ERRATA_MISSING 105#endif 106 ret 1071: 108 mov x0, #ERRATA_NOT_APPLIES 109 ret 110endfunc check_errata_cve_2017_5715 111 112func check_errata_cve_2018_3639 113#if WORKAROUND_CVE_2018_3639 114 mov x0, #ERRATA_APPLIES 115#else 116 mov x0, #ERRATA_MISSING 117#endif 118 ret 119endfunc check_errata_cve_2018_3639 120 121func check_errata_cve_2022_23960 122#if WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 123 cpu_check_csv2 x0, 1f 124 mov x0, #ERRATA_APPLIES 125 ret 126 1: 127# if WORKAROUND_CVE_2022_23960 128 mov x0, #ERRATA_APPLIES 129# else 130 mov x0, #ERRATA_MISSING 131# endif /* WORKAROUND_CVE_2022_23960 */ 132 ret 133#endif /* WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 */ 134 mov x0, #ERRATA_MISSING 135 ret 136endfunc check_errata_cve_2022_23960 137 138 /* ------------------------------------------------- 139 * The CPU Ops reset function for Cortex-A73. 140 * ------------------------------------------------- 141 */ 142 143func cortex_a73_reset_func 144 mov x19, x30 145 bl cpu_get_rev_var 146 mov x18, x0 147 148#if ERRATA_A73_852427 149 mov x0, x18 150 bl errata_a73_852427_wa 151#endif 152 153#if ERRATA_A73_855423 154 mov x0, x18 155 bl errata_a73_855423_wa 156#endif 157 158#if IMAGE_BL31 && (WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960) 159 cpu_check_csv2 x0, 1f 160 adr x0, wa_cve_2017_5715_bpiall_vbar 161 msr vbar_el3, x0 162 isb 163 /* Skip installing vector table again for CVE_2022_23960 */ 164 b 2f 1651: 166#if WORKAROUND_CVE_2022_23960 167 adr x0, wa_cve_2017_5715_bpiall_vbar 168 msr vbar_el3, x0 169 isb 170#endif 1712: 172#endif /* IMAGE_BL31 && (WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960) */ 173 174#if WORKAROUND_CVE_2018_3639 175 mrs x0, CORTEX_A73_IMP_DEF_REG1 176 orr x0, x0, #CORTEX_A73_IMP_DEF_REG1_DISABLE_LOAD_PASS_STORE 177 msr CORTEX_A73_IMP_DEF_REG1, x0 178 isb 179#endif 180 181 /* --------------------------------------------- 182 * Enable the SMP bit. 183 * Clobbers : x0 184 * --------------------------------------------- 185 */ 186 mrs x0, CORTEX_A73_CPUECTLR_EL1 187 orr x0, x0, #CORTEX_A73_CPUECTLR_SMP_BIT 188 msr CORTEX_A73_CPUECTLR_EL1, x0 189 isb 190 ret x19 191endfunc cortex_a73_reset_func 192 193func cortex_a73_core_pwr_dwn 194 mov x18, x30 195 196 /* --------------------------------------------- 197 * Turn off caches. 198 * --------------------------------------------- 199 */ 200 bl cortex_a73_disable_dcache 201 202 /* --------------------------------------------- 203 * Flush L1 caches. 204 * --------------------------------------------- 205 */ 206 mov x0, #DCCISW 207 bl dcsw_op_level1 208 209 /* --------------------------------------------- 210 * Come out of intra cluster coherency 211 * --------------------------------------------- 212 */ 213 mov x30, x18 214 b cortex_a73_disable_smp 215endfunc cortex_a73_core_pwr_dwn 216 217func cortex_a73_cluster_pwr_dwn 218 mov x18, x30 219 220 /* --------------------------------------------- 221 * Turn off caches. 222 * --------------------------------------------- 223 */ 224 bl cortex_a73_disable_dcache 225 226 /* --------------------------------------------- 227 * Flush L1 caches. 228 * --------------------------------------------- 229 */ 230 mov x0, #DCCISW 231 bl dcsw_op_level1 232 233 /* --------------------------------------------- 234 * Disable the optional ACP. 235 * --------------------------------------------- 236 */ 237 bl plat_disable_acp 238 239 /* --------------------------------------------- 240 * Flush L2 caches. 241 * --------------------------------------------- 242 */ 243 mov x0, #DCCISW 244 bl dcsw_op_level2 245 246 /* --------------------------------------------- 247 * Come out of intra cluster coherency 248 * --------------------------------------------- 249 */ 250 mov x30, x18 251 b cortex_a73_disable_smp 252endfunc cortex_a73_cluster_pwr_dwn 253 254 255#if REPORT_ERRATA 256/* 257 * Errata printing function for Cortex A75. Must follow AAPCS. 258 */ 259func cortex_a73_errata_report 260 stp x8, x30, [sp, #-16]! 261 262 bl cpu_get_rev_var 263 mov x8, x0 264 265 /* 266 * Report all errata. The revision-variant information is passed to 267 * checking functions of each errata. 268 */ 269 report_errata ERRATA_A73_852427, cortex_a73, 852427 270 report_errata ERRATA_A73_855423, cortex_a73, 855423 271 report_errata WORKAROUND_CVE_2017_5715, cortex_a73, cve_2017_5715 272 report_errata WORKAROUND_CVE_2018_3639, cortex_a73, cve_2018_3639 273 report_errata WORKAROUND_CVE_2022_23960, cortex_a73, cve_2022_23960 274 275 ldp x8, x30, [sp], #16 276 ret 277endfunc cortex_a73_errata_report 278#endif 279 280 /* --------------------------------------------- 281 * This function provides cortex_a73 specific 282 * register information for crash reporting. 283 * It needs to return with x6 pointing to 284 * a list of register names in ascii and 285 * x8 - x15 having values of registers to be 286 * reported. 287 * --------------------------------------------- 288 */ 289.section .rodata.cortex_a73_regs, "aS" 290cortex_a73_regs: /* The ascii list of register names to be reported */ 291 .asciz "cpuectlr_el1", "l2merrsr_el1", "" 292 293func cortex_a73_cpu_reg_dump 294 adr x6, cortex_a73_regs 295 mrs x8, CORTEX_A73_CPUECTLR_EL1 296 mrs x9, CORTEX_A73_L2MERRSR_EL1 297 ret 298endfunc cortex_a73_cpu_reg_dump 299 300declare_cpu_ops_wa cortex_a73, CORTEX_A73_MIDR, \ 301 cortex_a73_reset_func, \ 302 check_errata_cve_2017_5715, \ 303 CPU_NO_EXTRA2_FUNC, \ 304 check_smccc_arch_workaround_3, \ 305 cortex_a73_core_pwr_dwn, \ 306 cortex_a73_cluster_pwr_dwn 307