1/* 2 * Copyright (c) 2021-2023, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_x3.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex-X3 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex-X3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if WORKAROUND_CVE_2022_23960 26 wa_cve_2022_23960_bhb_vector_table CORTEX_X3_BHB_LOOP_COUNT, cortex_x3 27#endif /* WORKAROUND_CVE_2022_23960 */ 28 29workaround_runtime_start cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909 30 /* Set bit 36 in ACTLR2_EL1 */ 31 mrs x1, CORTEX_X3_CPUACTLR2_EL1 32 orr x1, x1, #CORTEX_X3_CPUACTLR2_EL1_BIT_36 33 msr CORTEX_X3_CPUACTLR2_EL1, x1 34workaround_runtime_end cortex_x3, ERRATUM(2313909), NO_ISB 35 36check_erratum_ls cortex_x3, ERRATUM(2313909), CPU_REV(1, 0) 37 38workaround_reset_start cortex_x3, ERRATUM(2615812), ERRATA_X3_2615812 39 /* Disable retention control for WFI and WFE. */ 40 mrs x0, CORTEX_X3_CPUPWRCTLR_EL1 41 bfi x0, xzr, #CORTEX_X3_CPUPWRCTLR_EL1_WFI_RET_CTRL_BITS_SHIFT, #3 42 bfi x0, xzr, #CORTEX_X3_CPUPWRCTLR_EL1_WFE_RET_CTRL_BITS_SHIFT, #3 43 msr CORTEX_X3_CPUPWRCTLR_EL1, x0 44workaround_reset_end cortex_x3, ERRATUM(2615812) 45 46check_erratum_ls cortex_x3, ERRATUM(2615812), CPU_REV(1, 1) 47 48workaround_reset_start cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 49#if IMAGE_BL31 50 adr x0, wa_cve_vbar_cortex_x3 51 msr vbar_el3, x0 52#endif /* IMAGE_BL31 */ 53workaround_reset_end cortex_x3, CVE(2022, 23960) 54 55check_erratum_chosen cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 56 57cpu_reset_func_start cortex_x3 58 /* Disable speculative loads */ 59 msr SSBS, xzr 60cpu_reset_func_end cortex_x3 61 62 /* ---------------------------------------------------- 63 * HW will do the cache maintenance while powering down 64 * ---------------------------------------------------- 65 */ 66func cortex_x3_core_pwr_dwn 67apply_erratum cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909 68 /* --------------------------------------------------- 69 * Enable CPU power down bit in power control register 70 * --------------------------------------------------- 71 */ 72 mrs x0, CORTEX_X3_CPUPWRCTLR_EL1 73 orr x0, x0, #CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 74 msr CORTEX_X3_CPUPWRCTLR_EL1, x0 75 isb 76 ret 77endfunc cortex_x3_core_pwr_dwn 78 79errata_report_shim cortex_x3 80 81 /* --------------------------------------------- 82 * This function provides Cortex-X3- 83 * specific register information for crash 84 * reporting. It needs to return with x6 85 * pointing to a list of register names in ascii 86 * and x8 - x15 having values of registers to be 87 * reported. 88 * --------------------------------------------- 89 */ 90.section .rodata.cortex_x3_regs, "aS" 91cortex_x3_regs: /* The ascii list of register names to be reported */ 92 .asciz "cpuectlr_el1", "" 93 94func cortex_x3_cpu_reg_dump 95 adr x6, cortex_x3_regs 96 mrs x8, CORTEX_X3_CPUECTLR_EL1 97 ret 98endfunc cortex_x3_cpu_reg_dump 99 100declare_cpu_ops cortex_x3, CORTEX_X3_MIDR, \ 101 cortex_x3_reset_func, \ 102 cortex_x3_core_pwr_dwn 103