1/* 2 * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a35.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14 /* --------------------------------------------- 15 * Disable L1 data cache and unified L2 cache 16 * --------------------------------------------- 17 */ 18func cortex_a35_disable_dcache 19 mrs x1, sctlr_el3 20 bic x1, x1, #SCTLR_C_BIT 21 msr sctlr_el3, x1 22 isb 23 ret 24endfunc cortex_a35_disable_dcache 25 26 /* --------------------------------------------- 27 * Disable intra-cluster coherency 28 * --------------------------------------------- 29 */ 30func cortex_a35_disable_smp 31 mrs x0, CORTEX_A35_CPUECTLR_EL1 32 bic x0, x0, #CORTEX_A35_CPUECTLR_SMPEN_BIT 33 msr CORTEX_A35_CPUECTLR_EL1, x0 34 isb 35 dsb sy 36 ret 37endfunc cortex_a35_disable_smp 38 39workaround_reset_start cortex_a35, ERRATUM(855472), ERRATA_A35_855472 40 mrs x1, CORTEX_A35_CPUACTLR_EL1 41 orr x1, x1, #CORTEX_A35_CPUACTLR_EL1_ENDCCASCI 42 msr CORTEX_A35_CPUACTLR_EL1, x1 43workaround_reset_end cortex_a35, ERRATUM(855472) 44 45check_erratum_ls cortex_a35, ERRATUM(855472), CPU_REV(0, 0) 46 47 /* ------------------------------------------------- 48 * The CPU Ops reset function for Cortex-A35. 49 * ------------------------------------------------- 50 */ 51cpu_reset_func_start cortex_a35 52 /* --------------------------------------------- 53 * Enable the SMP bit. 54 * --------------------------------------------- 55 */ 56 mrs x0, CORTEX_A35_CPUECTLR_EL1 57 orr x0, x0, #CORTEX_A35_CPUECTLR_SMPEN_BIT 58 msr CORTEX_A35_CPUECTLR_EL1, x0 59cpu_reset_func_end cortex_a35 60 61func cortex_a35_core_pwr_dwn 62 mov x18, x30 63 64 /* --------------------------------------------- 65 * Turn off caches. 66 * --------------------------------------------- 67 */ 68 bl cortex_a35_disable_dcache 69 70 /* --------------------------------------------- 71 * Flush L1 caches. 72 * --------------------------------------------- 73 */ 74 mov x0, #DCCISW 75 bl dcsw_op_level1 76 77 /* --------------------------------------------- 78 * Come out of intra cluster coherency 79 * --------------------------------------------- 80 */ 81 mov x30, x18 82 b cortex_a35_disable_smp 83endfunc cortex_a35_core_pwr_dwn 84 85func cortex_a35_cluster_pwr_dwn 86 mov x18, x30 87 88 /* --------------------------------------------- 89 * Turn off caches. 90 * --------------------------------------------- 91 */ 92 bl cortex_a35_disable_dcache 93 94 /* --------------------------------------------- 95 * Flush L1 caches. 96 * --------------------------------------------- 97 */ 98 mov x0, #DCCISW 99 bl dcsw_op_level1 100 101 /* --------------------------------------------- 102 * Disable the optional ACP. 103 * --------------------------------------------- 104 */ 105 bl plat_disable_acp 106 107 /* --------------------------------------------- 108 * Flush L2 caches. 109 * --------------------------------------------- 110 */ 111 mov x0, #DCCISW 112 bl dcsw_op_level2 113 114 /* --------------------------------------------- 115 * Come out of intra cluster coherency 116 * --------------------------------------------- 117 */ 118 mov x30, x18 119 b cortex_a35_disable_smp 120endfunc cortex_a35_cluster_pwr_dwn 121 122errata_report_shim cortex_a35 123 124 /* --------------------------------------------- 125 * This function provides cortex_a35 specific 126 * register information for crash reporting. 127 * It needs to return with x6 pointing to 128 * a list of register names in ascii and 129 * x8 - x15 having values of registers to be 130 * reported. 131 * --------------------------------------------- 132 */ 133.section .rodata.cortex_a35_regs, "aS" 134cortex_a35_regs: /* The ascii list of register names to be reported */ 135 .asciz "cpuectlr_el1", "" 136 137func cortex_a35_cpu_reg_dump 138 adr x6, cortex_a35_regs 139 mrs x8, CORTEX_A35_CPUECTLR_EL1 140 ret 141endfunc cortex_a35_cpu_reg_dump 142 143declare_cpu_ops cortex_a35, CORTEX_A35_MIDR, \ 144 cortex_a35_reset_func, \ 145 cortex_a35_core_pwr_dwn, \ 146 cortex_a35_cluster_pwr_dwn 147