1/* 2 * Copyright (c) 2019-2023, Arm Limited. All rights reserved. 3 * Copyright (c) 2021-2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8#include <arch.h> 9#include <asm_macros.S> 10#include <common/bl_common.h> 11#include <cortex_a78_ae.h> 12#include <cpu_macros.S> 13#include <plat_macros.S> 14#include "wa_cve_2022_23960_bhb_vector.S" 15 16/* Hardware handled coherency */ 17#if HW_ASSISTED_COHERENCY == 0 18#error "cortex_a78_ae must be compiled with HW_ASSISTED_COHERENCY enabled" 19#endif 20 21#if WORKAROUND_CVE_2022_23960 22 wa_cve_2022_23960_bhb_vector_table CORTEX_A78_AE_BHB_LOOP_COUNT, cortex_a78_ae 23#endif /* WORKAROUND_CVE_2022_23960 */ 24 25workaround_reset_start cortex_a78_ae, ERRATUM(1941500), ERRATA_A78_AE_1941500 26 /* Set bit 8 in ECTLR_EL1 */ 27 mrs x0, CORTEX_A78_AE_CPUECTLR_EL1 28 bic x0, x0, #CORTEX_A78_AE_CPUECTLR_EL1_BIT_8 29 msr CORTEX_A78_AE_CPUECTLR_EL1, x0 30workaround_reset_end cortex_a78_ae, ERRATUM(1941500) 31 32check_erratum_range cortex_a78_ae, ERRATUM(1941500), CPU_REV(0, 0), CPU_REV(0, 1) 33 34workaround_reset_start cortex_a78_ae, ERRATUM(1951502), ERRATA_A78_AE_1951502 35 msr S3_6_c15_c8_0, xzr 36 ldr x0, =0x10E3900002 37 msr S3_6_c15_c8_2, x0 38 ldr x0, =0x10FFF00083 39 msr S3_6_c15_c8_3, x0 40 ldr x0, =0x2001003FF 41 msr S3_6_c15_c8_1, x0 42 43 mov x0, #1 44 msr S3_6_c15_c8_0, x0 45 ldr x0, =0x10E3800082 46 msr S3_6_c15_c8_2, x0 47 ldr x0, =0x10FFF00083 48 msr S3_6_c15_c8_3, x0 49 ldr x0, =0x2001003FF 50 msr S3_6_c15_c8_1, x0 51 52 mov x0, #2 53 msr S3_6_c15_c8_0, x0 54 ldr x0, =0x10E3800200 55 msr S3_6_c15_c8_2, x0 56 ldr x0, =0x10FFF003E0 57 msr S3_6_c15_c8_3, x0 58 ldr x0, =0x2001003FF 59 msr S3_6_c15_c8_1, x0 60workaround_reset_end cortex_a78_ae, ERRATUM(1951502) 61 62check_erratum_range cortex_a78_ae, ERRATUM(1951502), CPU_REV(0, 0), CPU_REV(0, 1) 63 64workaround_reset_start cortex_a78_ae, ERRATUM(2376748), ERRATA_A78_AE_2376748 65 /* ------------------------------------------------------- 66 * Set CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM ST to 67 * behave like PLD/PRFM LD and not cause invalidations to 68 * other PE caches. There might be a small performance 69 * degradation to this workaround for certain workloads 70 * that share data. 71 * ------------------------------------------------------- 72 */ 73 mrs x0, CORTEX_A78_AE_ACTLR2_EL1 74 orr x0, x0, #CORTEX_A78_AE_ACTLR2_EL1_BIT_0 75 msr CORTEX_A78_AE_ACTLR2_EL1, x0 76workaround_reset_end cortex_a78_ae, ERRATUM(2376748) 77 78check_erratum_range cortex_a78_ae, ERRATUM(2376748), CPU_REV(0, 0), CPU_REV(0, 1) 79 80workaround_reset_start cortex_a78_ae, ERRATUM(2395408), ERRATA_A78_AE_2395408 81 /* -------------------------------------------------------- 82 * Disable folding of demand requests into older prefetches 83 * with L2 miss requests outstanding by setting the 84 * CPUACTLR2_EL1[40] to 1. 85 * -------------------------------------------------------- 86 */ 87 mrs x0, CORTEX_A78_AE_ACTLR2_EL1 88 orr x0, x0, #CORTEX_A78_AE_ACTLR2_EL1_BIT_40 89 msr CORTEX_A78_AE_ACTLR2_EL1, x0 90workaround_reset_end cortex_a78_ae, ERRATUM(2395408) 91 92check_erratum_range cortex_a78_ae, ERRATUM(2395408), CPU_REV(0, 0), CPU_REV(0, 1) 93 94workaround_reset_start cortex_a78_ae, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 95#if IMAGE_BL31 96 /* 97 * The Cortex-A78AE generic vectors are overridden to apply errata 98 * mitigation on exception entry from lower ELs. 99 */ 100 override_vector_table wa_cve_vbar_cortex_a78_ae 101#endif /* IMAGE_BL31 */ 102workaround_reset_end cortex_a78_ae, CVE(2022, 23960) 103 104check_erratum_chosen cortex_a78_ae, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 105 106cpu_reset_func_start cortex_a78_ae 107#if ENABLE_FEAT_AMU 108 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 109 mrs x0, actlr_el3 110 bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT 111 msr actlr_el3, x0 112 113 /* Make sure accesses from non-secure EL0/EL1 are not trapped to EL2 */ 114 mrs x0, actlr_el2 115 bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT 116 msr actlr_el2, x0 117 118 /* Enable group0 counters */ 119 mov x0, #CORTEX_A78_AMU_GROUP0_MASK 120 msr CPUAMCNTENSET0_EL0, x0 121 122 /* Enable group1 counters */ 123 mov x0, #CORTEX_A78_AMU_GROUP1_MASK 124 msr CPUAMCNTENSET1_EL0, x0 125#endif 126cpu_reset_func_end cortex_a78_ae 127 128 /* ------------------------------------------------------- 129 * HW will do the cache maintenance while powering down 130 * ------------------------------------------------------- 131 */ 132func cortex_a78_ae_core_pwr_dwn 133 /* ------------------------------------------------------- 134 * Enable CPU power down bit in power control register 135 * ------------------------------------------------------- 136 */ 137 mrs x0, CORTEX_A78_CPUPWRCTLR_EL1 138 orr x0, x0, #CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 139 msr CORTEX_A78_CPUPWRCTLR_EL1, x0 140 isb 141 ret 142endfunc cortex_a78_ae_core_pwr_dwn 143 144errata_report_shim cortex_a78_ae 145 146 /* ------------------------------------------------------- 147 * This function provides cortex_a78_ae specific 148 * register information for crash reporting. 149 * It needs to return with x6 pointing to 150 * a list of register names in ascii and 151 * x8 - x15 having values of registers to be 152 * reported. 153 * ------------------------------------------------------- 154 */ 155.section .rodata.cortex_a78_ae_regs, "aS" 156cortex_a78_ae_regs: /* The ascii list of register names to be reported */ 157 .asciz "cpuectlr_el1", "" 158 159func cortex_a78_ae_cpu_reg_dump 160 adr x6, cortex_a78_ae_regs 161 mrs x8, CORTEX_A78_CPUECTLR_EL1 162 ret 163endfunc cortex_a78_ae_cpu_reg_dump 164 165declare_cpu_ops cortex_a78_ae, CORTEX_A78_AE_MIDR, \ 166 cortex_a78_ae_reset_func, \ 167 cortex_a78_ae_core_pwr_dwn 168