1/* 2 * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a77.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex-A77 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex-A77 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if WORKAROUND_CVE_2022_23960 26 wa_cve_2022_23960_bhb_vector_table CORTEX_A77_BHB_LOOP_COUNT, cortex_a77 27#endif /* WORKAROUND_CVE_2022_23960 */ 28 29 /* -------------------------------------------------- 30 * Errata Workaround for Cortex A77 Errata #1508412. 31 * This applies only to revision <= r1p0 of Cortex A77. 32 * Inputs: 33 * x0: variant[4:7] and revision[0:3] of current cpu. 34 * Shall clobber: x0-x17 35 * -------------------------------------------------- 36 */ 37func errata_a77_1508412_wa 38 /* 39 * Compare x0 against revision r1p0 40 */ 41 mov x17, x30 42 bl check_errata_1508412 43 cbz x0, 3f 44 /* 45 * Compare x0 against revision r0p0 46 */ 47 bl check_errata_1508412_0 48 cbz x0, 1f 49 ldr x0, =0x0 50 msr CORTEX_A77_CPUPSELR_EL3, x0 51 ldr x0, =0x00E8400000 52 msr CORTEX_A77_CPUPOR_EL3, x0 53 ldr x0, =0x00FFE00000 54 msr CORTEX_A77_CPUPMR_EL3, x0 55 ldr x0, =0x4004003FF 56 msr CORTEX_A77_CPUPCR_EL3, x0 57 ldr x0, =0x1 58 msr CORTEX_A77_CPUPSELR_EL3, x0 59 ldr x0, =0x00E8C00040 60 msr CORTEX_A77_CPUPOR_EL3, x0 61 ldr x0, =0x00FFE00040 62 msr CORTEX_A77_CPUPMR_EL3, x0 63 b 2f 641: 65 ldr x0, =0x0 66 msr CORTEX_A77_CPUPSELR_EL3, x0 67 ldr x0, =0x00E8400000 68 msr CORTEX_A77_CPUPOR_EL3, x0 69 ldr x0, =0x00FF600000 70 msr CORTEX_A77_CPUPMR_EL3, x0 71 ldr x0, =0x00E8E00080 72 msr CORTEX_A77_CPUPOR2_EL3, x0 73 ldr x0, =0x00FFE000C0 74 msr CORTEX_A77_CPUPMR2_EL3, x0 752: 76 ldr x0, =0x04004003FF 77 msr CORTEX_A77_CPUPCR_EL3, x0 78 isb 793: 80 ret x17 81endfunc errata_a77_1508412_wa 82 83func check_errata_1508412 84 mov x1, #0x10 85 b cpu_rev_var_ls 86endfunc check_errata_1508412 87 88func check_errata_1508412_0 89 mov x1, #0x0 90 b cpu_rev_var_ls 91endfunc check_errata_1508412_0 92 93 /* -------------------------------------------------- 94 * Errata Workaround for Cortex A77 Errata #1791578. 95 * This applies to revisions r0p0, r1p0, and r1p1 and is still open. 96 * x0: variant[4:7] and revision[0:3] of current cpu. 97 * Shall clobber: x0-x17 98 * -------------------------------------------------- 99 */ 100func errata_a77_1791578_wa 101 /* Check workaround compatibility. */ 102 mov x17, x30 103 bl check_errata_1791578 104 cbz x0, 1f 105 106 /* Set bit 2 in ACTLR2_EL1 */ 107 mrs x1, CORTEX_A77_ACTLR2_EL1 108 orr x1, x1, #CORTEX_A77_ACTLR2_EL1_BIT_2 109 msr CORTEX_A77_ACTLR2_EL1, x1 110 isb 1111: 112 ret x17 113endfunc errata_a77_1791578_wa 114 115func check_errata_1791578 116 /* Applies to r0p0, r1p0, and r1p1 right now */ 117 mov x1, #0x11 118 b cpu_rev_var_ls 119endfunc check_errata_1791578 120 121 /* -------------------------------------------------- 122 * Errata Workaround for Cortex A77 Errata #1800714. 123 * This applies to revision <= r1p1 of Cortex A77. 124 * Inputs: 125 * x0: variant[4:7] and revision[0:3] of current cpu. 126 * Shall clobber: x0-x17 127 * -------------------------------------------------- 128 */ 129func errata_a77_1800714_wa 130 /* Compare x0 against revision <= r1p1 */ 131 mov x17, x30 132 bl check_errata_1800714 133 cbz x0, 1f 134 135 /* Disable allocation of splintered pages in the L2 TLB */ 136 mrs x1, CORTEX_A77_CPUECTLR_EL1 137 orr x1, x1, CORTEX_A77_CPUECTLR_EL1_BIT_53 138 msr CORTEX_A77_CPUECTLR_EL1, x1 139 isb 1401: 141 ret x17 142endfunc errata_a77_1800714_wa 143 144func check_errata_1800714 145 /* Applies to everything <= r1p1 */ 146 mov x1, #0x11 147 b cpu_rev_var_ls 148endfunc check_errata_1800714 149 150 /* -------------------------------------------------- 151 * Errata Workaround for Cortex A77 Errata #1925769. 152 * This applies to revision <= r1p1 of Cortex A77. 153 * Inputs: 154 * x0: variant[4:7] and revision[0:3] of current cpu. 155 * Shall clobber: x0-x17 156 * -------------------------------------------------- 157 */ 158func errata_a77_1925769_wa 159 /* Compare x0 against revision <= r1p1 */ 160 mov x17, x30 161 bl check_errata_1925769 162 cbz x0, 1f 163 164 /* Set bit 8 in ECTLR_EL1 */ 165 mrs x1, CORTEX_A77_CPUECTLR_EL1 166 orr x1, x1, #CORTEX_A77_CPUECTLR_EL1_BIT_8 167 msr CORTEX_A77_CPUECTLR_EL1, x1 168 isb 1691: 170 ret x17 171endfunc errata_a77_1925769_wa 172 173func check_errata_1925769 174 /* Applies to everything <= r1p1 */ 175 mov x1, #0x11 176 b cpu_rev_var_ls 177endfunc check_errata_1925769 178 179 /* -------------------------------------------------- 180 * Errata Workaround for Cortex A77 Errata #1946167. 181 * This applies to revision <= r1p1 of Cortex A77. 182 * Inputs: 183 * x0: variant[4:7] and revision[0:3] of current cpu. 184 * Shall clobber: x0-x17 185 * -------------------------------------------------- 186 */ 187func errata_a77_1946167_wa 188 /* Compare x0 against revision <= r1p1 */ 189 mov x17, x30 190 bl check_errata_1946167 191 cbz x0, 1f 192 193 ldr x0,=0x4 194 msr CORTEX_A77_CPUPSELR_EL3,x0 195 ldr x0,=0x10E3900002 196 msr CORTEX_A77_CPUPOR_EL3,x0 197 ldr x0,=0x10FFF00083 198 msr CORTEX_A77_CPUPMR_EL3,x0 199 ldr x0,=0x2001003FF 200 msr CORTEX_A77_CPUPCR_EL3,x0 201 202 ldr x0,=0x5 203 msr CORTEX_A77_CPUPSELR_EL3,x0 204 ldr x0,=0x10E3800082 205 msr CORTEX_A77_CPUPOR_EL3,x0 206 ldr x0,=0x10FFF00083 207 msr CORTEX_A77_CPUPMR_EL3,x0 208 ldr x0,=0x2001003FF 209 msr CORTEX_A77_CPUPCR_EL3,x0 210 211 ldr x0,=0x6 212 msr CORTEX_A77_CPUPSELR_EL3,x0 213 ldr x0,=0x10E3800200 214 msr CORTEX_A77_CPUPOR_EL3,x0 215 ldr x0,=0x10FFF003E0 216 msr CORTEX_A77_CPUPMR_EL3,x0 217 ldr x0,=0x2001003FF 218 msr CORTEX_A77_CPUPCR_EL3,x0 219 220 isb 2211: 222 ret x17 223endfunc errata_a77_1946167_wa 224 225func check_errata_1946167 226 /* Applies to everything <= r1p1 */ 227 mov x1, #0x11 228 b cpu_rev_var_ls 229endfunc check_errata_1946167 230 231 /* -------------------------------------------------- 232 * Errata Workaround for Cortex A77 Errata #2356587. 233 * This applies to revisions r0p0, r1p0, and r1p1 and is still open. 234 * x0: variant[4:7] and revision[0:3] of current cpu. 235 * Shall clobber: x0-x17 236 * -------------------------------------------------- 237 */ 238func errata_a77_2356587_wa 239 /* Check workaround compatibility. */ 240 mov x17, x30 241 bl check_errata_2356587 242 cbz x0, 1f 243 244 /* Set bit 0 in ACTLR2_EL1 */ 245 mrs x1, CORTEX_A77_ACTLR2_EL1 246 orr x1, x1, #CORTEX_A77_ACTLR2_EL1_BIT_0 247 msr CORTEX_A77_ACTLR2_EL1, x1 248 isb 2491: 250 ret x17 251endfunc errata_a77_2356587_wa 252 253func check_errata_2356587 254 /* Applies to r0p0, r1p0, and r1p1 right now */ 255 mov x1, #0x11 256 b cpu_rev_var_ls 257endfunc check_errata_2356587 258 259 /* ----------------------------------------------------------------- 260 * Errata Workaround for Cortex A77 Errata #2743100 261 * This applies to revisions r0p0, r1p0, and r1p1 and is still open. 262 * x0: variant[4:7] and revision[0:3] of current cpu. 263 * Shall clobber: x0-x17 264 * ----------------------------------------------------------------- 265 */ 266func errata_a77_2743100_wa 267 mov x17, x30 268 bl check_errata_2743100 269 cbz x0, 1f 270 271 /* dsb before isb of power down sequence */ 272 dsb sy 2731: 274 ret x17 275endfunc errata_a77_2743100_wa 276 277func check_errata_2743100 278 /* Applies to r0p0, r1p0, and r1p1 right now */ 279 mov x1, #0x11 280 b cpu_rev_var_ls 281endfunc check_errata_2743100 282 283func check_errata_cve_2022_23960 284#if WORKAROUND_CVE_2022_23960 285 mov x0, #ERRATA_APPLIES 286#else 287 mov x0, #ERRATA_MISSING 288#endif 289 ret 290endfunc check_errata_cve_2022_23960 291 292 /* ------------------------------------------------- 293 * The CPU Ops reset function for Cortex-A77. 294 * Shall clobber: x0-x19 295 * ------------------------------------------------- 296 */ 297func cortex_a77_reset_func 298 mov x19, x30 299 bl cpu_get_rev_var 300 mov x18, x0 301 302#if ERRATA_A77_1508412 303 mov x0, x18 304 bl errata_a77_1508412_wa 305#endif 306 307#if ERRATA_A77_1925769 308 mov x0, x18 309 bl errata_a77_1925769_wa 310#endif 311 312#if ERRATA_A77_1946167 313 mov x0, x18 314 bl errata_a77_1946167_wa 315#endif 316 317#if ERRATA_A77_1791578 318 mov x0, x18 319 bl errata_a77_1791578_wa 320#endif 321 322#if ERRATA_A77_2356587 323 mov x0, x18 324 bl errata_a77_2356587_wa 325#endif 326 327#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 328 /* 329 * The Cortex-A77 generic vectors are overridden to apply errata 330 * mitigation on exception entry from lower ELs. 331 */ 332 adr x0, wa_cve_vbar_cortex_a77 333 msr vbar_el3, x0 334#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ 335 336#if ERRATA_A77_1800714 337 mov x0, x18 338 bl errata_a77_1800714_wa 339#endif 340 341 isb 342 ret x19 343endfunc cortex_a77_reset_func 344 345 /* --------------------------------------------- 346 * HW will do the cache maintenance while powering down 347 * --------------------------------------------- 348 */ 349func cortex_a77_core_pwr_dwn 350 /* --------------------------------------------- 351 * Enable CPU power down bit in power control register 352 * --------------------------------------------- 353 */ 354 mrs x0, CORTEX_A77_CPUPWRCTLR_EL1 355 orr x0, x0, #CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 356 msr CORTEX_A77_CPUPWRCTLR_EL1, x0 357#if ERRATA_A77_2743100 358 mov x15, x30 359 bl cpu_get_rev_var 360 bl errata_a77_2743100_wa 361 mov x30, x15 362#endif /* ERRATA_A77_2743100 */ 363 isb 364 ret 365endfunc cortex_a77_core_pwr_dwn 366 367#if REPORT_ERRATA 368/* 369 * Errata printing function for Cortex-A77. Must follow AAPCS. 370 */ 371func cortex_a77_errata_report 372 stp x8, x30, [sp, #-16]! 373 374 bl cpu_get_rev_var 375 mov x8, x0 376 377 /* 378 * Report all errata. The revision-variant information is passed to 379 * checking functions of each errata. 380 */ 381 report_errata ERRATA_A77_1508412, cortex_a77, 1508412 382 report_errata ERRATA_A77_1791578, cortex_a77, 1791578 383 report_errata ERRATA_A77_1800714, cortex_a77, 1800714 384 report_errata ERRATA_A77_1925769, cortex_a77, 1925769 385 report_errata ERRATA_A77_1946167, cortex_a77, 1946167 386 report_errata ERRATA_A77_2356587, cortex_a77, 2356587 387 report_errata ERRATA_A77_2743100, cortex_a77, 2743100 388 report_errata WORKAROUND_CVE_2022_23960, cortex_a77, cve_2022_23960 389 390 ldp x8, x30, [sp], #16 391 ret 392endfunc cortex_a77_errata_report 393#endif 394 395 396 /* --------------------------------------------- 397 * This function provides Cortex-A77 specific 398 * register information for crash reporting. 399 * It needs to return with x6 pointing to 400 * a list of register names in ascii and 401 * x8 - x15 having values of registers to be 402 * reported. 403 * --------------------------------------------- 404 */ 405.section .rodata.cortex_a77_regs, "aS" 406cortex_a77_regs: /* The ascii list of register names to be reported */ 407 .asciz "cpuectlr_el1", "" 408 409func cortex_a77_cpu_reg_dump 410 adr x6, cortex_a77_regs 411 mrs x8, CORTEX_A77_CPUECTLR_EL1 412 ret 413endfunc cortex_a77_cpu_reg_dump 414 415declare_cpu_ops cortex_a77, CORTEX_A77_MIDR, \ 416 cortex_a77_reset_func, \ 417 cortex_a77_core_pwr_dwn 418