1/* 2 * Copyright (c) 2021-2023, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_x3.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex-X3 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex-X3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if WORKAROUND_CVE_2022_23960 26 wa_cve_2022_23960_bhb_vector_table CORTEX_X3_BHB_LOOP_COUNT, cortex_x3 27#endif /* WORKAROUND_CVE_2022_23960 */ 28 29/* ---------------------------------------------------------------------- 30 * Errata Workaround for Cortex-X3 Erratum 2313909 on power down request. 31 * This applies to revision r0p0 and r1p0 of Cortex-X3. Fixed in r1p1. 32 * Inputs: 33 * x0: variant[4:7] and revision[0:3] of current cpu. 34 * Shall clobber: x0-x1, x17 35 * ---------------------------------------------------------------------- 36 */ 37func errata_cortex_x3_2313909_wa 38 /* Check revision. */ 39 mov x17, x30 40 bl check_errata_2313909 41 cbz x0, 1f 42 43 /* Set bit 36 in ACTLR2_EL1 */ 44 mrs x1, CORTEX_X3_CPUACTLR2_EL1 45 orr x1, x1, #CORTEX_X3_CPUACTLR2_EL1_BIT_36 46 msr CORTEX_X3_CPUACTLR2_EL1, x1 471: 48 ret x17 49endfunc errata_cortex_x3_2313909_wa 50 51func check_errata_2313909 52 /* Applies to r0p0 and r1p0 */ 53 mov x1, #0x10 54 b cpu_rev_var_ls 55endfunc check_errata_2313909 56 57/* ---------------------------------------------------------------------- 58 * Errata Workaround for Cortex-X3 Erratum 2615812 on power-on. 59 * This applies to revision r0p0, r1p0, r1p1 of Cortex-X3. Open. 60 * Inputs: 61 * x0: variant[4:7] and revision[0:3] of current cpu. 62 * Shall clobber: x0-x1, x17 63 * ---------------------------------------------------------------------- 64 */ 65func errata_cortex_x3_2615812_wa 66 /* Check revision. */ 67 mov x17, x30 68 bl check_errata_2615812 69 cbz x0, 1f 70 71 /* Disable retention control for WFI and WFE. */ 72 mrs x0, CORTEX_X3_CPUPWRCTLR_EL1 73 bfi x0, xzr, #CORTEX_X3_CPUPWRCTLR_EL1_WFI_RET_CTRL_BITS_SHIFT, #3 74 bfi x0, xzr, #CORTEX_X3_CPUPWRCTLR_EL1_WFE_RET_CTRL_BITS_SHIFT, #3 75 msr CORTEX_X3_CPUPWRCTLR_EL1, x0 761: 77 ret x17 78endfunc errata_cortex_x3_2615812_wa 79 80func check_errata_2615812 81 /* Applies to r1p1 and below. */ 82 mov x1, #0x11 83 b cpu_rev_var_ls 84endfunc check_errata_2615812 85 86func check_errata_cve_2022_23960 87#if WORKAROUND_CVE_2022_23960 88 mov x0, #ERRATA_APPLIES 89#else 90 mov x0, #ERRATA_MISSING 91#endif 92 ret 93endfunc check_errata_cve_2022_23960 94 95func cortex_x3_reset_func 96 mov x19, x30 97 /* Disable speculative loads */ 98 msr SSBS, xzr 99 100#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 101 /* 102 * The Cortex-X3 generic vectors are overridden to apply 103 * errata mitigation on exception entry from lower ELs. 104 */ 105 adr x0, wa_cve_vbar_cortex_x3 106 msr vbar_el3, x0 107#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ 108 109 bl cpu_get_rev_var 110 111#if ERRATA_X3_2615812 112 bl errata_cortex_x3_2615812_wa 113#endif /* ERRATA_X3_2615812 */ 114 115 isb 116 ret x19 117endfunc cortex_x3_reset_func 118 119 /* ---------------------------------------------------- 120 * HW will do the cache maintenance while powering down 121 * ---------------------------------------------------- 122 */ 123func cortex_x3_core_pwr_dwn 124#if ERRATA_X3_2313909 125 mov x15, x30 126 bl cpu_get_rev_var 127 bl errata_cortex_x3_2313909_wa 128 mov x30, x15 129#endif /* ERRATA_X3_2313909 */ 130 131 /* --------------------------------------------------- 132 * Enable CPU power down bit in power control register 133 * --------------------------------------------------- 134 */ 135 mrs x0, CORTEX_X3_CPUPWRCTLR_EL1 136 orr x0, x0, #CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 137 msr CORTEX_X3_CPUPWRCTLR_EL1, x0 138 isb 139 ret 140endfunc cortex_x3_core_pwr_dwn 141 142#if REPORT_ERRATA 143 /* 144 * Errata printing function for Cortex-X3. Must follow AAPCS. 145 */ 146func cortex_x3_errata_report 147 stp x8, x30, [sp, #-16]! 148 149 bl cpu_get_rev_var 150 mov x8, x0 151 152 /* 153 * Report all errata. The revision-variant information is passed to 154 * checking functions of each errata. 155 */ 156 report_errata ERRATA_X3_2313909, cortex_x3, 2313909 157 report_errata ERRATA_X3_2615812, cortex_x3, 2615812 158 report_errata WORKAROUND_CVE_2022_23960, cortex_x3, cve_2022_23960 159 160 ldp x8, x30, [sp], #16 161 ret 162endfunc cortex_x3_errata_report 163#endif 164 165 /* --------------------------------------------- 166 * This function provides Cortex-X3- 167 * specific register information for crash 168 * reporting. It needs to return with x6 169 * pointing to a list of register names in ascii 170 * and x8 - x15 having values of registers to be 171 * reported. 172 * --------------------------------------------- 173 */ 174.section .rodata.cortex_x3_regs, "aS" 175cortex_x3_regs: /* The ascii list of register names to be reported */ 176 .asciz "cpuectlr_el1", "" 177 178func cortex_x3_cpu_reg_dump 179 adr x6, cortex_x3_regs 180 mrs x8, CORTEX_X3_CPUECTLR_EL1 181 ret 182endfunc cortex_x3_cpu_reg_dump 183 184declare_cpu_ops cortex_x3, CORTEX_X3_MIDR, \ 185 cortex_x3_reset_func, \ 186 cortex_x3_core_pwr_dwn 187