1/* 2 * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#include <arch.h> 7#include <asm_macros.S> 8#include <common/bl_common.h> 9#include <cortex_a73.h> 10#include <cpu_macros.S> 11#include <plat_macros.S> 12 13 /* --------------------------------------------- 14 * Disable L1 data cache 15 * --------------------------------------------- 16 */ 17func cortex_a73_disable_dcache 18 mrs x1, sctlr_el3 19 bic x1, x1, #SCTLR_C_BIT 20 msr sctlr_el3, x1 21 isb 22 ret 23endfunc cortex_a73_disable_dcache 24 25 /* --------------------------------------------- 26 * Disable intra-cluster coherency 27 * --------------------------------------------- 28 */ 29func cortex_a73_disable_smp 30 mrs x0, CORTEX_A73_CPUECTLR_EL1 31 bic x0, x0, #CORTEX_A73_CPUECTLR_SMP_BIT 32 msr CORTEX_A73_CPUECTLR_EL1, x0 33 isb 34 dsb sy 35 ret 36endfunc cortex_a73_disable_smp 37 38func check_smccc_arch_workaround_3 39 mov x0, #ERRATA_APPLIES 40 ret 41endfunc check_smccc_arch_workaround_3 42 43workaround_reset_start cortex_a73, ERRATUM(852427), ERRATA_A73_852427 44 mrs x1, CORTEX_A73_DIAGNOSTIC_REGISTER 45 orr x1, x1, #(1 << 12) 46 msr CORTEX_A73_DIAGNOSTIC_REGISTER, x1 47workaround_reset_end cortex_a73, ERRATUM(852427) 48 49check_erratum_ls cortex_a73, ERRATUM(852427), CPU_REV(0, 0) 50 51workaround_reset_start cortex_a73, ERRATUM(855423), ERRATA_A73_855423 52 mrs x1, CORTEX_A73_IMP_DEF_REG2 53 orr x1, x1, #(1 << 7) 54 msr CORTEX_A73_IMP_DEF_REG2, x1 55workaround_reset_end cortex_a73, ERRATUM(855423) 56 57check_erratum_ls cortex_a73, ERRATUM(855423), CPU_REV(0, 1) 58 59workaround_reset_start cortex_a73, CVE(2017, 5715), WORKAROUND_CVE_2017_5715 60#if IMAGE_BL31 61 adr x0, wa_cve_2017_5715_bpiall_vbar 62 msr vbar_el3, x0 63#endif /* IMAGE_BL31 */ 64workaround_reset_end cortex_a73, CVE(2017, 5715) 65 66check_erratum_custom_start cortex_a73, CVE(2017, 5715) 67 cpu_check_csv2 x0, 1f 68#if WORKAROUND_CVE_2017_5715 69 mov x0, #ERRATA_APPLIES 70#else 71 mov x0, #ERRATA_MISSING 72#endif 73 ret 741: 75 mov x0, #ERRATA_NOT_APPLIES 76 ret 77check_erratum_custom_end cortex_a73, CVE(2017, 5715) 78 79workaround_reset_start cortex_a73, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 80 mrs x0, CORTEX_A73_IMP_DEF_REG1 81 orr x0, x0, #CORTEX_A73_IMP_DEF_REG1_DISABLE_LOAD_PASS_STORE 82 msr CORTEX_A73_IMP_DEF_REG1, x0 83workaround_reset_end cortex_a73, CVE(2018, 3639) 84 85check_erratum_chosen cortex_a73, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 86 87workaround_reset_start cortex_a73, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 88#if IMAGE_BL31 89 /* Skip installing vector table again for CVE_2022_23960 */ 90 adr x0, wa_cve_2017_5715_bpiall_vbar 91 mrs x1, vbar_el3 92 cmp x0, x1 93 b.eq 1f 94 msr vbar_el3, x0 951: 96#endif /* IMAGE_BL31 */ 97workaround_reset_end cortex_a73, CVE(2022, 23960) 98 99check_erratum_custom_start cortex_a73, CVE(2022, 23960) 100#if WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 101 cpu_check_csv2 x0, 1f 102 mov x0, #ERRATA_APPLIES 103 ret 104 1: 105#if WORKAROUND_CVE_2022_23960 106 mov x0, #ERRATA_APPLIES 107#else 108 mov x0, #ERRATA_MISSING 109#endif /* WORKAROUND_CVE_2022_23960 */ 110 ret 111#endif /* WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 */ 112 mov x0, #ERRATA_MISSING 113 ret 114check_erratum_custom_end cortex_a73, CVE(2022, 23960) 115 116 /* ------------------------------------------------- 117 * The CPU Ops reset function for Cortex-A73. 118 * ------------------------------------------------- 119 */ 120 121cpu_reset_func_start cortex_a73 122 /* --------------------------------------------- 123 * Enable the SMP bit. 124 * Clobbers : x0 125 * --------------------------------------------- 126 */ 127 mrs x0, CORTEX_A73_CPUECTLR_EL1 128 orr x0, x0, #CORTEX_A73_CPUECTLR_SMP_BIT 129 msr CORTEX_A73_CPUECTLR_EL1, x0 130cpu_reset_func_end cortex_a73 131 132func cortex_a73_core_pwr_dwn 133 mov x18, x30 134 135 /* --------------------------------------------- 136 * Turn off caches. 137 * --------------------------------------------- 138 */ 139 bl cortex_a73_disable_dcache 140 141 /* --------------------------------------------- 142 * Flush L1 caches. 143 * --------------------------------------------- 144 */ 145 mov x0, #DCCISW 146 bl dcsw_op_level1 147 148 /* --------------------------------------------- 149 * Come out of intra cluster coherency 150 * --------------------------------------------- 151 */ 152 mov x30, x18 153 b cortex_a73_disable_smp 154endfunc cortex_a73_core_pwr_dwn 155 156func cortex_a73_cluster_pwr_dwn 157 mov x18, x30 158 159 /* --------------------------------------------- 160 * Turn off caches. 161 * --------------------------------------------- 162 */ 163 bl cortex_a73_disable_dcache 164 165 /* --------------------------------------------- 166 * Flush L1 caches. 167 * --------------------------------------------- 168 */ 169 mov x0, #DCCISW 170 bl dcsw_op_level1 171 172 /* --------------------------------------------- 173 * Disable the optional ACP. 174 * --------------------------------------------- 175 */ 176 bl plat_disable_acp 177 178 /* --------------------------------------------- 179 * Flush L2 caches. 180 * --------------------------------------------- 181 */ 182 mov x0, #DCCISW 183 bl dcsw_op_level2 184 185 /* --------------------------------------------- 186 * Come out of intra cluster coherency 187 * --------------------------------------------- 188 */ 189 mov x30, x18 190 b cortex_a73_disable_smp 191endfunc cortex_a73_cluster_pwr_dwn 192 193 194errata_report_shim cortex_a73 195 196 /* --------------------------------------------- 197 * This function provides cortex_a73 specific 198 * register information for crash reporting. 199 * It needs to return with x6 pointing to 200 * a list of register names in ascii and 201 * x8 - x15 having values of registers to be 202 * reported. 203 * --------------------------------------------- 204 */ 205.section .rodata.cortex_a73_regs, "aS" 206cortex_a73_regs: /* The ascii list of register names to be reported */ 207 .asciz "cpuectlr_el1", "l2merrsr_el1", "" 208 209func cortex_a73_cpu_reg_dump 210 adr x6, cortex_a73_regs 211 mrs x8, CORTEX_A73_CPUECTLR_EL1 212 mrs x9, CORTEX_A73_L2MERRSR_EL1 213 ret 214endfunc cortex_a73_cpu_reg_dump 215 216declare_cpu_ops_wa cortex_a73, CORTEX_A73_MIDR, \ 217 cortex_a73_reset_func, \ 218 check_erratum_cortex_a73_5715, \ 219 CPU_NO_EXTRA2_FUNC, \ 220 check_smccc_arch_workaround_3, \ 221 cortex_a73_core_pwr_dwn, \ 222 cortex_a73_cluster_pwr_dwn 223