1/* 2 * Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a77.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex-A77 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex-A77 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if WORKAROUND_CVE_2022_23960 26 wa_cve_2022_23960_bhb_vector_table CORTEX_A77_BHB_LOOP_COUNT, cortex_a77 27#endif /* WORKAROUND_CVE_2022_23960 */ 28 29workaround_reset_start cortex_a77, ERRATUM(1508412), ERRATA_A77_1508412 30 /* move cpu revision in again and compare against r0p0 */ 31 mov x0, x7 32 mov x1, #CPU_REV(0, 0) 33 bl cpu_rev_var_ls 34 cbz x0, 1f 35 36 ldr x0, =0x0 37 msr CORTEX_A77_CPUPSELR_EL3, x0 38 ldr x0, =0x00E8400000 39 msr CORTEX_A77_CPUPOR_EL3, x0 40 ldr x0, =0x00FFE00000 41 msr CORTEX_A77_CPUPMR_EL3, x0 42 ldr x0, =0x4004003FF 43 msr CORTEX_A77_CPUPCR_EL3, x0 44 ldr x0, =0x1 45 msr CORTEX_A77_CPUPSELR_EL3, x0 46 ldr x0, =0x00E8C00040 47 msr CORTEX_A77_CPUPOR_EL3, x0 48 ldr x0, =0x00FFE00040 49 msr CORTEX_A77_CPUPMR_EL3, x0 50 b 2f 511: 52 ldr x0, =0x0 53 msr CORTEX_A77_CPUPSELR_EL3, x0 54 ldr x0, =0x00E8400000 55 msr CORTEX_A77_CPUPOR_EL3, x0 56 ldr x0, =0x00FF600000 57 msr CORTEX_A77_CPUPMR_EL3, x0 58 ldr x0, =0x00E8E00080 59 msr CORTEX_A77_CPUPOR2_EL3, x0 60 ldr x0, =0x00FFE000C0 61 msr CORTEX_A77_CPUPMR2_EL3, x0 622: 63 ldr x0, =0x04004003FF 64 msr CORTEX_A77_CPUPCR_EL3, x0 65workaround_reset_end cortex_a77, ERRATUM(1508412) 66 67check_erratum_ls cortex_a77, ERRATUM(1508412), CPU_REV(1, 0) 68 69workaround_reset_start cortex_a77, ERRATUM(1791578), ERRATA_A77_1791578 70 /* Set bit 2 in ACTLR2_EL1 */ 71 mrs x1, CORTEX_A77_ACTLR2_EL1 72 orr x1, x1, #CORTEX_A77_ACTLR2_EL1_BIT_2 73 msr CORTEX_A77_ACTLR2_EL1, x1 74workaround_reset_end cortex_a77, ERRATUM(1791578) 75 76check_erratum_ls cortex_a77, ERRATUM(1791578), CPU_REV(1, 1) 77 78workaround_reset_start cortex_a77, ERRATUM(1800714), ERRATA_A77_1800714 79 /* Disable allocation of splintered pages in the L2 TLB */ 80 mrs x1, CORTEX_A77_CPUECTLR_EL1 81 orr x1, x1, CORTEX_A77_CPUECTLR_EL1_BIT_53 82 msr CORTEX_A77_CPUECTLR_EL1, x1 83workaround_reset_end cortex_a77, ERRATUM(1800714) 84 85check_erratum_ls cortex_a77, ERRATUM(1800714), CPU_REV(1, 1) 86 87workaround_reset_start cortex_a77, ERRATUM(1925769), ERRATA_A77_1925769 88 /* Set bit 8 in ECTLR_EL1 */ 89 mrs x1, CORTEX_A77_CPUECTLR_EL1 90 orr x1, x1, #CORTEX_A77_CPUECTLR_EL1_BIT_8 91 msr CORTEX_A77_CPUECTLR_EL1, x1 92workaround_reset_end cortex_a77, ERRATUM(1925769) 93 94check_erratum_ls cortex_a77, ERRATUM(1925769), CPU_REV(1, 1) 95 96workaround_reset_start cortex_a77, ERRATUM(1946167), ERRATA_A77_1946167 97 ldr x0,=0x4 98 msr CORTEX_A77_CPUPSELR_EL3,x0 99 ldr x0,=0x10E3900002 100 msr CORTEX_A77_CPUPOR_EL3,x0 101 ldr x0,=0x10FFF00083 102 msr CORTEX_A77_CPUPMR_EL3,x0 103 ldr x0,=0x2001003FF 104 msr CORTEX_A77_CPUPCR_EL3,x0 105 106 ldr x0,=0x5 107 msr CORTEX_A77_CPUPSELR_EL3,x0 108 ldr x0,=0x10E3800082 109 msr CORTEX_A77_CPUPOR_EL3,x0 110 ldr x0,=0x10FFF00083 111 msr CORTEX_A77_CPUPMR_EL3,x0 112 ldr x0,=0x2001003FF 113 msr CORTEX_A77_CPUPCR_EL3,x0 114 115 ldr x0,=0x6 116 msr CORTEX_A77_CPUPSELR_EL3,x0 117 ldr x0,=0x10E3800200 118 msr CORTEX_A77_CPUPOR_EL3,x0 119 ldr x0,=0x10FFF003E0 120 msr CORTEX_A77_CPUPMR_EL3,x0 121 ldr x0,=0x2001003FF 122 msr CORTEX_A77_CPUPCR_EL3,x0 123workaround_reset_end cortex_a77, ERRATUM(1946167) 124 125check_erratum_ls cortex_a77, ERRATUM(1946167), CPU_REV(1, 1) 126 127workaround_reset_start cortex_a77, ERRATUM(2356587), ERRATA_A77_2356587 128 /* Set bit 0 in ACTLR2_EL1 */ 129 mrs x1, CORTEX_A77_ACTLR2_EL1 130 orr x1, x1, #CORTEX_A77_ACTLR2_EL1_BIT_0 131 msr CORTEX_A77_ACTLR2_EL1, x1 132workaround_reset_end cortex_a77, ERRATUM(2356587) 133 134check_erratum_ls cortex_a77, ERRATUM(2356587), CPU_REV(1, 1) 135 136workaround_runtime_start cortex_a77, ERRATUM(2743100), ERRATA_A77_2743100 137 /* dsb before isb of power down sequence */ 138 dsb sy 139workaround_runtime_end cortex_a77, ERRATUM(2743100), NO_ISB 140 141check_erratum_ls cortex_a77, ERRATUM(2743100), CPU_REV(1, 1) 142 143workaround_reset_start cortex_a77, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 144#if IMAGE_BL31 145 /* 146 * The Cortex-A77 generic vectors are overridden to apply errata 147 * mitigation on exception entry from lower ELs. 148 */ 149 adr x0, wa_cve_vbar_cortex_a77 150 msr vbar_el3, x0 151#endif /* IMAGE_BL31 */ 152workaround_reset_end cortex_a77, CVE(2022, 23960) 153 154check_erratum_chosen cortex_a77, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 155 156 /* ------------------------------------------------- 157 * The CPU Ops reset function for Cortex-A77. Must follow AAPCS. 158 * ------------------------------------------------- 159 */ 160cpu_reset_func_start cortex_a77 161cpu_reset_func_end cortex_a77 162 163 /* --------------------------------------------- 164 * HW will do the cache maintenance while powering down 165 * --------------------------------------------- 166 */ 167func cortex_a77_core_pwr_dwn 168 /* --------------------------------------------- 169 * Enable CPU power down bit in power control register 170 * --------------------------------------------- 171 */ 172 mrs x0, CORTEX_A77_CPUPWRCTLR_EL1 173 orr x0, x0, #CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 174 msr CORTEX_A77_CPUPWRCTLR_EL1, x0 175#if ERRATA_A77_2743100 176 mov x15, x30 177 bl cpu_get_rev_var 178 bl erratum_cortex_a77_2743100_wa 179 mov x30, x15 180#endif /* ERRATA_A77_2743100 */ 181 isb 182 ret 183endfunc cortex_a77_core_pwr_dwn 184 185errata_report_shim cortex_a77 186 /* --------------------------------------------- 187 * This function provides Cortex-A77 specific 188 * register information for crash reporting. 189 * It needs to return with x6 pointing to 190 * a list of register names in ascii and 191 * x8 - x15 having values of registers to be 192 * reported. 193 * --------------------------------------------- 194 */ 195.section .rodata.cortex_a77_regs, "aS" 196cortex_a77_regs: /* The ascii list of register names to be reported */ 197 .asciz "cpuectlr_el1", "" 198 199func cortex_a77_cpu_reg_dump 200 adr x6, cortex_a77_regs 201 mrs x8, CORTEX_A77_CPUECTLR_EL1 202 ret 203endfunc cortex_a77_cpu_reg_dump 204 205declare_cpu_ops cortex_a77, CORTEX_A77_MIDR, \ 206 cortex_a77_reset_func, \ 207 cortex_a77_core_pwr_dwn 208