docs(security): add CVE-2024-5660 and CVE-2024-7881 reference links

Add missing hyperlink targets for CVE-2024-5660 and CVE-2024-7881 in
cpu-specific-build-macros.rst to allow cross-referencing thes

docs(security): add CVE-2024-5660 and CVE-2024-7881 reference links

Add missing hyperlink targets for CVE-2024-5660 and CVE-2024-7881 in
cpu-specific-build-macros.rst to allow cross-referencing these CVEs
from documentation.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ia3c003d5c359f101f230fbd54845f61117456abb

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Merge changes from topic "xl/a725-errata" into integration

* changes:
fix(cpus): workaround for Cortex-A725 erratum 3456106
fix(cpus): workaround for Cortex-A725 erratum 3711914
fix(cpus): wor

Merge changes from topic "xl/a725-errata" into integration

* changes:
fix(cpus): workaround for Cortex-A725 erratum 3456106
fix(cpus): workaround for Cortex-A725 erratum 3711914
fix(cpus): workaround for Cortex-A725 erratum 2936490
fix(cpus): workaround for Cortex-A725 erratum 2874943

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Merge changes from topic "ar/feat_uinj" into integration

* changes:
feat(cpufeat): add support for FEAT_UINJ
feat(cpufeat): enable mandatory Armv9.4–Armv9.6 features by default
fix(cpufeat): u

Merge changes from topic "ar/feat_uinj" into integration

* changes:
feat(cpufeat): add support for FEAT_UINJ
feat(cpufeat): enable mandatory Armv9.4–Armv9.6 features by default
fix(cpufeat): update feature names and comments
fix(cpufeat): simplify AArch32 feature disablement

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Merge changes from topic "xl/a65-errata" into integration

* changes:
fix(cpus): workaround for Cortex-A65 erratum 1541130
fix(cpus): workaround for Cortex-A65 erratum 1227419
fix(cpus): workar

Merge changes from topic "xl/a65-errata" into integration

* changes:
fix(cpus): workaround for Cortex-A65 erratum 1541130
fix(cpus): workaround for Cortex-A65 erratum 1227419
fix(cpus): workaround for Cortex-A65 erratum 1179935

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Merge changes from topic "xl/a76ae-errata" into integration

* changes:
fix(cpus): workaround for Cortex-A76AE erratum 2371140
fix(cpus): workaround for Cortex-A76AE erratum 1969401
fix(cpus):

Merge changes from topic "xl/a76ae-errata" into integration

* changes:
fix(cpus): workaround for Cortex-A76AE erratum 2371140
fix(cpus): workaround for Cortex-A76AE erratum 1969401
fix(cpus): workaround for Cortex-A76AE erratum 1931435
fix(cpus): workaround for Cortex-A76AE erratum 1931427

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fix(gicv3): add an isb between the ICC_SRE_EL2 and ICC_SRE_EL1 writes

While ICC_SRE_EL2.SRE is 0, ICC_SRE_EL1.SRE is RAZ/WI. Except for an
isb between the two writes, there is nothing to guarantee t

fix(gicv3): add an isb between the ICC_SRE_EL2 and ICC_SRE_EL1 writes

While ICC_SRE_EL2.SRE is 0, ICC_SRE_EL1.SRE is RAZ/WI. Except for an
isb between the two writes, there is nothing to guarantee that the
ICC_SRE_EL2.SRE write has taken effect by the time the ICC_SRE_EL1.SRE
write occurs. Add the isb to guarantee that the write is successful.

Change-Id: Ib84193f49e67ed0a64d6e2c6c71fb99b5b58a211
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(cm): do not check for AArch32 support to enable features

EL3 is running in AArch64 mode so it is always able to enable all
features. Some features are not implemented for AArch32 but that will b

fix(cm): do not check for AArch32 support to enable features

EL3 is running in AArch64 mode so it is always able to enable all
features. Some features are not implemented for AArch32 but that will be
handled architecturally on changing exception levels so we don't need to
worry about it. Always enable all features (checked on the FEAT_STATE
flag of course) and save ourselves the check.

To prevent confusion in future, the SCR bits that actually affect
AArch32 execution and must always be checked are moved up in the file
and grouped together, rather than being straddled by feature enablement.

Change-Id: I154957405befb750c03738d1989bfb12696fc79d
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "fix(intel): remove invalid SDM SMMU Stream ID register from bypass list" into integration

Merge "fix(intel): prevent invalid register rejection on non-A5F4 devices" into integration

Merge "style(qemu-sbsa): wrap declaration in braces for clang" into integration

style(qemu-sbsa): wrap declaration in braces for clang

Clang errors if a label is followed directly by a declaration.
The variable `struct platform_cpu_topology topology` must be
inside a block to a

style(qemu-sbsa): wrap declaration in braces for clang

Clang errors if a label is followed directly by a declaration.
The variable `struct platform_cpu_topology topology` must be
inside a block to avoid the C23-extension diagnostic:

```
plat/qemu/qemu_sbsa/sbsa_sip_svc.c:86:3:
error: label followed by a declaration is a C23 extension
[-Werror,-Wc23-extensions]
86 | struct platform_cpu_topology topology;
| ^
```

Change-Id: I005f3eb054f8f33128403c79659ae10989c78d63
Signed-off-by: Vineel Kovvuri[MSFT] <vineelko@microsoft.com>

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fix(cpus): workaround for Cortex-A725 erratum 3456106

Cortex-A725 erratum 3456106 is a Cat B erratum that applies
to revisions r0p0, r0p1 and r0p2, it is still open.

This erratum can be avoided by

fix(cpus): workaround for Cortex-A725 erratum 3456106

Cortex-A725 erratum 3456106 is a Cat B erratum that applies
to revisions r0p0, r0p1 and r0p2, it is still open.

This erratum can be avoided by having Speculation Barrier (SB)
instruction after the writes to the PSTATE.SSBS.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2832921/latest/

Change-Id: I10d1e8cb4da19ba4101a5617245ff75866707d25
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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Merge "feat(clk): add get_possible_parents_num callback" into integration

fix(cpus): workaround for Cortex-A65 erratum 1541130

Cortex-A65 erratum 1541130 is a Cat B erratum that applies
to r0p0, r1p0, r1p1, r1p2 revisions of the CPU and is still open.

This erratum can be

fix(cpus): workaround for Cortex-A65 erratum 1541130

Cortex-A65 erratum 1541130 is a Cat B erratum that applies
to r0p0, r1p0, r1p1, r1p2 revisions of the CPU and is still open.

This erratum can be avoided by disable stage1 page table walk for
lower Els (EL1 and EL0) in EL3, so 'AT' speculative fetch at any
point produces either the correct result or failure without TLB
allocation.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1065159/latest/

Change-Id: I72498f60f8449193ed4b5b2a9e7a08530e786ec3
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A725 erratum 3711914

Cortex-A725 erratum 3711914 is a Cat B erratum that applies
to revisions r0p0 and r0p1 and it is fixed in r0p2.

This erratum can be avoided by

fix(cpus): workaround for Cortex-A725 erratum 3711914

Cortex-A725 erratum 3711914 is a Cat B erratum that applies
to revisions r0p0 and r0p1 and it is fixed in r0p2.

This erratum can be avoided by inserting a DMB LD after each DSB ST instruction.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2832921/latest/

Change-Id: If3b9d3a0f495b3a172d3e6e5ca7afa8c30aeb4ea
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A725 erratum 2936490

Cortex-A725 erratum 2936490 is a Cat B erratum that applies
to revisions in r0p0, and is fixed in r0p1.

This erratum can be avoided by setting

fix(cpus): workaround for Cortex-A725 erratum 2936490

Cortex-A725 erratum 2936490 is a Cat B erratum that applies
to revisions in r0p0, and is fixed in r0p1.

This erratum can be avoided by setting CPUACTLR2_EL1[37] to 1.
Setting this bit is expected to have a negligible performance impact.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2832921/latest/

Change-Id: I9833f8831ba3735a94763791a65be11b95c00bdb
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A725 erratum 2874943

Cortex-A725 erratum 2874943 is a Cat B erratum that applies
to revision r0p0 when FEAT_SPE is enabled, it is fixed in r0p1.

This erratum can be

fix(cpus): workaround for Cortex-A725 erratum 2874943

Cortex-A725 erratum 2874943 is a Cat B erratum that applies
to revision r0p0 when FEAT_SPE is enabled, it is fixed in r0p1.

This erratum can be avoided by setting bits[58:57] to 0b11 in CPUACTLR_EL1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2832921/latest/

Change-Id: I686bbde8756d52afee92097ec05b97138b550025
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A65 erratum 1227419

Cortex-A65 erratum 1227419 is a Cat B erratum that applies
to r0p0, r1p0, it is fixed in r1p1.

This erratum can be avoided by setting CPUACTLR_E

fix(cpus): workaround for Cortex-A65 erratum 1227419

Cortex-A65 erratum 1227419 is a Cat B erratum that applies
to r0p0, r1p0, it is fixed in r1p1.

This erratum can be avoided by setting CPUACTLR_EL1[51] to 1.
This bit disables the cross-thread sharing in instruction uTLB.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1065159/latest/

Change-Id: I42371e7d53fce3a7e085bf0b348f080fa323fb51
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A65 erratum 1179935

Cortex-A65 erratum 1179935 is a Cat B erratum that applies
to r0p0, it is fixed in r1p0.

This erratum can be avoided by setting CPUACTLR_EL1[49]

fix(cpus): workaround for Cortex-A65 erratum 1179935

Cortex-A65 erratum 1179935 is a Cat B erratum that applies
to r0p0, it is fixed in r1p0.

This erratum can be avoided by setting CPUACTLR_EL1[49] to 1. The bit
prevents translation table walks from allocating lines into the
L1 cache. This has a negligible impact on performance when an
L2 cache is present.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1065159/latest/

Change-Id: Ie59a4897f849269a590d8fa2d25cceab5f2cba3c
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A76AE erratum 2371140

Cortex-A76AE erratum 2371140 is a Cat B erratum that applies
to all revisions <= r1p1, and is still open.

This erratum can be avoided by setti

fix(cpus): workaround for Cortex-A76AE erratum 2371140

Cortex-A76AE erratum 2371140 is a Cat B erratum that applies
to all revisions <= r1p1, and is still open.

This erratum can be avoided by setting CPUACTLR2_EL1[0] to 1. The
bit force PLDW/PFRM ST to behave like PLD/PRFM LD and not cause
invalidations to other PE caches. There might be a small performance
degradation to this workaround for certain workloads that share data.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1277541/1700/?lang=en

Change-Id: Id65846bebde1a0911ba11956202d0d255d3c8c82
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A76AE erratum 1969401

Cortex-A76AE erratum 1969401 is a Cat B erratum that applies
to r0p0 and r1p0, it is fixed in r1p1.

This erratum can be avoided by inserting a

fix(cpus): workaround for Cortex-A76AE erratum 1969401

Cortex-A76AE erratum 1969401 is a Cat B erratum that applies
to r0p0 and r1p0, it is fixed in r1p1.

This erratum can be avoided by inserting a DMB ST before acquire
atomic instructions without release semantics.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1277541/1700/?lang=en

Change-Id: I893452450d430833e6c5a8e33a1e37b708218576
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A76AE erratum 1931435

Cortex-A76AE erratum 1931435 is a Cat B erratum that applies
to r0p0 and r1p0, it is fixed in r1p1.

This erratum can be avoided by setting CPU

fix(cpus): workaround for Cortex-A76AE erratum 1931435

Cortex-A76AE erratum 1931435 is a Cat B erratum that applies
to r0p0 and r1p0, it is fixed in r1p1.

This erratum can be avoided by setting CPUACTLR_EL1[13] to 1. This bit
delays instruction fetch after branch misprediction. This workaround
will have a small impact on performance.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1277541/1700/?lang=en

Change-Id: I1baba8752f5f2e2ab5c873030e1f00cbb8cf1e60
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A76AE erratum 1931427

Cortex-A76AE erratum 1931427 is a Cat B erratum that applies
to r0p0 and r1p0, it is fixed in r1p1.

This erratum can be avoided by setting CPU

fix(cpus): workaround for Cortex-A76AE erratum 1931427

Cortex-A76AE erratum 1931427 is a Cat B erratum that applies
to r0p0 and r1p0, it is fixed in r1p1.

This erratum can be avoided by setting CPUACTLR2_EL1[2] to 1. The bit
to force Atomic Store operations to write-back memory to be performed
in the L1 data cache.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1277541/1700/?lang=en

Change-Id: I31566838f894372e5627abda8b0bea1505f11f5d
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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Merge "feat(imx8m): keep console at runtime when building TF-A/bl31 with DEBUG" into integration

Merge changes from topic "image_decryption" into integration

* changes:
feat(fvp): extend image decryption support for FVP
fix(io): add NULL check for spec io_open FIP