1 /* 2 * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2023, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 10 #include <arch.h> 11 #include <arch_helpers.h> 12 #include <common/debug.h> 13 #include <common/interrupt_props.h> 14 #include <drivers/arm/gic600_multichip.h> 15 #include <drivers/arm/gicv3.h> 16 #include <lib/spinlock.h> 17 #include <plat/common/platform.h> 18 19 #include "gicv3_private.h" 20 21 const gicv3_driver_data_t *gicv3_driver_data; 22 23 /* 24 * Spinlock to guard registers needing read-modify-write. APIs protected by this 25 * spinlock are used either at boot time (when only a single CPU is active), or 26 * when the system is fully coherent. 27 */ 28 static spinlock_t gic_lock; 29 30 /* 31 * Redistributor power operations are weakly bound so that they can be 32 * overridden 33 */ 34 #pragma weak gicv3_rdistif_off 35 #pragma weak gicv3_rdistif_on 36 37 /* Check for valid SGI/PPI or SPI interrupt ID */ 38 static bool is_valid_interrupt(unsigned int id); 39 40 /* 41 * Helper macros to save and restore GICR and GICD registers 42 * corresponding to their numbers to and from the context 43 */ 44 #define RESTORE_GICR_REG(base, ctx, name, i) \ 45 gicr_write_##name((base), (i), (ctx)->gicr_##name[(i)]) 46 47 #define SAVE_GICR_REG(base, ctx, name, i) \ 48 (ctx)->gicr_##name[(i)] = gicr_read_##name((base), (i)) 49 50 /* Helper macros to save and restore GICD registers to and from the context */ 51 #define RESTORE_GICD_REGS(base, ctx, intr_num, reg, REG) \ 52 do { \ 53 for (unsigned int int_id = MIN_SPI_ID; int_id < (intr_num);\ 54 int_id += (1U << REG##R_SHIFT)) { \ 55 gicd_write_##reg((base), int_id, \ 56 (ctx)->gicd_##reg[(int_id - MIN_SPI_ID) >> \ 57 REG##R_SHIFT]); \ 58 } \ 59 } while (false) 60 61 #define SAVE_GICD_REGS(base, ctx, intr_num, reg, REG) \ 62 do { \ 63 for (unsigned int int_id = MIN_SPI_ID; int_id < (intr_num);\ 64 int_id += (1U << REG##R_SHIFT)) { \ 65 (ctx)->gicd_##reg[(int_id - MIN_SPI_ID) >> \ 66 REG##R_SHIFT] = gicd_read_##reg((base), int_id); \ 67 } \ 68 } while (false) 69 70 #if GIC_EXT_INTID 71 #define RESTORE_GICD_EREGS(base, ctx, intr_num, reg, REG) \ 72 do { \ 73 for (unsigned int int_id = MIN_ESPI_ID; int_id < (intr_num);\ 74 int_id += (1U << REG##R_SHIFT)) { \ 75 gicd_write_##reg((base), int_id, \ 76 (ctx)->gicd_##reg[(int_id - (MIN_ESPI_ID - \ 77 round_up(TOTAL_SPI_INTR_NUM, 1U << REG##R_SHIFT)))\ 78 >> REG##R_SHIFT]); \ 79 } \ 80 } while (false) 81 82 #define SAVE_GICD_EREGS(base, ctx, intr_num, reg, REG) \ 83 do { \ 84 for (unsigned int int_id = MIN_ESPI_ID; int_id < (intr_num);\ 85 int_id += (1U << REG##R_SHIFT)) { \ 86 (ctx)->gicd_##reg[(int_id - (MIN_ESPI_ID - \ 87 round_up(TOTAL_SPI_INTR_NUM, 1U << REG##R_SHIFT)))\ 88 >> REG##R_SHIFT] = gicd_read_##reg((base), int_id);\ 89 } \ 90 } while (false) 91 #else 92 #define SAVE_GICD_EREGS(base, ctx, intr_num, reg, REG) 93 #define RESTORE_GICD_EREGS(base, ctx, intr_num, reg, REG) 94 #endif /* GIC_EXT_INTID */ 95 96 /******************************************************************************* 97 * This function initialises the ARM GICv3 driver in EL3 with provided platform 98 * inputs. 99 ******************************************************************************/ 100 void __init gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data) 101 { 102 unsigned int gic_version; 103 unsigned int gicv2_compat; 104 105 assert(plat_driver_data != NULL); 106 assert(plat_driver_data->gicd_base != 0U); 107 assert(plat_driver_data->rdistif_num != 0U); 108 assert(plat_driver_data->rdistif_base_addrs != NULL); 109 110 assert(IS_IN_EL3()); 111 112 assert((plat_driver_data->interrupt_props_num == 0U) || 113 (plat_driver_data->interrupt_props != NULL)); 114 115 /* Check for system register support */ 116 #ifndef __aarch64__ 117 assert((read_id_pfr1() & 118 (ID_PFR1_GIC_MASK << ID_PFR1_GIC_SHIFT)) != 0U); 119 #else 120 assert((read_id_aa64pfr0_el1() & 121 (ID_AA64PFR0_GIC_MASK << ID_AA64PFR0_GIC_SHIFT)) != 0U); 122 #endif /* !__aarch64__ */ 123 124 gic_version = gicd_read_pidr2(plat_driver_data->gicd_base); 125 gic_version >>= PIDR2_ARCH_REV_SHIFT; 126 gic_version &= PIDR2_ARCH_REV_MASK; 127 128 /* Check GIC version */ 129 #if !GIC_ENABLE_V4_EXTN 130 assert(gic_version == ARCH_REV_GICV3); 131 #endif 132 /* 133 * Find out whether the GIC supports the GICv2 compatibility mode. 134 * The ARE_S bit resets to 0 if supported 135 */ 136 gicv2_compat = gicd_read_ctlr(plat_driver_data->gicd_base); 137 gicv2_compat >>= CTLR_ARE_S_SHIFT; 138 gicv2_compat = gicv2_compat & CTLR_ARE_S_MASK; 139 140 if (plat_driver_data->gicr_base != 0U) { 141 /* 142 * Find the base address of each implemented Redistributor interface. 143 * The number of interfaces should be equal to the number of CPUs in the 144 * system. The memory for saving these addresses has to be allocated by 145 * the platform port 146 */ 147 gicv3_rdistif_base_addrs_probe(plat_driver_data->rdistif_base_addrs, 148 plat_driver_data->rdistif_num, 149 plat_driver_data->gicr_base, 150 plat_driver_data->mpidr_to_core_pos); 151 #if !HW_ASSISTED_COHERENCY 152 /* 153 * Flush the rdistif_base_addrs[] contents linked to the GICv3 driver. 154 */ 155 flush_dcache_range((uintptr_t)(plat_driver_data->rdistif_base_addrs), 156 plat_driver_data->rdistif_num * 157 sizeof(*(plat_driver_data->rdistif_base_addrs))); 158 #endif 159 } 160 gicv3_driver_data = plat_driver_data; 161 162 /* 163 * The GIC driver data is initialized by the primary CPU with caches 164 * enabled. When the secondary CPU boots up, it initializes the 165 * GICC/GICR interface with the caches disabled. Hence flush the 166 * driver data to ensure coherency. This is not required if the 167 * platform has HW_ASSISTED_COHERENCY enabled. 168 */ 169 #if !HW_ASSISTED_COHERENCY 170 flush_dcache_range((uintptr_t)&gicv3_driver_data, 171 sizeof(gicv3_driver_data)); 172 flush_dcache_range((uintptr_t)gicv3_driver_data, 173 sizeof(*gicv3_driver_data)); 174 #endif 175 gicv3_check_erratas_applies(plat_driver_data->gicd_base); 176 177 INFO("GICv%u with%s legacy support detected.\n", gic_version, 178 (gicv2_compat == 0U) ? "" : "out"); 179 INFO("ARM GICv%u driver initialized in EL3\n", gic_version); 180 } 181 182 /******************************************************************************* 183 * This function initialises the GIC distributor interface based upon the data 184 * provided by the platform while initialising the driver. 185 ******************************************************************************/ 186 void __init gicv3_distif_init(void) 187 { 188 unsigned int bitmap; 189 190 assert(gicv3_driver_data != NULL); 191 assert(gicv3_driver_data->gicd_base != 0U); 192 193 assert(IS_IN_EL3()); 194 195 /* 196 * Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring 197 * the ARE_S bit. The Distributor might generate a system error 198 * otherwise. 199 */ 200 gicd_clr_ctlr(gicv3_driver_data->gicd_base, 201 CTLR_ENABLE_G0_BIT | 202 CTLR_ENABLE_G1S_BIT | 203 CTLR_ENABLE_G1NS_BIT, 204 RWP_TRUE); 205 206 /* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */ 207 gicd_set_ctlr(gicv3_driver_data->gicd_base, 208 CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE); 209 210 /* Set the default attribute of all (E)SPIs */ 211 gicv3_spis_config_defaults(gicv3_driver_data->gicd_base); 212 213 bitmap = gicv3_secure_spis_config_props( 214 gicv3_driver_data->gicd_base, 215 gicv3_driver_data->interrupt_props, 216 gicv3_driver_data->interrupt_props_num); 217 218 /* Enable the secure (E)SPIs now that they have been configured */ 219 gicd_set_ctlr(gicv3_driver_data->gicd_base, bitmap, RWP_TRUE); 220 } 221 222 /******************************************************************************* 223 * This function initialises the GIC Redistributor interface of the calling CPU 224 * (identified by the 'proc_num' parameter) based upon the data provided by the 225 * platform while initialising the driver. 226 ******************************************************************************/ 227 void gicv3_rdistif_init(unsigned int proc_num) 228 { 229 uintptr_t gicr_base; 230 unsigned int bitmap; 231 uint32_t ctlr; 232 233 assert(gicv3_driver_data != NULL); 234 assert(proc_num < gicv3_driver_data->rdistif_num); 235 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 236 assert(gicv3_driver_data->gicd_base != 0U); 237 238 ctlr = gicd_read_ctlr(gicv3_driver_data->gicd_base); 239 assert((ctlr & CTLR_ARE_S_BIT) != 0U); 240 241 assert(IS_IN_EL3()); 242 243 /* Power on redistributor */ 244 gicv3_rdistif_on(proc_num); 245 246 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 247 assert(gicr_base != 0U); 248 249 /* Set the default attribute of all SGIs and (E)PPIs */ 250 gicv3_ppi_sgi_config_defaults(gicr_base); 251 252 bitmap = gicv3_secure_ppi_sgi_config_props(gicr_base, 253 gicv3_driver_data->interrupt_props, 254 gicv3_driver_data->interrupt_props_num); 255 256 /* Enable interrupt groups as required, if not already */ 257 if ((ctlr & bitmap) != bitmap) { 258 gicd_set_ctlr(gicv3_driver_data->gicd_base, bitmap, RWP_TRUE); 259 } 260 } 261 262 /******************************************************************************* 263 * Functions to perform power operations on GIC Redistributor 264 ******************************************************************************/ 265 void gicv3_rdistif_off(unsigned int proc_num) 266 { 267 } 268 269 void gicv3_rdistif_on(unsigned int proc_num) 270 { 271 } 272 273 /******************************************************************************* 274 * This function enables the GIC CPU interface of the calling CPU using only 275 * system register accesses. 276 ******************************************************************************/ 277 void gicv3_cpuif_enable(unsigned int proc_num) 278 { 279 uintptr_t gicr_base; 280 u_register_t scr_el3; 281 unsigned int icc_sre_el3; 282 283 assert(gicv3_driver_data != NULL); 284 assert(proc_num < gicv3_driver_data->rdistif_num); 285 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 286 assert(IS_IN_EL3()); 287 288 /* Mark the connected core as awake */ 289 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 290 gicv3_rdistif_mark_core_awake(gicr_base); 291 292 /* Disable the legacy interrupt bypass */ 293 icc_sre_el3 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT; 294 295 /* 296 * Enable system register access for EL3 and allow lower exception 297 * levels to configure the same for themselves. If the legacy mode is 298 * not supported, the SRE bit is RAO/WI 299 */ 300 icc_sre_el3 |= (ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT); 301 write_icc_sre_el3(read_icc_sre_el3() | icc_sre_el3); 302 303 scr_el3 = read_scr_el3(); 304 305 /* 306 * Switch to NS state to write Non secure ICC_SRE_EL1 and 307 * ICC_SRE_EL2 registers. 308 */ 309 write_scr_el3(scr_el3 | SCR_NS_BIT); 310 isb(); 311 312 write_icc_sre_el2(read_icc_sre_el2() | icc_sre_el3); 313 isb(); 314 write_icc_sre_el1(ICC_SRE_SRE_BIT); 315 isb(); 316 317 /* Switch to secure state. */ 318 write_scr_el3(scr_el3 & (~SCR_NS_BIT)); 319 isb(); 320 321 /* Write the secure ICC_SRE_EL1 register */ 322 write_icc_sre_el1(ICC_SRE_SRE_BIT); 323 isb(); 324 325 /* Program the idle priority in the PMR */ 326 write_icc_pmr_el1(GIC_PRI_MASK); 327 328 /* Enable Group0 interrupts */ 329 write_icc_igrpen0_el1(IGRPEN1_EL1_ENABLE_G0_BIT); 330 331 /* Enable Group1 Secure interrupts */ 332 write_icc_igrpen1_el3(read_icc_igrpen1_el3() | 333 IGRPEN1_EL3_ENABLE_G1S_BIT); 334 /* and restore the original */ 335 write_scr_el3(scr_el3); 336 isb(); 337 /* Add DSB to ensure visibility of System register writes */ 338 dsb(); 339 } 340 341 /******************************************************************************* 342 * This function disables the GIC CPU interface of the calling CPU using 343 * only system register accesses. 344 ******************************************************************************/ 345 void gicv3_cpuif_disable(unsigned int proc_num) 346 { 347 uintptr_t gicr_base; 348 349 assert(gicv3_driver_data != NULL); 350 assert(proc_num < gicv3_driver_data->rdistif_num); 351 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 352 353 assert(IS_IN_EL3()); 354 355 /* Disable legacy interrupt bypass */ 356 write_icc_sre_el3(read_icc_sre_el3() | 357 (ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT)); 358 359 /* Disable Group0 interrupts */ 360 write_icc_igrpen0_el1(read_icc_igrpen0_el1() & 361 ~IGRPEN1_EL1_ENABLE_G0_BIT); 362 363 /* Disable Group1 Secure and Non-Secure interrupts */ 364 write_icc_igrpen1_el3(read_icc_igrpen1_el3() & 365 ~(IGRPEN1_EL3_ENABLE_G1NS_BIT | 366 IGRPEN1_EL3_ENABLE_G1S_BIT)); 367 368 /* Synchronise accesses to group enable registers */ 369 isb(); 370 /* Add DSB to ensure visibility of System register writes */ 371 dsb(); 372 373 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 374 assert(gicr_base != 0UL); 375 376 /* 377 * dsb() already issued previously after clearing the CPU group 378 * enabled, apply below workaround to toggle the "DPG*" 379 * bits of GICR_CTLR register for unblocking event. 380 */ 381 gicv3_apply_errata_wa_2384374(gicr_base); 382 383 /* Mark the connected core as asleep */ 384 gicv3_rdistif_mark_core_asleep(gicr_base); 385 } 386 387 /******************************************************************************* 388 * This function returns the id of the highest priority pending interrupt at 389 * the GIC cpu interface. 390 ******************************************************************************/ 391 unsigned int gicv3_get_pending_interrupt_id(void) 392 { 393 unsigned int id; 394 395 assert(IS_IN_EL3()); 396 id = (uint32_t)read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK; 397 398 /* 399 * If the ID is special identifier corresponding to G1S or G1NS 400 * interrupt, then read the highest pending group 1 interrupt. 401 */ 402 if ((id == PENDING_G1S_INTID) || (id == PENDING_G1NS_INTID)) { 403 return (uint32_t)read_icc_hppir1_el1() & HPPIR1_EL1_INTID_MASK; 404 } 405 406 return id; 407 } 408 409 /******************************************************************************* 410 * This function returns the type of the highest priority pending interrupt at 411 * the GIC cpu interface. The return values can be one of the following : 412 * PENDING_G1S_INTID : The interrupt type is secure Group 1. 413 * PENDING_G1NS_INTID : The interrupt type is non secure Group 1. 414 * 0 - 1019 : The interrupt type is secure Group 0. 415 * GIC_SPURIOUS_INTERRUPT : there is no pending interrupt with 416 * sufficient priority to be signaled 417 ******************************************************************************/ 418 unsigned int gicv3_get_pending_interrupt_type(void) 419 { 420 assert(IS_IN_EL3()); 421 return (uint32_t)read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK; 422 } 423 424 /******************************************************************************* 425 * This function returns the group that has been configured under by the 426 * interrupt controller for the given interrupt id i.e. either group0 or group1 427 * Secure / Non Secure. The return value can be one of the following : 428 * INTR_GROUP0 : The interrupt type is a Secure Group 0 interrupt 429 * INTR_GROUP1S : The interrupt type is a Secure Group 1 secure interrupt 430 * INTR_GROUP1NS: The interrupt type is a Secure Group 1 non secure 431 * interrupt. 432 ******************************************************************************/ 433 unsigned int gicv3_get_interrupt_group(unsigned int id, unsigned int proc_num) 434 { 435 unsigned int igroup, grpmodr; 436 uintptr_t gicr_base; 437 uintptr_t gicd_base; 438 439 assert(IS_IN_EL3()); 440 assert(gicv3_driver_data != NULL); 441 442 /* Ensure the parameters are valid */ 443 assert((id < PENDING_G1S_INTID) || (id >= MIN_LPI_ID)); 444 assert(proc_num < gicv3_driver_data->rdistif_num); 445 446 /* All LPI interrupts are Group 1 non secure */ 447 if (id >= MIN_LPI_ID) { 448 return INTR_GROUP1NS; 449 } 450 451 if (!is_valid_interrupt(id)) { 452 panic(); 453 } 454 455 /* Check interrupt ID */ 456 if (IS_SGI_PPI(id)) { 457 /* SGIs: 0-15, PPIs: 16-31, EPPIs: 1056-1119 */ 458 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 459 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 460 igroup = gicr_get_igroupr(gicr_base, id); 461 grpmodr = gicr_get_igrpmodr(gicr_base, id); 462 } else { 463 /* SPIs: 32-1019, ESPIs: 4096-5119 */ 464 assert(gicv3_driver_data->gicd_base != 0U); 465 gicd_base = gicv3_get_multichip_base(id, gicv3_driver_data->gicd_base); 466 igroup = gicd_get_igroupr(gicd_base, id); 467 grpmodr = gicd_get_igrpmodr(gicd_base, id); 468 } 469 470 /* 471 * If the IGROUP bit is set, then it is a Group 1 Non secure 472 * interrupt 473 */ 474 if (igroup != 0U) { 475 return INTR_GROUP1NS; 476 } 477 478 /* If the GRPMOD bit is set, then it is a Group 1 Secure interrupt */ 479 if (grpmodr != 0U) { 480 return INTR_GROUP1S; 481 } 482 483 /* Else it is a Group 0 Secure interrupt */ 484 return INTR_GROUP0; 485 } 486 487 /***************************************************************************** 488 * Function to save and disable the GIC ITS register context. The power 489 * management of GIC ITS is implementation-defined and this function doesn't 490 * save any memory structures required to support ITS. As the sequence to save 491 * this state is implementation defined, it should be executed in platform 492 * specific code. Calling this function alone and then powering down the GIC and 493 * ITS without implementing the aforementioned platform specific code will 494 * corrupt the ITS state. 495 * 496 * This function must be invoked after the GIC CPU interface is disabled. 497 *****************************************************************************/ 498 void gicv3_its_save_disable(uintptr_t gits_base, 499 gicv3_its_ctx_t * const its_ctx) 500 { 501 unsigned int i; 502 503 assert(gicv3_driver_data != NULL); 504 assert(IS_IN_EL3()); 505 assert(its_ctx != NULL); 506 assert(gits_base != 0U); 507 508 its_ctx->gits_ctlr = gits_read_ctlr(gits_base); 509 510 /* Disable the ITS */ 511 gits_write_ctlr(gits_base, its_ctx->gits_ctlr & ~GITS_CTLR_ENABLED_BIT); 512 513 /* Wait for quiescent state */ 514 gits_wait_for_quiescent_bit(gits_base); 515 516 its_ctx->gits_cbaser = gits_read_cbaser(gits_base); 517 its_ctx->gits_cwriter = gits_read_cwriter(gits_base); 518 519 for (i = 0U; i < ARRAY_SIZE(its_ctx->gits_baser); i++) { 520 its_ctx->gits_baser[i] = gits_read_baser(gits_base, i); 521 } 522 } 523 524 /***************************************************************************** 525 * Function to restore the GIC ITS register context. The power 526 * management of GIC ITS is implementation defined and this function doesn't 527 * restore any memory structures required to support ITS. The assumption is 528 * that these structures are in memory and are retained during system suspend. 529 * 530 * This must be invoked before the GIC CPU interface is enabled. 531 *****************************************************************************/ 532 void gicv3_its_restore(uintptr_t gits_base, 533 const gicv3_its_ctx_t * const its_ctx) 534 { 535 unsigned int i; 536 537 assert(gicv3_driver_data != NULL); 538 assert(IS_IN_EL3()); 539 assert(its_ctx != NULL); 540 assert(gits_base != 0U); 541 542 /* Assert that the GITS is disabled and quiescent */ 543 assert((gits_read_ctlr(gits_base) & GITS_CTLR_ENABLED_BIT) == 0U); 544 assert((gits_read_ctlr(gits_base) & GITS_CTLR_QUIESCENT_BIT) != 0U); 545 546 gits_write_cbaser(gits_base, its_ctx->gits_cbaser); 547 gits_write_cwriter(gits_base, its_ctx->gits_cwriter); 548 549 for (i = 0U; i < ARRAY_SIZE(its_ctx->gits_baser); i++) { 550 gits_write_baser(gits_base, i, its_ctx->gits_baser[i]); 551 } 552 553 /* Restore the ITS CTLR but leave the ITS disabled */ 554 gits_write_ctlr(gits_base, its_ctx->gits_ctlr & ~GITS_CTLR_ENABLED_BIT); 555 } 556 557 /***************************************************************************** 558 * Function to save the GIC Redistributor register context. This function 559 * must be invoked after CPU interface disable and prior to Distributor save. 560 *****************************************************************************/ 561 void gicv3_rdistif_save(unsigned int proc_num, 562 gicv3_redist_ctx_t * const rdist_ctx) 563 { 564 uintptr_t gicr_base; 565 unsigned int i, ppi_regs_num, regs_num; 566 567 assert(gicv3_driver_data != NULL); 568 assert(proc_num < gicv3_driver_data->rdistif_num); 569 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 570 assert(IS_IN_EL3()); 571 assert(rdist_ctx != NULL); 572 573 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 574 575 #if GIC_EXT_INTID 576 /* Calculate number of PPI registers */ 577 ppi_regs_num = (unsigned int)((gicr_read_typer(gicr_base) >> 578 TYPER_PPI_NUM_SHIFT) & TYPER_PPI_NUM_MASK) + 1; 579 /* All other values except PPInum [0-2] are reserved */ 580 if (ppi_regs_num > 3U) { 581 ppi_regs_num = 1U; 582 } 583 #else 584 ppi_regs_num = 1U; 585 #endif 586 /* 587 * Wait for any write to GICR_CTLR to complete before trying to save any 588 * state. 589 */ 590 gicr_wait_for_pending_write(gicr_base); 591 592 rdist_ctx->gicr_ctlr = gicr_read_ctlr(gicr_base); 593 594 rdist_ctx->gicr_propbaser = gicr_read_propbaser(gicr_base); 595 rdist_ctx->gicr_pendbaser = gicr_read_pendbaser(gicr_base); 596 597 /* 32 interrupt IDs per register */ 598 for (i = 0U; i < ppi_regs_num; ++i) { 599 SAVE_GICR_REG(gicr_base, rdist_ctx, igroupr, i); 600 SAVE_GICR_REG(gicr_base, rdist_ctx, isenabler, i); 601 SAVE_GICR_REG(gicr_base, rdist_ctx, ispendr, i); 602 SAVE_GICR_REG(gicr_base, rdist_ctx, isactiver, i); 603 SAVE_GICR_REG(gicr_base, rdist_ctx, igrpmodr, i); 604 } 605 606 /* 16 interrupt IDs per GICR_ICFGR register */ 607 regs_num = ppi_regs_num << 1; 608 for (i = 0U; i < regs_num; ++i) { 609 SAVE_GICR_REG(gicr_base, rdist_ctx, icfgr, i); 610 } 611 612 rdist_ctx->gicr_nsacr = gicr_read_nsacr(gicr_base); 613 614 /* 4 interrupt IDs per GICR_IPRIORITYR register */ 615 regs_num = ppi_regs_num << 3; 616 for (i = 0U; i < regs_num; ++i) { 617 rdist_ctx->gicr_ipriorityr[i] = 618 gicr_ipriorityr_read(gicr_base, i); 619 } 620 621 /* 622 * Call the pre-save hook that implements the IMP DEF sequence that may 623 * be required on some GIC implementations. As this may need to access 624 * the Redistributor registers, we pass it proc_num. 625 */ 626 gicv3_distif_pre_save(proc_num); 627 } 628 629 /***************************************************************************** 630 * Function to restore the GIC Redistributor register context. We disable 631 * LPI and per-cpu interrupts before we start restore of the Redistributor. 632 * This function must be invoked after Distributor restore but prior to 633 * CPU interface enable. The pending and active interrupts are restored 634 * after the interrupts are fully configured and enabled. 635 *****************************************************************************/ 636 void gicv3_rdistif_init_restore(unsigned int proc_num, 637 const gicv3_redist_ctx_t * const rdist_ctx) 638 { 639 uintptr_t gicr_base; 640 unsigned int i, ppi_regs_num, regs_num; 641 642 assert(gicv3_driver_data != NULL); 643 assert(proc_num < gicv3_driver_data->rdistif_num); 644 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 645 assert(IS_IN_EL3()); 646 assert(rdist_ctx != NULL); 647 648 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 649 650 #if GIC_EXT_INTID 651 /* Calculate number of PPI registers */ 652 ppi_regs_num = (unsigned int)((gicr_read_typer(gicr_base) >> 653 TYPER_PPI_NUM_SHIFT) & TYPER_PPI_NUM_MASK) + 1; 654 /* All other values except PPInum [0-2] are reserved */ 655 if (ppi_regs_num > 3U) { 656 ppi_regs_num = 1U; 657 } 658 #else 659 ppi_regs_num = 1U; 660 #endif 661 /* Power on redistributor */ 662 gicv3_rdistif_on(proc_num); 663 664 /* 665 * Call the post-restore hook that implements the IMP DEF sequence that 666 * may be required on some GIC implementations. As this may need to 667 * access the Redistributor registers, we pass it proc_num. 668 */ 669 gicv3_distif_post_restore(proc_num); 670 671 /* 672 * Disable all SGIs (imp. def.)/(E)PPIs before configuring them. 673 * This is a more scalable approach as it avoids clearing the enable 674 * bits in the GICD_CTLR. 675 */ 676 for (i = 0U; i < ppi_regs_num; ++i) { 677 gicr_write_icenabler(gicr_base, i, ~0U); 678 } 679 680 /* Wait for pending writes to GICR_ICENABLER */ 681 gicr_wait_for_pending_write(gicr_base); 682 683 /* 684 * Disable the LPIs to avoid unpredictable behavior when writing to 685 * GICR_PROPBASER and GICR_PENDBASER. 686 */ 687 gicr_write_ctlr(gicr_base, 688 rdist_ctx->gicr_ctlr & ~(GICR_CTLR_EN_LPIS_BIT)); 689 690 gicr_wait_for_pending_write(gicr_base); 691 692 /* Restore registers' content */ 693 gicr_write_propbaser(gicr_base, rdist_ctx->gicr_propbaser); 694 gicr_write_pendbaser(gicr_base, rdist_ctx->gicr_pendbaser); 695 696 /* 32 interrupt IDs per register */ 697 for (i = 0U; i < ppi_regs_num; ++i) { 698 RESTORE_GICR_REG(gicr_base, rdist_ctx, igroupr, i); 699 RESTORE_GICR_REG(gicr_base, rdist_ctx, igrpmodr, i); 700 } 701 702 /* 4 interrupt IDs per GICR_IPRIORITYR register */ 703 regs_num = ppi_regs_num << 3; 704 for (i = 0U; i < regs_num; ++i) { 705 gicr_ipriorityr_write(gicr_base, i, 706 rdist_ctx->gicr_ipriorityr[i]); 707 } 708 709 /* 16 interrupt IDs per GICR_ICFGR register */ 710 regs_num = ppi_regs_num << 1; 711 for (i = 0U; i < regs_num; ++i) { 712 RESTORE_GICR_REG(gicr_base, rdist_ctx, icfgr, i); 713 } 714 715 gicr_write_nsacr(gicr_base, rdist_ctx->gicr_nsacr); 716 717 /* Restore after group and priorities are set. 718 * 32 interrupt IDs per register 719 */ 720 for (i = 0U; i < ppi_regs_num; ++i) { 721 RESTORE_GICR_REG(gicr_base, rdist_ctx, ispendr, i); 722 RESTORE_GICR_REG(gicr_base, rdist_ctx, isactiver, i); 723 } 724 725 /* 726 * Wait for all writes to the Distributor to complete before enabling 727 * the SGI and (E)PPIs. 728 */ 729 gicr_wait_for_upstream_pending_write(gicr_base); 730 731 /* 32 interrupt IDs per GICR_ISENABLER register */ 732 for (i = 0U; i < ppi_regs_num; ++i) { 733 RESTORE_GICR_REG(gicr_base, rdist_ctx, isenabler, i); 734 } 735 736 /* 737 * Restore GICR_CTLR.Enable_LPIs bit and wait for pending writes in case 738 * the first write to GICR_CTLR was still in flight (this write only 739 * restores GICR_CTLR.Enable_LPIs and no waiting is required for this 740 * bit). 741 */ 742 gicr_write_ctlr(gicr_base, rdist_ctx->gicr_ctlr); 743 gicr_wait_for_pending_write(gicr_base); 744 } 745 746 /***************************************************************************** 747 * Function to save the GIC Distributor register context. This function 748 * must be invoked after CPU interface disable and Redistributor save. 749 *****************************************************************************/ 750 void gicv3_distif_save(gicv3_dist_ctx_t * const dist_ctx) 751 { 752 assert(gicv3_driver_data != NULL); 753 assert(gicv3_driver_data->gicd_base != 0U); 754 assert(IS_IN_EL3()); 755 assert(dist_ctx != NULL); 756 757 uintptr_t gicd_base = gicv3_driver_data->gicd_base; 758 unsigned int num_ints = gicv3_get_spi_limit(gicd_base); 759 #if GIC_EXT_INTID 760 unsigned int num_eints = gicv3_get_espi_limit(gicd_base); 761 #endif 762 763 /* Wait for pending write to complete */ 764 gicd_wait_for_pending_write(gicd_base); 765 766 /* Save the GICD_CTLR */ 767 dist_ctx->gicd_ctlr = gicd_read_ctlr(gicd_base); 768 769 /* Save GICD_IGROUPR for INTIDs 32 - 1019 */ 770 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUP); 771 772 /* Save GICD_IGROUPRE for INTIDs 4096 - 5119 */ 773 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, igroupr, IGROUP); 774 775 /* Save GICD_ISENABLER for INT_IDs 32 - 1019 */ 776 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, isenabler, ISENABLE); 777 778 /* Save GICD_ISENABLERE for INT_IDs 4096 - 5119 */ 779 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, isenabler, ISENABLE); 780 781 /* Save GICD_ISPENDR for INTIDs 32 - 1019 */ 782 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, ispendr, ISPEND); 783 784 /* Save GICD_ISPENDRE for INTIDs 4096 - 5119 */ 785 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, ispendr, ISPEND); 786 787 /* Save GICD_ISACTIVER for INTIDs 32 - 1019 */ 788 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, isactiver, ISACTIVE); 789 790 /* Save GICD_ISACTIVERE for INTIDs 4096 - 5119 */ 791 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, isactiver, ISACTIVE); 792 793 /* Save GICD_IPRIORITYR for INTIDs 32 - 1019 */ 794 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, ipriorityr, IPRIORITY); 795 796 /* Save GICD_IPRIORITYRE for INTIDs 4096 - 5119 */ 797 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, ipriorityr, IPRIORITY); 798 799 /* Save GICD_ICFGR for INTIDs 32 - 1019 */ 800 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, icfgr, ICFG); 801 802 /* Save GICD_ICFGRE for INTIDs 4096 - 5119 */ 803 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, icfgr, ICFG); 804 805 /* Save GICD_IGRPMODR for INTIDs 32 - 1019 */ 806 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, igrpmodr, IGRPMOD); 807 808 /* Save GICD_IGRPMODRE for INTIDs 4096 - 5119 */ 809 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, igrpmodr, IGRPMOD); 810 811 /* Save GICD_NSACR for INTIDs 32 - 1019 */ 812 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, nsacr, NSAC); 813 814 /* Save GICD_NSACRE for INTIDs 4096 - 5119 */ 815 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, nsacr, NSAC); 816 817 /* Save GICD_IROUTER for INTIDs 32 - 1019 */ 818 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, irouter, IROUTE); 819 820 /* Save GICD_IROUTERE for INTIDs 4096 - 5119 */ 821 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, irouter, IROUTE); 822 823 /* 824 * GICD_ITARGETSR<n> and GICD_SPENDSGIR<n> are RAZ/WI when 825 * GICD_CTLR.ARE_(S|NS) bits are set which is the case for our GICv3 826 * driver. 827 */ 828 } 829 830 /***************************************************************************** 831 * Function to restore the GIC Distributor register context. We disable G0, G1S 832 * and G1NS interrupt groups before we start restore of the Distributor. This 833 * function must be invoked prior to Redistributor restore and CPU interface 834 * enable. The pending and active interrupts are restored after the interrupts 835 * are fully configured and enabled. 836 *****************************************************************************/ 837 void gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx) 838 { 839 assert(gicv3_driver_data != NULL); 840 assert(gicv3_driver_data->gicd_base != 0U); 841 assert(IS_IN_EL3()); 842 assert(dist_ctx != NULL); 843 844 uintptr_t gicd_base = gicv3_driver_data->gicd_base; 845 846 /* 847 * Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring 848 * the ARE_S bit. The Distributor might generate a system error 849 * otherwise. 850 */ 851 gicd_clr_ctlr(gicd_base, 852 CTLR_ENABLE_G0_BIT | 853 CTLR_ENABLE_G1S_BIT | 854 CTLR_ENABLE_G1NS_BIT, 855 RWP_TRUE); 856 857 /* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */ 858 gicd_set_ctlr(gicd_base, CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE); 859 860 unsigned int num_ints = gicv3_get_spi_limit(gicd_base); 861 #if GIC_EXT_INTID 862 unsigned int num_eints = gicv3_get_espi_limit(gicd_base); 863 #endif 864 /* Restore GICD_IGROUPR for INTIDs 32 - 1019 */ 865 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUP); 866 867 /* Restore GICD_IGROUPRE for INTIDs 4096 - 5119 */ 868 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, igroupr, IGROUP); 869 870 /* Restore GICD_IPRIORITYR for INTIDs 32 - 1019 */ 871 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, ipriorityr, IPRIORITY); 872 873 /* Restore GICD_IPRIORITYRE for INTIDs 4096 - 5119 */ 874 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, ipriorityr, IPRIORITY); 875 876 /* Restore GICD_ICFGR for INTIDs 32 - 1019 */ 877 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, icfgr, ICFG); 878 879 /* Restore GICD_ICFGRE for INTIDs 4096 - 5119 */ 880 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, icfgr, ICFG); 881 882 /* Restore GICD_IGRPMODR for INTIDs 32 - 1019 */ 883 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igrpmodr, IGRPMOD); 884 885 /* Restore GICD_IGRPMODRE for INTIDs 4096 - 5119 */ 886 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, igrpmodr, IGRPMOD); 887 888 /* Restore GICD_NSACR for INTIDs 32 - 1019 */ 889 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, nsacr, NSAC); 890 891 /* Restore GICD_NSACRE for INTIDs 4096 - 5119 */ 892 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, nsacr, NSAC); 893 894 /* Restore GICD_IROUTER for INTIDs 32 - 1019 */ 895 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, irouter, IROUTE); 896 897 /* Restore GICD_IROUTERE for INTIDs 4096 - 5119 */ 898 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, irouter, IROUTE); 899 900 /* 901 * Restore ISENABLER(E), ISPENDR(E) and ISACTIVER(E) after 902 * the interrupts are configured. 903 */ 904 905 /* Restore GICD_ISENABLER for INT_IDs 32 - 1019 */ 906 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, isenabler, ISENABLE); 907 908 /* Restore GICD_ISENABLERE for INT_IDs 4096 - 5119 */ 909 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, isenabler, ISENABLE); 910 911 /* Restore GICD_ISPENDR for INTIDs 32 - 1019 */ 912 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, ispendr, ISPEND); 913 914 /* Restore GICD_ISPENDRE for INTIDs 4096 - 5119 */ 915 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, ispendr, ISPEND); 916 917 /* Restore GICD_ISACTIVER for INTIDs 32 - 1019 */ 918 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, isactiver, ISACTIVE); 919 920 /* Restore GICD_ISACTIVERE for INTIDs 4096 - 5119 */ 921 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, isactiver, ISACTIVE); 922 923 /* Restore the GICD_CTLR */ 924 gicd_write_ctlr(gicd_base, dist_ctx->gicd_ctlr); 925 gicd_wait_for_pending_write(gicd_base); 926 } 927 928 /******************************************************************************* 929 * This function gets the priority of the interrupt the processor is currently 930 * servicing. 931 ******************************************************************************/ 932 unsigned int gicv3_get_running_priority(void) 933 { 934 return (unsigned int)read_icc_rpr_el1(); 935 } 936 937 /******************************************************************************* 938 * This function checks if the interrupt identified by id is active (whether the 939 * state is either active, or active and pending). The proc_num is used if the 940 * interrupt is SGI or (E)PPI and programs the corresponding Redistributor 941 * interface. 942 ******************************************************************************/ 943 unsigned int gicv3_get_interrupt_active(unsigned int id, unsigned int proc_num) 944 { 945 uintptr_t gicd_base; 946 947 assert(gicv3_driver_data != NULL); 948 assert(gicv3_driver_data->gicd_base != 0U); 949 assert(proc_num < gicv3_driver_data->rdistif_num); 950 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 951 952 if (!is_valid_interrupt(id)) { 953 panic(); 954 } 955 /* Check interrupt ID */ 956 if (IS_SGI_PPI(id)) { 957 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 958 return gicr_get_isactiver( 959 gicv3_driver_data->rdistif_base_addrs[proc_num], id); 960 } 961 962 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 963 gicd_base = gicv3_get_multichip_base(id, gicv3_driver_data->gicd_base); 964 return gicd_get_isactiver(gicd_base, id); 965 } 966 967 /******************************************************************************* 968 * This function enables the interrupt identified by id. The proc_num 969 * is used if the interrupt is SGI or PPI, and programs the corresponding 970 * Redistributor interface. 971 ******************************************************************************/ 972 void gicv3_enable_interrupt(unsigned int id, unsigned int proc_num) 973 { 974 uintptr_t gicd_base; 975 976 assert(gicv3_driver_data != NULL); 977 assert(gicv3_driver_data->gicd_base != 0U); 978 assert(proc_num < gicv3_driver_data->rdistif_num); 979 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 980 981 /* 982 * Ensure that any shared variable updates depending on out of band 983 * interrupt trigger are observed before enabling interrupt. 984 */ 985 dsbishst(); 986 if (!is_valid_interrupt(id)) { 987 panic(); 988 } 989 /* Check interrupt ID */ 990 if (IS_SGI_PPI(id)) { 991 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 992 gicr_set_isenabler( 993 gicv3_driver_data->rdistif_base_addrs[proc_num], id); 994 } else { 995 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 996 gicd_base = gicv3_get_multichip_base(id, gicv3_driver_data->gicd_base); 997 gicd_set_isenabler(gicd_base, id); 998 } 999 } 1000 1001 /******************************************************************************* 1002 * This function disables the interrupt identified by id. The proc_num 1003 * is used if the interrupt is SGI or PPI, and programs the corresponding 1004 * Redistributor interface. 1005 ******************************************************************************/ 1006 void gicv3_disable_interrupt(unsigned int id, unsigned int proc_num) 1007 { 1008 uintptr_t gicd_base; 1009 1010 assert(gicv3_driver_data != NULL); 1011 assert(gicv3_driver_data->gicd_base != 0U); 1012 assert(proc_num < gicv3_driver_data->rdistif_num); 1013 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 1014 1015 /* 1016 * Disable interrupt, and ensure that any shared variable updates 1017 * depending on out of band interrupt trigger are observed afterwards. 1018 */ 1019 if (!is_valid_interrupt(id)) { 1020 panic(); 1021 } 1022 /* Check interrupt ID */ 1023 if (IS_SGI_PPI(id)) { 1024 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 1025 gicr_set_icenabler( 1026 gicv3_driver_data->rdistif_base_addrs[proc_num], id); 1027 1028 /* Write to clear enable requires waiting for pending writes */ 1029 gicr_wait_for_pending_write( 1030 gicv3_driver_data->rdistif_base_addrs[proc_num]); 1031 } else { 1032 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 1033 gicd_base = gicv3_get_multichip_base(id, gicv3_driver_data->gicd_base); 1034 gicd_set_icenabler(gicd_base, id); 1035 1036 /* Write to clear enable requires waiting for pending writes */ 1037 gicd_wait_for_pending_write(gicd_base); 1038 } 1039 1040 dsbishst(); 1041 } 1042 1043 /******************************************************************************* 1044 * This function sets the interrupt priority as supplied for the given interrupt 1045 * id. 1046 ******************************************************************************/ 1047 void gicv3_set_interrupt_priority(unsigned int id, unsigned int proc_num, 1048 unsigned int priority) 1049 { 1050 uintptr_t gicr_base; 1051 uintptr_t gicd_base; 1052 1053 assert(gicv3_driver_data != NULL); 1054 assert(gicv3_driver_data->gicd_base != 0U); 1055 assert(proc_num < gicv3_driver_data->rdistif_num); 1056 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 1057 1058 if (!is_valid_interrupt(id)) { 1059 panic(); 1060 } 1061 /* Check interrupt ID */ 1062 if (IS_SGI_PPI(id)) { 1063 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 1064 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 1065 gicr_set_ipriorityr(gicr_base, id, priority); 1066 } else { 1067 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 1068 gicd_base = gicv3_get_multichip_base(id, gicv3_driver_data->gicd_base); 1069 gicd_set_ipriorityr(gicd_base, id, priority); 1070 } 1071 } 1072 1073 /******************************************************************************* 1074 * This function assigns group for the interrupt identified by id. The proc_num 1075 * is used if the interrupt is SGI or (E)PPI, and programs the corresponding 1076 * Redistributor interface. The group can be any of GICV3_INTR_GROUP* 1077 ******************************************************************************/ 1078 void gicv3_set_interrupt_group(unsigned int id, unsigned int proc_num, 1079 unsigned int group) 1080 { 1081 bool igroup = false, grpmod = false; 1082 uintptr_t gicr_base; 1083 uintptr_t gicd_base; 1084 1085 assert(gicv3_driver_data != NULL); 1086 assert(gicv3_driver_data->gicd_base != 0U); 1087 assert(proc_num < gicv3_driver_data->rdistif_num); 1088 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 1089 1090 switch (group) { 1091 case INTR_GROUP1S: 1092 igroup = false; 1093 grpmod = true; 1094 break; 1095 case INTR_GROUP0: 1096 igroup = false; 1097 grpmod = false; 1098 break; 1099 case INTR_GROUP1NS: 1100 igroup = true; 1101 grpmod = false; 1102 break; 1103 default: 1104 assert(false); 1105 break; 1106 } 1107 1108 if (!is_valid_interrupt(id)) { 1109 panic(); 1110 } 1111 /* Check interrupt ID */ 1112 if (IS_SGI_PPI(id)) { 1113 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 1114 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 1115 1116 igroup ? gicr_set_igroupr(gicr_base, id) : 1117 gicr_clr_igroupr(gicr_base, id); 1118 grpmod ? gicr_set_igrpmodr(gicr_base, id) : 1119 gicr_clr_igrpmodr(gicr_base, id); 1120 } else { 1121 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 1122 1123 /* Serialize read-modify-write to Distributor registers */ 1124 spin_lock(&gic_lock); 1125 1126 gicd_base = gicv3_get_multichip_base(id, gicv3_driver_data->gicd_base); 1127 1128 igroup ? gicd_set_igroupr(gicd_base, id) : 1129 gicd_clr_igroupr(gicd_base, id); 1130 grpmod ? gicd_set_igrpmodr(gicd_base, id) : 1131 gicd_clr_igrpmodr(gicd_base, id); 1132 1133 spin_unlock(&gic_lock); 1134 } 1135 } 1136 1137 /******************************************************************************* 1138 * This function raises the specified SGI of the specified group. 1139 * 1140 * The target parameter must be a valid MPIDR in the system. 1141 ******************************************************************************/ 1142 void gicv3_raise_sgi(unsigned int sgi_num, gicv3_irq_group_t group, 1143 u_register_t target) 1144 { 1145 unsigned int tgt, aff3, aff2, aff1, aff0; 1146 uint64_t sgi_val; 1147 1148 /* Verify interrupt number is in the SGI range */ 1149 assert((sgi_num >= MIN_SGI_ID) && (sgi_num < MIN_PPI_ID)); 1150 1151 /* Extract affinity fields from target */ 1152 aff0 = (unsigned int)MPIDR_AFFLVL0_VAL(target); 1153 aff1 = (unsigned int)MPIDR_AFFLVL1_VAL(target); 1154 aff2 = (unsigned int)MPIDR_AFFLVL2_VAL(target); 1155 aff3 = (unsigned int)MPIDR_AFFLVL3_VAL(target); 1156 1157 /* 1158 * Make target list from affinity 0, and ensure GICv3 SGI can target 1159 * this PE. 1160 */ 1161 assert(aff0 < GICV3_MAX_SGI_TARGETS); 1162 tgt = BIT_32(aff0); 1163 1164 /* Raise SGI to PE specified by its affinity */ 1165 sgi_val = GICV3_SGIR_VALUE(aff3, aff2, aff1, sgi_num, SGIR_IRM_TO_AFF, 1166 tgt); 1167 1168 /* 1169 * Ensure that any shared variable updates depending on out of band 1170 * interrupt trigger are observed before raising SGI. 1171 */ 1172 dsbishst(); 1173 1174 switch (group) { 1175 case GICV3_G0: 1176 write_icc_sgi0r_el1(sgi_val); 1177 break; 1178 case GICV3_G1NS: 1179 write_icc_asgi1r(sgi_val); 1180 break; 1181 case GICV3_G1S: 1182 write_icc_sgi1r(sgi_val); 1183 break; 1184 default: 1185 assert(false); 1186 break; 1187 } 1188 1189 isb(); 1190 } 1191 1192 /******************************************************************************* 1193 * This function sets the interrupt routing for the given (E)SPI interrupt id. 1194 * The interrupt routing is specified in routing mode and mpidr. 1195 * 1196 * The routing mode can be either of: 1197 * - GICV3_IRM_ANY 1198 * - GICV3_IRM_PE 1199 * 1200 * The mpidr is the affinity of the PE to which the interrupt will be routed, 1201 * and is ignored for routing mode GICV3_IRM_ANY. 1202 ******************************************************************************/ 1203 void gicv3_set_spi_routing(unsigned int id, unsigned int irm, u_register_t mpidr) 1204 { 1205 unsigned long long aff; 1206 uint64_t router; 1207 uintptr_t gicd_base; 1208 1209 assert(gicv3_driver_data != NULL); 1210 assert(gicv3_driver_data->gicd_base != 0U); 1211 1212 assert((irm == GICV3_IRM_ANY) || (irm == GICV3_IRM_PE)); 1213 1214 assert(IS_SPI(id)); 1215 1216 aff = gicd_irouter_val_from_mpidr(mpidr, irm); 1217 gicd_base = gicv3_get_multichip_base(id, gicv3_driver_data->gicd_base); 1218 gicd_write_irouter(gicd_base, id, aff); 1219 1220 /* 1221 * In implementations that do not require 1 of N distribution of SPIs, 1222 * IRM might be RAZ/WI. Read back and verify IRM bit. 1223 */ 1224 if (irm == GICV3_IRM_ANY) { 1225 router = gicd_read_irouter(gicd_base, id); 1226 if (((router >> IROUTER_IRM_SHIFT) & IROUTER_IRM_MASK) == 0U) { 1227 ERROR("GICv3 implementation doesn't support routing ANY\n"); 1228 panic(); 1229 } 1230 } 1231 } 1232 1233 /******************************************************************************* 1234 * This function clears the pending status of an interrupt identified by id. 1235 * The proc_num is used if the interrupt is SGI or (E)PPI, and programs the 1236 * corresponding Redistributor interface. 1237 ******************************************************************************/ 1238 void gicv3_clear_interrupt_pending(unsigned int id, unsigned int proc_num) 1239 { 1240 uintptr_t gicd_base; 1241 1242 assert(gicv3_driver_data != NULL); 1243 assert(gicv3_driver_data->gicd_base != 0U); 1244 assert(proc_num < gicv3_driver_data->rdistif_num); 1245 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 1246 1247 /* 1248 * Clear pending interrupt, and ensure that any shared variable updates 1249 * depending on out of band interrupt trigger are observed afterwards. 1250 */ 1251 if (!is_valid_interrupt(id)) { 1252 panic(); 1253 } 1254 /* Check interrupt ID */ 1255 if (IS_SGI_PPI(id)) { 1256 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 1257 gicr_set_icpendr( 1258 gicv3_driver_data->rdistif_base_addrs[proc_num], id); 1259 } else { 1260 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 1261 gicd_base = gicv3_get_multichip_base(id, gicv3_driver_data->gicd_base); 1262 gicd_set_icpendr(gicd_base, id); 1263 } 1264 1265 dsbishst(); 1266 } 1267 1268 /******************************************************************************* 1269 * This function sets the pending status of an interrupt identified by id. 1270 * The proc_num is used if the interrupt is SGI or PPI and programs the 1271 * corresponding Redistributor interface. 1272 ******************************************************************************/ 1273 void gicv3_set_interrupt_pending(unsigned int id, unsigned int proc_num) 1274 { 1275 uintptr_t gicd_base; 1276 1277 assert(gicv3_driver_data != NULL); 1278 assert(gicv3_driver_data->gicd_base != 0U); 1279 assert(proc_num < gicv3_driver_data->rdistif_num); 1280 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 1281 1282 /* 1283 * Ensure that any shared variable updates depending on out of band 1284 * interrupt trigger are observed before setting interrupt pending. 1285 */ 1286 dsbishst(); 1287 1288 if (!is_valid_interrupt(id)) { 1289 panic(); 1290 } 1291 1292 /* Check interrupt ID */ 1293 if (IS_SGI_PPI(id)) { 1294 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 1295 gicr_set_ispendr( 1296 gicv3_driver_data->rdistif_base_addrs[proc_num], id); 1297 } else { 1298 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 1299 gicd_base = gicv3_get_multichip_base(id, gicv3_driver_data->gicd_base); 1300 gicd_set_ispendr(gicd_base, id); 1301 } 1302 } 1303 1304 /******************************************************************************* 1305 * This function sets the PMR register with the supplied value. Returns the 1306 * original PMR. 1307 ******************************************************************************/ 1308 unsigned int gicv3_set_pmr(unsigned int mask) 1309 { 1310 unsigned int old_mask; 1311 1312 old_mask = (unsigned int)read_icc_pmr_el1(); 1313 1314 /* 1315 * Order memory updates w.r.t. PMR write, and ensure they're visible 1316 * before potential out of band interrupt trigger because of PMR update. 1317 * PMR system register writes are self-synchronizing, so no ISB required 1318 * thereafter. 1319 */ 1320 dsbishst(); 1321 write_icc_pmr_el1(mask); 1322 1323 return old_mask; 1324 } 1325 1326 /******************************************************************************* 1327 * This function restores the PMR register to old value and also triggers 1328 * gicv3_apply_errata_wa_2384374() that flushes the GIC buffer allowing any 1329 * pending interrupts to processed. Returns the original PMR. 1330 ******************************************************************************/ 1331 unsigned int gicv3_deactivate_priority(unsigned int mask) 1332 { 1333 1334 unsigned int old_mask, proc_num; 1335 uintptr_t gicr_base; 1336 1337 old_mask = gicv3_set_pmr(mask); 1338 1339 proc_num = plat_my_core_pos(); 1340 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 1341 assert(gicr_base != 0UL); 1342 1343 /* Add DSB to ensure visibility of System register writes */ 1344 dsb(); 1345 1346 gicv3_apply_errata_wa_2384374(gicr_base); 1347 1348 return old_mask; 1349 } 1350 1351 /******************************************************************************* 1352 * This function delegates the responsibility of discovering the corresponding 1353 * Redistributor frames to each CPU itself. It is a modified version of 1354 * gicv3_rdistif_base_addrs_probe() and is executed by each CPU in the platform 1355 * unlike the previous way in which only the Primary CPU did the discovery of 1356 * all the Redistributor frames for every CPU. It also handles the scenario in 1357 * which the frames of various CPUs are not contiguous in physical memory. 1358 ******************************************************************************/ 1359 int gicv3_rdistif_probe(const uintptr_t gicr_frame) 1360 { 1361 u_register_t mpidr, mpidr_self; 1362 unsigned int proc_num; 1363 uint64_t typer_val; 1364 uintptr_t rdistif_base; 1365 bool gicr_frame_found = false; 1366 1367 assert(gicv3_driver_data->gicr_base == 0U); 1368 1369 if (plat_can_cmo()) { 1370 /* Ensure this function is called with Data Cache enabled */ 1371 #ifndef __aarch64__ 1372 assert((read_sctlr() & SCTLR_C_BIT) != 0U); 1373 #else 1374 assert((read_sctlr_el3() & SCTLR_C_BIT) != 0U); 1375 #endif /* !__aarch64__ */ 1376 } 1377 1378 mpidr_self = read_mpidr_el1() & MPIDR_AFFINITY_MASK; 1379 rdistif_base = gicr_frame; 1380 do { 1381 typer_val = gicr_read_typer(rdistif_base); 1382 mpidr = mpidr_from_gicr_typer(typer_val); 1383 if (gicv3_driver_data->mpidr_to_core_pos != NULL) { 1384 proc_num = gicv3_driver_data->mpidr_to_core_pos(mpidr); 1385 } else { 1386 proc_num = (unsigned int)(typer_val >> 1387 TYPER_PROC_NUM_SHIFT) & TYPER_PROC_NUM_MASK; 1388 } 1389 if (mpidr == mpidr_self) { 1390 /* The base address doesn't need to be initialized on 1391 * every warm boot. 1392 */ 1393 if (gicv3_driver_data->rdistif_base_addrs[proc_num] 1394 != 0U) { 1395 return 0; 1396 } 1397 gicv3_driver_data->rdistif_base_addrs[proc_num] = 1398 rdistif_base; 1399 gicr_frame_found = true; 1400 break; 1401 } 1402 rdistif_base += gicv3_redist_size(typer_val); 1403 } while ((typer_val & TYPER_LAST_BIT) == 0U); 1404 1405 if (!gicr_frame_found) { 1406 return -1; 1407 } 1408 1409 /* 1410 * Flush the driver data to ensure coherency. This is 1411 * not required if platform has HW_ASSISTED_COHERENCY 1412 * enabled. 1413 */ 1414 #if !HW_ASSISTED_COHERENCY 1415 /* 1416 * Flush the rdistif_base_addrs[] contents linked to the GICv3 driver. 1417 */ 1418 flush_dcache_range((uintptr_t)&(gicv3_driver_data->rdistif_base_addrs[proc_num]), 1419 sizeof(*(gicv3_driver_data->rdistif_base_addrs))); 1420 #endif 1421 return 0; /* Found matching GICR frame */ 1422 } 1423 1424 /****************************************************************************** 1425 * This function checks the interrupt ID and returns true for SGIs, (E)PPIs 1426 * and (E)SPIs IDs. Any interrupt ID outside the range is invalid and returns 1427 * false. 1428 *****************************************************************************/ 1429 static bool is_valid_interrupt(unsigned int id) 1430 { 1431 /* Valid interrupts: 1432 * SGIs: 0-15, PPIs: 16-31, EPPIs: 1056-1119 1433 * SPIs: 32-1019, ESPIs: 4096-5119 1434 */ 1435 if ((IS_SGI_PPI(id)) || (IS_SPI(id))) { 1436 return true; 1437 } 1438 1439 return false; 1440 } 1441