rockchip: close the PD center logic during suspend

The RK3399 supports close the center logic enter power mode,
so we can close PD_CENTER to save more power during suspend.
Therefore, we need to sup

rockchip: close the PD center logic during suspend

The RK3399 supports close the center logic enter power mode,
so we can close PD_CENTER to save more power during suspend.
Therefore, we need to support save/restore the DDR PHY and
controller registers during suspend/resume.

Also, need CL (http://crosreview.com/397399) to check disabling
center logic.

Change-Id: I288defd8e9caa3846d9fa663a33e4d51df1aaa5d
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

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rockchip: add support save/restore configuration for DDR during enter S3

This patch intend to support save the registers of the DDR controller
and PHY before suspend, and restore them after resume.

rockchip: add support save/restore configuration for DDR during enter S3

This patch intend to support save the registers of the DDR controller
and PHY before suspend, and restore them after resume.

Change-Id: Ia10b476c0b837628ac0f365416a7118292753e96
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

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rockchip: Change dmc register accesses to ATF style for rk3399

This changes the style of dmc register accesses to be a read/write on
a base address plus a register offset instead of reinterpretting

rockchip: Change dmc register accesses to ATF style for rk3399

This changes the style of dmc register accesses to be a read/write on
a base address plus a register offset instead of reinterpretting a
base address as a struct and accessing members within that struct.

Change-Id: Iead097cd6afdb830d8bc193608cd39d01ce5a6bc
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

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rockchip: Break out common dram code for rk3399

This renames dram.c and dram.h to dfs.c and dfs.h respectively. This
is to make room for common functionality between frequency scaling and
suspend co

rockchip: Break out common dram code for rk3399

This renames dram.c and dram.h to dfs.c and dfs.h respectively. This
is to make room for common functionality between frequency scaling and
suspend code for the DRAM in a pair of common files named dram.c and
dram.h. It also removes a duplicate enum definition from
dram_spec_timing.h

Change-Id: Ibfa1041f8781401f9d27901fe8c61862bcb05562
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

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rockchip: move pmu registers into another header for rk3399

This moves the PMU register definitions into another file for use in
later patches.

Change-Id: I8b5f1e7938b63ada6a743cf9661c3e474e96e4e4

rockchip: move pmu registers into another header for rk3399

This moves the PMU register definitions into another file for use in
later patches.

Change-Id: I8b5f1e7938b63ada6a743cf9661c3e474e96e4e4
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

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fiptool: fix Segmentation fault when only --verbose option is given

Fix the following bug:

$ tools/fiptool/fiptool -v
Segmentation fault (core dumped)

Signed-off-by: Masahiro Yamada <yamada.ma

fiptool: fix Segmentation fault when only --verbose option is given

Fix the following bug:

$ tools/fiptool/fiptool -v
Segmentation fault (core dumped)

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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Merge pull request #724 from rockchip-linux/support-rk3399-sdram

rockchip: optimize the link mechanism for SRAM code

Merge pull request #739 from rockchip-linux/fixes-latency

rockchip: fix A72 L2CTLR_DATA_RAM_LATENCY to 5

rockchip: fix A72 L2CTLR_DATA_RAM_LATENCY to 5

The default value of L2CTLR_DATA_RAM_LATENCY is 2, depends to
the test result on rk3399, the A72 will need lower voltage for
high frequency if it's set

rockchip: fix A72 L2CTLR_DATA_RAM_LATENCY to 5

The default value of L2CTLR_DATA_RAM_LATENCY is 2, depends to
the test result on rk3399, the A72 will need lower voltage for
high frequency if it's set to be 5, and almost no effect on performance.

Change-Id: I99a6a43edcc0c58f7775c10f4b85669dc3eff66d
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

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rockchip: clear the power mode status via M0

Due to the PMU design, the PMU may not clear the WAKEUP bit after
wakeup, therefore, the state machine at the power mode may enter
the infinite loop duri

rockchip: clear the power mode status via M0

Due to the PMU design, the PMU may not clear the WAKEUP bit after
wakeup, therefore, the state machine at the power mode may enter
the infinite loop during WFI.

There is a solution that we can use the M0 to monitor the WAKEUP
bit and clear it during power mode, then the state machine will be
recovered immediately. Then, the DUT can exit the WFI normally.

Change-Id: I303628553b728c214bf2d436bd3122032b5e669c
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

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rockchip: add M0 source code and build system for RK3399

This CL supports add M0 source code to built into the bl31.bin, the
goal is that we can load the M0 code binary into SRAM and execute it.

We

rockchip: add M0 source code and build system for RK3399

This CL supports add M0 source code to built into the bl31.bin, the
goal is that we can load the M0 code binary into SRAM and execute it.

We need the M0 help us to clean the power_mode_en bit during the AP
PMU enter the state machine with interrupt, and avoid to the AP can
not exit the loop forever.

Change-Id: I844582c54a1f0d44ca41290d44618df58679f341
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

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rockchip: optimize the link mechanism for SRAM code

Add the common extra.ld.S and customized rk3399.ld.S to extend
to more features for different platforms.
For example, we can add SRAM section and

rockchip: optimize the link mechanism for SRAM code

Add the common extra.ld.S and customized rk3399.ld.S to extend
to more features for different platforms.
For example, we can add SRAM section and specific address to
load there if we need it, and the common bl31.ld.S not need to
be modified.

Therefore, we can remove the unused codes which copying explicitly
from the function pmusram_prepare(). It looks like more clear.

Change-Id: Ibffa2da5e8e3d1d2fca80085ebb296ceb967fce8
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

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.gitignore: ignore editor backup files

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

Fix comment of plat_reset_handler stub

As described in the Porting Guide, plat_reset_handler should
preserve x19 to x29.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

Docs: fix a typo in Porting Guide about plat_get_my_entrypoint()

Do not double the phrase "called with the".

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

Mandate 'Signed-off-by' line in commit messages

This patch updates the configuration file for the checkpatch.pl
script to check for the presence of a 'Signed-off-by' line in the
commit message. This

Mandate 'Signed-off-by' line in commit messages

This patch updates the configuration file for the checkpatch.pl
script to check for the presence of a 'Signed-off-by' line in the
commit message. This is now required by TF contribution process.

Change-Id: I8bcd6d39a5dcd85547244d60c10a7cd2148c404f

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

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Merge pull request #740 from rockchip-linux/rk3399/fixes-cru-typo

rockchip: fixes the wrong CLKSEL_CON count for CRU

rockchip: fixes the wrong CLKSEL_CON count for CRU

The CRU_CLKSEL_COUNT value is 108, not 0x108.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Change-Id: Ib9db066b8b3ecafcee7f645dd5633b55a808e3d7

Merge pull request #677 from hzhuang1/gpt

partition: check GPT partition table

fiptool: Link `toc_entry` and `image` structures via UUID

The `toc_entry` and `image` data structures had a cyclic
relationship. This patch removes the explicit dependencies and introduces
function

fiptool: Link `toc_entry` and `image` structures via UUID

The `toc_entry` and `image` data structures had a cyclic
relationship. This patch removes the explicit dependencies and introduces
functions to link them via the UUID.

This change highlights the intent of the code better and makes it more
flexible for future enhancements.

Change-Id: I0c3dd7bfda2a631a3827c8ba4831849c500affe9
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>

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Merge pull request #735 from soby-mathew/sm/aarch32_sctlr

Unify SCTLR initialization for AArch32 normal world

Merge pull request #734 from afaerber/make-help

Makefile: Add missing space in help output

Merge pull request #730 from dp-arm/dp/uuid-cleanup

Remove non-standard <sys/cdefs.h> include from uuid.h

Merge pull request #729 from dp-arm/dp/arm-sip

Add instrumentation support for PSCI

Merge pull request #721 from rockchip-linux/fixes-the-clock-select-and-divide-register

rockchip: fixes the clock select and divide register for rk3399