1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <debug.h> 33 #include <mmio.h> 34 #include <m0_ctl.h> 35 #include <plat_private.h> 36 #include "dfs.h" 37 #include "dram.h" 38 #include "dram_spec_timing.h" 39 #include "string.h" 40 #include "soc.h" 41 #include "pmu.h" 42 43 #include <delay_timer.h> 44 45 #define ENPER_CS_TRAINING_FREQ (933) 46 #define PHY_DLL_BYPASS_FREQ (260) 47 48 static const struct pll_div dpll_rates_table[] = { 49 50 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2 */ 51 {.mhz = 928, .refdiv = 1, .fbdiv = 116, .postdiv1 = 3, .postdiv2 = 1}, 52 {.mhz = 800, .refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1}, 53 {.mhz = 732, .refdiv = 1, .fbdiv = 61, .postdiv1 = 2, .postdiv2 = 1}, 54 {.mhz = 666, .refdiv = 1, .fbdiv = 111, .postdiv1 = 4, .postdiv2 = 1}, 55 {.mhz = 600, .refdiv = 1, .fbdiv = 50, .postdiv1 = 2, .postdiv2 = 1}, 56 {.mhz = 528, .refdiv = 1, .fbdiv = 66, .postdiv1 = 3, .postdiv2 = 1}, 57 {.mhz = 400, .refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1}, 58 {.mhz = 300, .refdiv = 1, .fbdiv = 50, .postdiv1 = 4, .postdiv2 = 1}, 59 {.mhz = 200, .refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 2}, 60 }; 61 62 struct rk3399_dram_status { 63 uint32_t current_index; 64 uint32_t index_freq[2]; 65 uint32_t boot_freq; 66 uint32_t low_power_stat; 67 struct timing_related_config timing_config; 68 struct drv_odt_lp_config drv_odt_lp_cfg; 69 }; 70 71 struct rk3399_saved_status { 72 uint32_t freq; 73 uint32_t low_power_stat; 74 uint32_t odt; 75 }; 76 77 static struct rk3399_dram_status rk3399_dram_status; 78 static struct rk3399_saved_status rk3399_suspend_status; 79 static uint32_t wrdqs_delay_val[2][2][4]; 80 81 static struct rk3399_sdram_default_config ddr3_default_config = { 82 .bl = 8, 83 .ap = 0, 84 .burst_ref_cnt = 1, 85 .zqcsi = 0 86 }; 87 88 static struct rk3399_sdram_default_config lpddr3_default_config = { 89 .bl = 8, 90 .ap = 0, 91 .burst_ref_cnt = 1, 92 .zqcsi = 0 93 }; 94 95 static struct rk3399_sdram_default_config lpddr4_default_config = { 96 .bl = 16, 97 .ap = 0, 98 .caodt = 240, 99 .burst_ref_cnt = 1, 100 .zqcsi = 0 101 }; 102 103 static uint32_t get_cs_die_capability(struct rk3399_sdram_params *sdram_config, 104 uint8_t channel, uint8_t cs) 105 { 106 struct rk3399_sdram_channel *ch = &sdram_config->ch[channel]; 107 uint32_t bandwidth; 108 uint32_t die_bandwidth; 109 uint32_t die; 110 uint32_t cs_cap; 111 uint32_t row; 112 113 row = cs == 0 ? ch->cs0_row : ch->cs1_row; 114 bandwidth = 8 * (1 << ch->bw); 115 die_bandwidth = 8 * (1 << ch->dbw); 116 die = bandwidth / die_bandwidth; 117 cs_cap = (1 << (row + ((1 << ch->bk) / 4 + 1) + ch->col + 118 (bandwidth / 16))); 119 if (ch->row_3_4) 120 cs_cap = cs_cap * 3 / 4; 121 122 return (cs_cap / die); 123 } 124 125 static void get_dram_drv_odt_val(uint32_t dram_type, 126 struct drv_odt_lp_config *drv_config) 127 { 128 uint32_t tmp; 129 uint32_t mr1_val, mr3_val, mr11_val; 130 131 switch (dram_type) { 132 case DDR3: 133 mr1_val = (mmio_read_32(CTL_REG(0, 133)) >> 16) & 0xffff; 134 tmp = ((mr1_val >> 1) & 1) | ((mr1_val >> 4) & 1); 135 if (tmp) 136 drv_config->dram_side_drv = 34; 137 else 138 drv_config->dram_side_drv = 40; 139 tmp = ((mr1_val >> 2) & 1) | ((mr1_val >> 5) & 1) | 140 ((mr1_val >> 7) & 1); 141 if (tmp == 0) 142 drv_config->dram_side_dq_odt = 0; 143 else if (tmp == 1) 144 drv_config->dram_side_dq_odt = 60; 145 else if (tmp == 3) 146 drv_config->dram_side_dq_odt = 40; 147 else 148 drv_config->dram_side_dq_odt = 120; 149 break; 150 case LPDDR3: 151 mr3_val = mmio_read_32(CTL_REG(0, 138)) & 0xf; 152 mr11_val = (mmio_read_32(CTL_REG(0, 139)) >> 24) & 0x3; 153 if (mr3_val == 0xb) 154 drv_config->dram_side_drv = 3448; 155 else if (mr3_val == 0xa) 156 drv_config->dram_side_drv = 4048; 157 else if (mr3_val == 0x9) 158 drv_config->dram_side_drv = 3440; 159 else if (mr3_val == 0x4) 160 drv_config->dram_side_drv = 60; 161 else if (mr3_val == 0x3) 162 drv_config->dram_side_drv = 48; 163 else if (mr3_val == 0x2) 164 drv_config->dram_side_drv = 40; 165 else 166 drv_config->dram_side_drv = 34; 167 168 if (mr11_val == 1) 169 drv_config->dram_side_dq_odt = 60; 170 else if (mr11_val == 2) 171 drv_config->dram_side_dq_odt = 120; 172 else if (mr11_val == 0) 173 drv_config->dram_side_dq_odt = 0; 174 else 175 drv_config->dram_side_dq_odt = 240; 176 break; 177 case LPDDR4: 178 default: 179 mr3_val = (mmio_read_32(CTL_REG(0, 138)) >> 3) & 0x7; 180 mr11_val = (mmio_read_32(CTL_REG(0, 139)) >> 24) & 0xff; 181 182 if ((mr3_val == 0) || (mr3_val == 7)) 183 drv_config->dram_side_drv = 40; 184 else 185 drv_config->dram_side_drv = 240 / mr3_val; 186 187 tmp = mr11_val & 0x7; 188 if ((tmp == 7) || (tmp == 0)) 189 drv_config->dram_side_dq_odt = 0; 190 else 191 drv_config->dram_side_dq_odt = 240 / tmp; 192 193 tmp = (mr11_val >> 4) & 0x7; 194 if ((tmp == 7) || (tmp == 0)) 195 drv_config->dram_side_ca_odt = 0; 196 else 197 drv_config->dram_side_ca_odt = 240 / tmp; 198 break; 199 } 200 } 201 202 static void sdram_timing_cfg_init(struct timing_related_config *ptiming_config, 203 struct rk3399_sdram_params *sdram_params, 204 struct drv_odt_lp_config *drv_config) 205 { 206 uint32_t i, j; 207 208 for (i = 0; i < sdram_params->num_channels; i++) { 209 ptiming_config->dram_info[i].speed_rate = DDR3_DEFAULT; 210 ptiming_config->dram_info[i].cs_cnt = sdram_params->ch[i].rank; 211 for (j = 0; j < sdram_params->ch[i].rank; j++) { 212 ptiming_config->dram_info[i].per_die_capability[j] = 213 get_cs_die_capability(sdram_params, i, j); 214 } 215 } 216 ptiming_config->dram_type = sdram_params->dramtype; 217 ptiming_config->ch_cnt = sdram_params->num_channels; 218 switch (sdram_params->dramtype) { 219 case DDR3: 220 ptiming_config->bl = ddr3_default_config.bl; 221 ptiming_config->ap = ddr3_default_config.ap; 222 break; 223 case LPDDR3: 224 ptiming_config->bl = lpddr3_default_config.bl; 225 ptiming_config->ap = lpddr3_default_config.ap; 226 break; 227 case LPDDR4: 228 ptiming_config->bl = lpddr4_default_config.bl; 229 ptiming_config->ap = lpddr4_default_config.ap; 230 ptiming_config->rdbi = 0; 231 ptiming_config->wdbi = 0; 232 break; 233 } 234 ptiming_config->dramds = drv_config->dram_side_drv; 235 ptiming_config->dramodt = drv_config->dram_side_dq_odt; 236 ptiming_config->caodt = drv_config->dram_side_ca_odt; 237 ptiming_config->odt = (mmio_read_32(PHY_REG(0, 5)) >> 16) & 0x1; 238 } 239 240 struct lat_adj_pair { 241 uint32_t cl; 242 uint32_t rdlat_adj; 243 uint32_t cwl; 244 uint32_t wrlat_adj; 245 }; 246 247 const struct lat_adj_pair ddr3_lat_adj[] = { 248 {6, 5, 5, 4}, 249 {8, 7, 6, 5}, 250 {10, 9, 7, 6}, 251 {11, 9, 8, 7}, 252 {13, 0xb, 9, 8}, 253 {14, 0xb, 0xa, 9} 254 }; 255 256 const struct lat_adj_pair lpddr3_lat_adj[] = { 257 {3, 2, 1, 0}, 258 {6, 5, 3, 2}, 259 {8, 7, 4, 3}, 260 {9, 8, 5, 4}, 261 {10, 9, 6, 5}, 262 {11, 9, 6, 5}, 263 {12, 0xa, 6, 5}, 264 {14, 0xc, 8, 7}, 265 {16, 0xd, 8, 7} 266 }; 267 268 const struct lat_adj_pair lpddr4_lat_adj[] = { 269 {6, 5, 4, 2}, 270 {10, 9, 6, 4}, 271 {14, 0xc, 8, 6}, 272 {20, 0x11, 0xa, 8}, 273 {24, 0x15, 0xc, 0xa}, 274 {28, 0x18, 0xe, 0xc}, 275 {32, 0x1b, 0x10, 0xe}, 276 {36, 0x1e, 0x12, 0x10} 277 }; 278 279 static uint32_t get_rdlat_adj(uint32_t dram_type, uint32_t cl) 280 { 281 const struct lat_adj_pair *p; 282 uint32_t cnt; 283 uint32_t i; 284 285 if (dram_type == DDR3) { 286 p = ddr3_lat_adj; 287 cnt = ARRAY_SIZE(ddr3_lat_adj); 288 } else if (dram_type == LPDDR3) { 289 p = lpddr3_lat_adj; 290 cnt = ARRAY_SIZE(lpddr3_lat_adj); 291 } else { 292 p = lpddr4_lat_adj; 293 cnt = ARRAY_SIZE(lpddr4_lat_adj); 294 } 295 296 for (i = 0; i < cnt; i++) { 297 if (cl == p[i].cl) 298 return p[i].rdlat_adj; 299 } 300 /* fail */ 301 return 0xff; 302 } 303 304 static uint32_t get_wrlat_adj(uint32_t dram_type, uint32_t cwl) 305 { 306 const struct lat_adj_pair *p; 307 uint32_t cnt; 308 uint32_t i; 309 310 if (dram_type == DDR3) { 311 p = ddr3_lat_adj; 312 cnt = ARRAY_SIZE(ddr3_lat_adj); 313 } else if (dram_type == LPDDR3) { 314 p = lpddr3_lat_adj; 315 cnt = ARRAY_SIZE(lpddr3_lat_adj); 316 } else { 317 p = lpddr4_lat_adj; 318 cnt = ARRAY_SIZE(lpddr4_lat_adj); 319 } 320 321 for (i = 0; i < cnt; i++) { 322 if (cwl == p[i].cwl) 323 return p[i].wrlat_adj; 324 } 325 /* fail */ 326 return 0xff; 327 } 328 329 #define PI_REGS_DIMM_SUPPORT (0) 330 #define PI_ADD_LATENCY (0) 331 #define PI_DOUBLEFREEK (1) 332 333 #define PI_PAD_DELAY_PS_VALUE (1000) 334 #define PI_IE_ENABLE_VALUE (3000) 335 #define PI_TSEL_ENABLE_VALUE (700) 336 337 static uint32_t get_pi_rdlat_adj(struct dram_timing_t *pdram_timing) 338 { 339 /*[DLLSUBTYPE2] == "STD_DENALI_HS" */ 340 uint32_t rdlat, delay_adder, ie_enable, hs_offset, tsel_adder, 341 extra_adder, tsel_enable; 342 343 ie_enable = PI_IE_ENABLE_VALUE; 344 tsel_enable = PI_TSEL_ENABLE_VALUE; 345 346 rdlat = pdram_timing->cl + PI_ADD_LATENCY; 347 delay_adder = ie_enable / (1000000 / pdram_timing->mhz); 348 if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0) 349 delay_adder++; 350 hs_offset = 0; 351 tsel_adder = 0; 352 extra_adder = 0; 353 /* rdlat = rdlat - (PREAMBLE_SUPPORT & 0x1); */ 354 tsel_adder = tsel_enable / (1000000 / pdram_timing->mhz); 355 if ((tsel_enable % (1000000 / pdram_timing->mhz)) != 0) 356 tsel_adder++; 357 delay_adder = delay_adder - 1; 358 if (tsel_adder > delay_adder) 359 extra_adder = tsel_adder - delay_adder; 360 else 361 extra_adder = 0; 362 if (PI_REGS_DIMM_SUPPORT && PI_DOUBLEFREEK) 363 hs_offset = 2; 364 else 365 hs_offset = 1; 366 367 if (delay_adder > (rdlat - 1 - hs_offset)) { 368 rdlat = rdlat - tsel_adder; 369 } else { 370 if ((rdlat - delay_adder) < 2) 371 rdlat = 2; 372 else 373 rdlat = rdlat - delay_adder - extra_adder; 374 } 375 376 return rdlat; 377 } 378 379 static uint32_t get_pi_wrlat(struct dram_timing_t *pdram_timing, 380 struct timing_related_config *timing_config) 381 { 382 uint32_t tmp; 383 384 if (timing_config->dram_type == LPDDR3) { 385 tmp = pdram_timing->cl; 386 if (tmp >= 14) 387 tmp = 8; 388 else if (tmp >= 10) 389 tmp = 6; 390 else if (tmp == 9) 391 tmp = 5; 392 else if (tmp == 8) 393 tmp = 4; 394 else if (tmp == 6) 395 tmp = 3; 396 else 397 tmp = 1; 398 } else { 399 tmp = 1; 400 } 401 402 return tmp; 403 } 404 405 static uint32_t get_pi_wrlat_adj(struct dram_timing_t *pdram_timing, 406 struct timing_related_config *timing_config) 407 { 408 return get_pi_wrlat(pdram_timing, timing_config) + PI_ADD_LATENCY - 1; 409 } 410 411 static uint32_t get_pi_tdfi_phy_rdlat(struct dram_timing_t *pdram_timing, 412 struct timing_related_config *timing_config) 413 { 414 /* [DLLSUBTYPE2] == "STD_DENALI_HS" */ 415 uint32_t cas_lat, delay_adder, ie_enable, hs_offset, ie_delay_adder; 416 uint32_t mem_delay_ps, round_trip_ps; 417 uint32_t phy_internal_delay, lpddr_adder, dfi_adder, rdlat_delay; 418 419 ie_enable = PI_IE_ENABLE_VALUE; 420 421 delay_adder = ie_enable / (1000000 / pdram_timing->mhz); 422 if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0) 423 delay_adder++; 424 delay_adder = delay_adder - 1; 425 if (PI_REGS_DIMM_SUPPORT && PI_DOUBLEFREEK) 426 hs_offset = 2; 427 else 428 hs_offset = 1; 429 430 cas_lat = pdram_timing->cl + PI_ADD_LATENCY; 431 432 if (delay_adder > (cas_lat - 1 - hs_offset)) { 433 ie_delay_adder = 0; 434 } else { 435 ie_delay_adder = ie_enable / (1000000 / pdram_timing->mhz); 436 if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0) 437 ie_delay_adder++; 438 } 439 440 if (timing_config->dram_type == DDR3) { 441 mem_delay_ps = 0; 442 } else if (timing_config->dram_type == LPDDR4) { 443 mem_delay_ps = 3600; 444 } else if (timing_config->dram_type == LPDDR3) { 445 mem_delay_ps = 5500; 446 } else { 447 printf("get_pi_tdfi_phy_rdlat:dramtype unsupport\n"); 448 return 0; 449 } 450 round_trip_ps = 1100 + 500 + mem_delay_ps + 500 + 600; 451 delay_adder = round_trip_ps / (1000000 / pdram_timing->mhz); 452 if ((round_trip_ps % (1000000 / pdram_timing->mhz)) != 0) 453 delay_adder++; 454 455 phy_internal_delay = 5 + 2 + 4; 456 lpddr_adder = mem_delay_ps / (1000000 / pdram_timing->mhz); 457 if ((mem_delay_ps % (1000000 / pdram_timing->mhz)) != 0) 458 lpddr_adder++; 459 dfi_adder = 0; 460 phy_internal_delay = phy_internal_delay + 2; 461 rdlat_delay = delay_adder + phy_internal_delay + 462 ie_delay_adder + lpddr_adder + dfi_adder; 463 464 rdlat_delay = rdlat_delay + 2; 465 return rdlat_delay; 466 } 467 468 static uint32_t get_pi_todtoff_min(struct dram_timing_t *pdram_timing, 469 struct timing_related_config *timing_config) 470 { 471 uint32_t tmp, todtoff_min_ps; 472 473 if (timing_config->dram_type == LPDDR3) 474 todtoff_min_ps = 2500; 475 else if (timing_config->dram_type == LPDDR4) 476 todtoff_min_ps = 1500; 477 else 478 todtoff_min_ps = 0; 479 /* todtoff_min */ 480 tmp = todtoff_min_ps / (1000000 / pdram_timing->mhz); 481 if ((todtoff_min_ps % (1000000 / pdram_timing->mhz)) != 0) 482 tmp++; 483 return tmp; 484 } 485 486 static uint32_t get_pi_todtoff_max(struct dram_timing_t *pdram_timing, 487 struct timing_related_config *timing_config) 488 { 489 uint32_t tmp, todtoff_max_ps; 490 491 if ((timing_config->dram_type == LPDDR4) 492 || (timing_config->dram_type == LPDDR3)) 493 todtoff_max_ps = 3500; 494 else 495 todtoff_max_ps = 0; 496 497 /* todtoff_max */ 498 tmp = todtoff_max_ps / (1000000 / pdram_timing->mhz); 499 if ((todtoff_max_ps % (1000000 / pdram_timing->mhz)) != 0) 500 tmp++; 501 return tmp; 502 } 503 504 static void gen_rk3399_ctl_params_f0(struct timing_related_config 505 *timing_config, 506 struct dram_timing_t *pdram_timing) 507 { 508 uint32_t i; 509 uint32_t tmp, tmp1; 510 511 for (i = 0; i < timing_config->ch_cnt; i++) { 512 if (timing_config->dram_type == DDR3) { 513 tmp = ((700000 + 10) * timing_config->freq + 514 999) / 1000; 515 tmp += pdram_timing->txsnr + (pdram_timing->tmrd * 3) + 516 pdram_timing->tmod + pdram_timing->tzqinit; 517 mmio_write_32(CTL_REG(i, 5), tmp); 518 519 mmio_clrsetbits_32(CTL_REG(i, 22), 0xffff, 520 pdram_timing->tdllk); 521 522 mmio_write_32(CTL_REG(i, 32), 523 (pdram_timing->tmod << 8) | 524 pdram_timing->tmrd); 525 526 mmio_clrsetbits_32(CTL_REG(i, 59), 0xffff << 16, 527 (pdram_timing->txsr - 528 pdram_timing->trcd) << 16); 529 } else if (timing_config->dram_type == LPDDR4) { 530 mmio_write_32(CTL_REG(i, 5), pdram_timing->tinit1 + 531 pdram_timing->tinit3); 532 mmio_write_32(CTL_REG(i, 32), 533 (pdram_timing->tmrd << 8) | 534 pdram_timing->tmrd); 535 mmio_clrsetbits_32(CTL_REG(i, 59), 0xffff << 16, 536 pdram_timing->txsr << 16); 537 } else { 538 mmio_write_32(CTL_REG(i, 5), pdram_timing->tinit1); 539 mmio_write_32(CTL_REG(i, 7), pdram_timing->tinit4); 540 mmio_write_32(CTL_REG(i, 32), 541 (pdram_timing->tmrd << 8) | 542 pdram_timing->tmrd); 543 mmio_clrsetbits_32(CTL_REG(i, 59), 0xffff << 16, 544 pdram_timing->txsr << 16); 545 } 546 mmio_write_32(CTL_REG(i, 6), pdram_timing->tinit3); 547 mmio_write_32(CTL_REG(i, 8), pdram_timing->tinit5); 548 mmio_clrsetbits_32(CTL_REG(i, 23), (0x7f << 16), 549 ((pdram_timing->cl * 2) << 16)); 550 mmio_clrsetbits_32(CTL_REG(i, 23), (0x1f << 24), 551 (pdram_timing->cwl << 24)); 552 mmio_clrsetbits_32(CTL_REG(i, 24), 0x3f, pdram_timing->al); 553 mmio_clrsetbits_32(CTL_REG(i, 26), 0xffff << 16, 554 (pdram_timing->trc << 24) | 555 (pdram_timing->trrd << 16)); 556 mmio_write_32(CTL_REG(i, 27), 557 (pdram_timing->tfaw << 24) | 558 (pdram_timing->trppb << 16) | 559 (pdram_timing->twtr << 8) | 560 pdram_timing->tras_min); 561 562 mmio_clrsetbits_32(CTL_REG(i, 31), 0xff << 24, 563 max(4, pdram_timing->trtp) << 24); 564 mmio_write_32(CTL_REG(i, 33), (pdram_timing->tcke << 24) | 565 pdram_timing->tras_max); 566 mmio_clrsetbits_32(CTL_REG(i, 34), 0xff, 567 max(1, pdram_timing->tckesr)); 568 mmio_clrsetbits_32(CTL_REG(i, 39), 569 (0x3f << 16) | (0xff << 8), 570 (pdram_timing->twr << 16) | 571 (pdram_timing->trcd << 8)); 572 mmio_clrsetbits_32(CTL_REG(i, 42), 0x1f << 16, 573 pdram_timing->tmrz << 16); 574 tmp = pdram_timing->tdal ? pdram_timing->tdal : 575 (pdram_timing->twr + pdram_timing->trp); 576 mmio_clrsetbits_32(CTL_REG(i, 44), 0xff, tmp); 577 mmio_clrsetbits_32(CTL_REG(i, 45), 0xff, pdram_timing->trp); 578 mmio_write_32(CTL_REG(i, 48), 579 ((pdram_timing->trefi - 8) << 16) | 580 pdram_timing->trfc); 581 mmio_clrsetbits_32(CTL_REG(i, 52), 0xffff, pdram_timing->txp); 582 mmio_clrsetbits_32(CTL_REG(i, 53), 0xffff << 16, 583 pdram_timing->txpdll << 16); 584 mmio_clrsetbits_32(CTL_REG(i, 55), 0xf << 24, 585 pdram_timing->tcscke << 24); 586 mmio_clrsetbits_32(CTL_REG(i, 55), 0xff, pdram_timing->tmrri); 587 mmio_write_32(CTL_REG(i, 56), 588 (pdram_timing->tzqcke << 24) | 589 (pdram_timing->tmrwckel << 16) | 590 (pdram_timing->tckehcs << 8) | 591 pdram_timing->tckelcs); 592 mmio_clrsetbits_32(CTL_REG(i, 60), 0xffff, pdram_timing->txsnr); 593 mmio_clrsetbits_32(CTL_REG(i, 62), 0xffff << 16, 594 (pdram_timing->tckehcmd << 24) | 595 (pdram_timing->tckelcmd << 16)); 596 mmio_write_32(CTL_REG(i, 63), 597 (pdram_timing->tckelpd << 24) | 598 (pdram_timing->tescke << 16) | 599 (pdram_timing->tsr << 8) | 600 pdram_timing->tckckel); 601 mmio_clrsetbits_32(CTL_REG(i, 64), 0xfff, 602 (pdram_timing->tcmdcke << 8) | 603 pdram_timing->tcsckeh); 604 mmio_clrsetbits_32(CTL_REG(i, 92), 0xffff << 8, 605 (pdram_timing->tcksrx << 16) | 606 (pdram_timing->tcksre << 8)); 607 mmio_clrsetbits_32(CTL_REG(i, 108), 0x1 << 24, 608 (timing_config->dllbp << 24)); 609 mmio_clrsetbits_32(CTL_REG(i, 122), 0x3ff << 16, 610 (pdram_timing->tvrcg_enable << 16)); 611 mmio_write_32(CTL_REG(i, 123), (pdram_timing->tfc_long << 16) | 612 pdram_timing->tvrcg_disable); 613 mmio_write_32(CTL_REG(i, 124), 614 (pdram_timing->tvref_long << 16) | 615 (pdram_timing->tckfspx << 8) | 616 pdram_timing->tckfspe); 617 mmio_write_32(CTL_REG(i, 133), (pdram_timing->mr[1] << 16) | 618 pdram_timing->mr[0]); 619 mmio_clrsetbits_32(CTL_REG(i, 134), 0xffff, 620 pdram_timing->mr[2]); 621 mmio_clrsetbits_32(CTL_REG(i, 138), 0xffff, 622 pdram_timing->mr[3]); 623 mmio_clrsetbits_32(CTL_REG(i, 139), 0xff << 24, 624 pdram_timing->mr11 << 24); 625 mmio_write_32(CTL_REG(i, 147), 626 (pdram_timing->mr[1] << 16) | 627 pdram_timing->mr[0]); 628 mmio_clrsetbits_32(CTL_REG(i, 148), 0xffff, 629 pdram_timing->mr[2]); 630 mmio_clrsetbits_32(CTL_REG(i, 152), 0xffff, 631 pdram_timing->mr[3]); 632 mmio_clrsetbits_32(CTL_REG(i, 153), 0xff << 24, 633 pdram_timing->mr11 << 24); 634 if (timing_config->dram_type == LPDDR4) { 635 mmio_clrsetbits_32(CTL_REG(i, 140), 0xffff << 16, 636 pdram_timing->mr12 << 16); 637 mmio_clrsetbits_32(CTL_REG(i, 142), 0xffff << 16, 638 pdram_timing->mr14 << 16); 639 mmio_clrsetbits_32(CTL_REG(i, 145), 0xffff << 16, 640 pdram_timing->mr22 << 16); 641 mmio_clrsetbits_32(CTL_REG(i, 154), 0xffff << 16, 642 pdram_timing->mr12 << 16); 643 mmio_clrsetbits_32(CTL_REG(i, 156), 0xffff << 16, 644 pdram_timing->mr14 << 16); 645 mmio_clrsetbits_32(CTL_REG(i, 159), 0xffff << 16, 646 pdram_timing->mr22 << 16); 647 } 648 mmio_clrsetbits_32(CTL_REG(i, 179), 0xfff << 8, 649 pdram_timing->tzqinit << 8); 650 mmio_write_32(CTL_REG(i, 180), (pdram_timing->tzqcs << 16) | 651 (pdram_timing->tzqinit / 2)); 652 mmio_write_32(CTL_REG(i, 181), (pdram_timing->tzqlat << 16) | 653 pdram_timing->tzqcal); 654 mmio_clrsetbits_32(CTL_REG(i, 212), 0xff << 8, 655 pdram_timing->todton << 8); 656 657 if (timing_config->odt) { 658 mmio_setbits_32(CTL_REG(i, 213), 1 << 16); 659 if (timing_config->freq < 400) 660 tmp = 4 << 24; 661 else 662 tmp = 8 << 24; 663 } else { 664 mmio_clrbits_32(CTL_REG(i, 213), 1 << 16); 665 tmp = 2 << 24; 666 } 667 668 mmio_clrsetbits_32(CTL_REG(i, 216), 0x1f << 24, tmp); 669 mmio_clrsetbits_32(CTL_REG(i, 221), (0x3 << 16) | (0xf << 8), 670 (pdram_timing->tdqsck << 16) | 671 (pdram_timing->tdqsck_max << 8)); 672 tmp = 673 (get_wrlat_adj(timing_config->dram_type, pdram_timing->cwl) 674 << 8) | get_rdlat_adj(timing_config->dram_type, 675 pdram_timing->cl); 676 mmio_clrsetbits_32(CTL_REG(i, 284), 0xffff, tmp); 677 mmio_clrsetbits_32(CTL_REG(i, 82), 0xffff << 16, 678 (4 * pdram_timing->trefi) << 16); 679 680 mmio_clrsetbits_32(CTL_REG(i, 83), 0xffff, 681 (2 * pdram_timing->trefi) & 0xffff); 682 683 if ((timing_config->dram_type == LPDDR3) || 684 (timing_config->dram_type == LPDDR4)) { 685 tmp = get_pi_wrlat(pdram_timing, timing_config); 686 tmp1 = get_pi_todtoff_max(pdram_timing, timing_config); 687 tmp = (tmp > tmp1) ? (tmp - tmp1) : 0; 688 } else { 689 tmp = 0; 690 } 691 mmio_clrsetbits_32(CTL_REG(i, 214), 0x3f << 16, 692 (tmp & 0x3f) << 16); 693 694 if ((timing_config->dram_type == LPDDR3) || 695 (timing_config->dram_type == LPDDR4)) { 696 /* min_rl_preamble = cl+TDQSCK_MIN -1 */ 697 tmp = pdram_timing->cl + 698 get_pi_todtoff_min(pdram_timing, timing_config) - 1; 699 /* todtoff_max */ 700 tmp1 = get_pi_todtoff_max(pdram_timing, timing_config); 701 tmp = (tmp > tmp1) ? (tmp - tmp1) : 0; 702 } else { 703 tmp = pdram_timing->cl - pdram_timing->cwl; 704 } 705 mmio_clrsetbits_32(CTL_REG(i, 215), 0x3f << 8, 706 (tmp & 0x3f) << 8); 707 708 mmio_clrsetbits_32(CTL_REG(i, 275), 0xff << 16, 709 (get_pi_tdfi_phy_rdlat(pdram_timing, 710 timing_config) & 711 0xff) << 16); 712 713 mmio_clrsetbits_32(CTL_REG(i, 277), 0xffff, 714 (2 * pdram_timing->trefi) & 0xffff); 715 716 mmio_clrsetbits_32(CTL_REG(i, 282), 0xffff, 717 (2 * pdram_timing->trefi) & 0xffff); 718 719 mmio_write_32(CTL_REG(i, 283), 20 * pdram_timing->trefi); 720 721 /* CTL_308 TDFI_CALVL_CAPTURE_F0:RW:16:10 */ 722 tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1; 723 if ((20000 % (1000000 / pdram_timing->mhz)) != 0) 724 tmp1++; 725 tmp = (tmp1 >> 1) + (tmp1 % 2) + 5; 726 mmio_clrsetbits_32(CTL_REG(i, 308), 0x3ff << 16, tmp << 16); 727 728 /* CTL_308 TDFI_CALVL_CC_F0:RW:0:10 */ 729 tmp = tmp + 18; 730 mmio_clrsetbits_32(CTL_REG(i, 308), 0x3ff, tmp); 731 732 /* CTL_314 TDFI_WRCSLAT_F0:RW:8:8 */ 733 tmp1 = get_pi_wrlat_adj(pdram_timing, timing_config); 734 if (timing_config->freq <= ENPER_CS_TRAINING_FREQ) { 735 if (tmp1 == 0) 736 tmp = 0; 737 else if (tmp1 < 5) 738 tmp = tmp1 - 1; 739 else 740 tmp = tmp1 - 5; 741 } else { 742 tmp = tmp1 - 2; 743 } 744 mmio_clrsetbits_32(CTL_REG(i, 314), 0xff << 8, tmp << 8); 745 746 /* CTL_314 TDFI_RDCSLAT_F0:RW:0:8 */ 747 if ((timing_config->freq <= ENPER_CS_TRAINING_FREQ) && 748 (pdram_timing->cl >= 5)) 749 tmp = pdram_timing->cl - 5; 750 else 751 tmp = pdram_timing->cl - 2; 752 mmio_clrsetbits_32(CTL_REG(i, 314), 0xff, tmp); 753 } 754 } 755 756 static void gen_rk3399_ctl_params_f1(struct timing_related_config 757 *timing_config, 758 struct dram_timing_t *pdram_timing) 759 { 760 uint32_t i; 761 uint32_t tmp, tmp1; 762 763 for (i = 0; i < timing_config->ch_cnt; i++) { 764 if (timing_config->dram_type == DDR3) { 765 tmp = 766 ((700000 + 10) * timing_config->freq + 999) / 1000; 767 tmp += pdram_timing->txsnr + (pdram_timing->tmrd * 3) + 768 pdram_timing->tmod + pdram_timing->tzqinit; 769 mmio_write_32(CTL_REG(i, 9), tmp); 770 mmio_clrsetbits_32(CTL_REG(i, 22), 0xffff << 16, 771 pdram_timing->tdllk << 16); 772 mmio_clrsetbits_32(CTL_REG(i, 34), 0xffffff00, 773 (pdram_timing->tmod << 24) | 774 (pdram_timing->tmrd << 16) | 775 (pdram_timing->trtp << 8)); 776 mmio_clrsetbits_32(CTL_REG(i, 60), 0xffff << 16, 777 (pdram_timing->txsr - 778 pdram_timing->trcd) << 16); 779 } else if (timing_config->dram_type == LPDDR4) { 780 mmio_write_32(CTL_REG(i, 9), pdram_timing->tinit1 + 781 pdram_timing->tinit3); 782 mmio_clrsetbits_32(CTL_REG(i, 34), 0xffffff00, 783 (pdram_timing->tmrd << 24) | 784 (pdram_timing->tmrd << 16) | 785 (pdram_timing->trtp << 8)); 786 mmio_clrsetbits_32(CTL_REG(i, 60), 0xffff << 16, 787 pdram_timing->txsr << 16); 788 } else { 789 mmio_write_32(CTL_REG(i, 9), pdram_timing->tinit1); 790 mmio_write_32(CTL_REG(i, 11), pdram_timing->tinit4); 791 mmio_clrsetbits_32(CTL_REG(i, 34), 0xffffff00, 792 (pdram_timing->tmrd << 24) | 793 (pdram_timing->tmrd << 16) | 794 (pdram_timing->trtp << 8)); 795 mmio_clrsetbits_32(CTL_REG(i, 60), 0xffff << 16, 796 pdram_timing->txsr << 16); 797 } 798 mmio_write_32(CTL_REG(i, 10), pdram_timing->tinit3); 799 mmio_write_32(CTL_REG(i, 12), pdram_timing->tinit5); 800 mmio_clrsetbits_32(CTL_REG(i, 24), (0x7f << 8), 801 ((pdram_timing->cl * 2) << 8)); 802 mmio_clrsetbits_32(CTL_REG(i, 24), (0x1f << 16), 803 (pdram_timing->cwl << 16)); 804 mmio_clrsetbits_32(CTL_REG(i, 24), 0x3f << 24, 805 pdram_timing->al << 24); 806 mmio_clrsetbits_32(CTL_REG(i, 28), 0xffffff00, 807 (pdram_timing->tras_min << 24) | 808 (pdram_timing->trc << 16) | 809 (pdram_timing->trrd << 8)); 810 mmio_clrsetbits_32(CTL_REG(i, 29), 0xffffff, 811 (pdram_timing->tfaw << 16) | 812 (pdram_timing->trppb << 8) | 813 pdram_timing->twtr); 814 mmio_write_32(CTL_REG(i, 35), (pdram_timing->tcke << 24) | 815 pdram_timing->tras_max); 816 mmio_clrsetbits_32(CTL_REG(i, 36), 0xff, 817 max(1, pdram_timing->tckesr)); 818 mmio_clrsetbits_32(CTL_REG(i, 39), (0xff << 24), 819 (pdram_timing->trcd << 24)); 820 mmio_clrsetbits_32(CTL_REG(i, 40), 0x3f, pdram_timing->twr); 821 mmio_clrsetbits_32(CTL_REG(i, 42), 0x1f << 24, 822 pdram_timing->tmrz << 24); 823 tmp = pdram_timing->tdal ? pdram_timing->tdal : 824 (pdram_timing->twr + pdram_timing->trp); 825 mmio_clrsetbits_32(CTL_REG(i, 44), 0xff << 8, tmp << 8); 826 mmio_clrsetbits_32(CTL_REG(i, 45), 0xff << 8, 827 pdram_timing->trp << 8); 828 mmio_write_32(CTL_REG(i, 49), 829 ((pdram_timing->trefi - 8) << 16) | 830 pdram_timing->trfc); 831 mmio_clrsetbits_32(CTL_REG(i, 52), 0xffff << 16, 832 pdram_timing->txp << 16); 833 mmio_clrsetbits_32(CTL_REG(i, 54), 0xffff, 834 pdram_timing->txpdll); 835 mmio_clrsetbits_32(CTL_REG(i, 55), 0xff << 8, 836 pdram_timing->tmrri << 8); 837 mmio_write_32(CTL_REG(i, 57), (pdram_timing->tmrwckel << 24) | 838 (pdram_timing->tckehcs << 16) | 839 (pdram_timing->tckelcs << 8) | 840 pdram_timing->tcscke); 841 mmio_clrsetbits_32(CTL_REG(i, 58), 0xf, pdram_timing->tzqcke); 842 mmio_clrsetbits_32(CTL_REG(i, 61), 0xffff, pdram_timing->txsnr); 843 mmio_clrsetbits_32(CTL_REG(i, 64), 0xffff << 16, 844 (pdram_timing->tckehcmd << 24) | 845 (pdram_timing->tckelcmd << 16)); 846 mmio_write_32(CTL_REG(i, 65), (pdram_timing->tckelpd << 24) | 847 (pdram_timing->tescke << 16) | 848 (pdram_timing->tsr << 8) | 849 pdram_timing->tckckel); 850 mmio_clrsetbits_32(CTL_REG(i, 66), 0xfff, 851 (pdram_timing->tcmdcke << 8) | 852 pdram_timing->tcsckeh); 853 mmio_clrsetbits_32(CTL_REG(i, 92), (0xff << 24), 854 (pdram_timing->tcksre << 24)); 855 mmio_clrsetbits_32(CTL_REG(i, 93), 0xff, 856 pdram_timing->tcksrx); 857 mmio_clrsetbits_32(CTL_REG(i, 108), (0x1 << 25), 858 (timing_config->dllbp << 25)); 859 mmio_write_32(CTL_REG(i, 125), 860 (pdram_timing->tvrcg_disable << 16) | 861 pdram_timing->tvrcg_enable); 862 mmio_write_32(CTL_REG(i, 126), (pdram_timing->tckfspx << 24) | 863 (pdram_timing->tckfspe << 16) | 864 pdram_timing->tfc_long); 865 mmio_clrsetbits_32(CTL_REG(i, 127), 0xffff, 866 pdram_timing->tvref_long); 867 mmio_clrsetbits_32(CTL_REG(i, 134), 0xffff << 16, 868 pdram_timing->mr[0] << 16); 869 mmio_write_32(CTL_REG(i, 135), (pdram_timing->mr[2] << 16) | 870 pdram_timing->mr[1]); 871 mmio_clrsetbits_32(CTL_REG(i, 138), 0xffff << 16, 872 pdram_timing->mr[3] << 16); 873 mmio_clrsetbits_32(CTL_REG(i, 140), 0xff, pdram_timing->mr11); 874 mmio_clrsetbits_32(CTL_REG(i, 148), 0xffff << 16, 875 pdram_timing->mr[0] << 16); 876 mmio_write_32(CTL_REG(i, 149), (pdram_timing->mr[2] << 16) | 877 pdram_timing->mr[1]); 878 mmio_clrsetbits_32(CTL_REG(i, 152), 0xffff << 16, 879 pdram_timing->mr[3] << 16); 880 mmio_clrsetbits_32(CTL_REG(i, 154), 0xff, pdram_timing->mr11); 881 if (timing_config->dram_type == LPDDR4) { 882 mmio_clrsetbits_32(CTL_REG(i, 141), 0xffff, 883 pdram_timing->mr12); 884 mmio_clrsetbits_32(CTL_REG(i, 143), 0xffff, 885 pdram_timing->mr14); 886 mmio_clrsetbits_32(CTL_REG(i, 146), 0xffff, 887 pdram_timing->mr22); 888 mmio_clrsetbits_32(CTL_REG(i, 155), 0xffff, 889 pdram_timing->mr12); 890 mmio_clrsetbits_32(CTL_REG(i, 157), 0xffff, 891 pdram_timing->mr14); 892 mmio_clrsetbits_32(CTL_REG(i, 160), 0xffff, 893 pdram_timing->mr22); 894 } 895 mmio_write_32(CTL_REG(i, 182), 896 ((pdram_timing->tzqinit / 2) << 16) | 897 pdram_timing->tzqinit); 898 mmio_write_32(CTL_REG(i, 183), (pdram_timing->tzqcal << 16) | 899 pdram_timing->tzqcs); 900 mmio_clrsetbits_32(CTL_REG(i, 184), 0x3f, pdram_timing->tzqlat); 901 mmio_clrsetbits_32(CTL_REG(i, 188), 0xfff, 902 pdram_timing->tzqreset); 903 mmio_clrsetbits_32(CTL_REG(i, 212), 0xff << 16, 904 pdram_timing->todton << 16); 905 906 if (timing_config->odt) { 907 mmio_setbits_32(CTL_REG(i, 213), (1 << 24)); 908 if (timing_config->freq < 400) 909 tmp = 4 << 24; 910 else 911 tmp = 8 << 24; 912 } else { 913 mmio_clrbits_32(CTL_REG(i, 213), (1 << 24)); 914 tmp = 2 << 24; 915 } 916 mmio_clrsetbits_32(CTL_REG(i, 217), 0x1f << 24, tmp); 917 mmio_clrsetbits_32(CTL_REG(i, 221), 0xf << 24, 918 (pdram_timing->tdqsck_max << 24)); 919 mmio_clrsetbits_32(CTL_REG(i, 222), 0x3, pdram_timing->tdqsck); 920 mmio_clrsetbits_32(CTL_REG(i, 291), 0xffff, 921 (get_wrlat_adj(timing_config->dram_type, 922 pdram_timing->cwl) << 8) | 923 get_rdlat_adj(timing_config->dram_type, 924 pdram_timing->cl)); 925 926 mmio_clrsetbits_32(CTL_REG(i, 84), 0xffff, 927 (4 * pdram_timing->trefi) & 0xffff); 928 929 mmio_clrsetbits_32(CTL_REG(i, 84), 0xffff << 16, 930 ((2 * pdram_timing->trefi) & 0xffff) << 16); 931 932 if ((timing_config->dram_type == LPDDR3) || 933 (timing_config->dram_type == LPDDR4)) { 934 tmp = get_pi_wrlat(pdram_timing, timing_config); 935 tmp1 = get_pi_todtoff_max(pdram_timing, timing_config); 936 tmp = (tmp > tmp1) ? (tmp - tmp1) : 0; 937 } else { 938 tmp = 0; 939 } 940 mmio_clrsetbits_32(CTL_REG(i, 214), 0x3f << 24, 941 (tmp & 0x3f) << 24); 942 943 if ((timing_config->dram_type == LPDDR3) || 944 (timing_config->dram_type == LPDDR4)) { 945 /* min_rl_preamble = cl + TDQSCK_MIN - 1 */ 946 tmp = pdram_timing->cl + 947 get_pi_todtoff_min(pdram_timing, timing_config); 948 tmp--; 949 /* todtoff_max */ 950 tmp1 = get_pi_todtoff_max(pdram_timing, timing_config); 951 tmp = (tmp > tmp1) ? (tmp - tmp1) : 0; 952 } else { 953 tmp = pdram_timing->cl - pdram_timing->cwl; 954 } 955 mmio_clrsetbits_32(CTL_REG(i, 215), 0x3f << 16, 956 (tmp & 0x3f) << 16); 957 958 mmio_clrsetbits_32(CTL_REG(i, 275), 0xff << 24, 959 (get_pi_tdfi_phy_rdlat(pdram_timing, 960 timing_config) & 961 0xff) << 24); 962 963 mmio_clrsetbits_32(CTL_REG(i, 284), 0xffff << 16, 964 ((2 * pdram_timing->trefi) & 0xffff) << 16); 965 966 mmio_clrsetbits_32(CTL_REG(i, 289), 0xffff, 967 (2 * pdram_timing->trefi) & 0xffff); 968 969 mmio_write_32(CTL_REG(i, 290), 20 * pdram_timing->trefi); 970 971 /* CTL_309 TDFI_CALVL_CAPTURE_F1:RW:16:10 */ 972 tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1; 973 if ((20000 % (1000000 / pdram_timing->mhz)) != 0) 974 tmp1++; 975 tmp = (tmp1 >> 1) + (tmp1 % 2) + 5; 976 mmio_clrsetbits_32(CTL_REG(i, 309), 0x3ff << 16, tmp << 16); 977 978 /* CTL_309 TDFI_CALVL_CC_F1:RW:0:10 */ 979 tmp = tmp + 18; 980 mmio_clrsetbits_32(CTL_REG(i, 309), 0x3ff, tmp); 981 982 /* CTL_314 TDFI_WRCSLAT_F1:RW:24:8 */ 983 tmp1 = get_pi_wrlat_adj(pdram_timing, timing_config); 984 if (timing_config->freq <= ENPER_CS_TRAINING_FREQ) { 985 if (tmp1 == 0) 986 tmp = 0; 987 else if (tmp1 < 5) 988 tmp = tmp1 - 1; 989 else 990 tmp = tmp1 - 5; 991 } else { 992 tmp = tmp1 - 2; 993 } 994 995 mmio_clrsetbits_32(CTL_REG(i, 314), 0xff << 24, tmp << 24); 996 997 /* CTL_314 TDFI_RDCSLAT_F1:RW:16:8 */ 998 if ((timing_config->freq <= ENPER_CS_TRAINING_FREQ) && 999 (pdram_timing->cl >= 5)) 1000 tmp = pdram_timing->cl - 5; 1001 else 1002 tmp = pdram_timing->cl - 2; 1003 mmio_clrsetbits_32(CTL_REG(i, 314), 0xff << 16, tmp << 16); 1004 } 1005 } 1006 1007 static void gen_rk3399_enable_training(uint32_t ch_cnt, uint32_t nmhz) 1008 { 1009 uint32_t i, tmp; 1010 1011 if (nmhz <= PHY_DLL_BYPASS_FREQ) 1012 tmp = 0; 1013 else 1014 tmp = 1; 1015 1016 for (i = 0; i < ch_cnt; i++) { 1017 mmio_clrsetbits_32(CTL_REG(i, 305), 1 << 16, tmp << 16); 1018 mmio_clrsetbits_32(CTL_REG(i, 71), 1, tmp); 1019 } 1020 } 1021 1022 static void gen_rk3399_ctl_params(struct timing_related_config *timing_config, 1023 struct dram_timing_t *pdram_timing, 1024 uint32_t fn) 1025 { 1026 if (fn == 0) 1027 gen_rk3399_ctl_params_f0(timing_config, pdram_timing); 1028 else 1029 gen_rk3399_ctl_params_f1(timing_config, pdram_timing); 1030 } 1031 1032 static void gen_rk3399_pi_params_f0(struct timing_related_config *timing_config, 1033 struct dram_timing_t *pdram_timing) 1034 { 1035 uint32_t tmp, tmp1, tmp2; 1036 uint32_t i; 1037 1038 for (i = 0; i < timing_config->ch_cnt; i++) { 1039 /* PI_02 PI_TDFI_PHYMSTR_MAX_F0:RW:0:32 */ 1040 tmp = 4 * pdram_timing->trefi; 1041 mmio_write_32(PI_REG(i, 2), tmp); 1042 /* PI_03 PI_TDFI_PHYMSTR_RESP_F0:RW:0:16 */ 1043 tmp = 2 * pdram_timing->trefi; 1044 mmio_clrsetbits_32(PI_REG(i, 3), 0xffff, tmp); 1045 /* PI_07 PI_TDFI_PHYUPD_RESP_F0:RW:16:16 */ 1046 mmio_clrsetbits_32(PI_REG(i, 7), 0xffff << 16, tmp << 16); 1047 1048 /* PI_42 PI_TDELAY_RDWR_2_BUS_IDLE_F0:RW:0:8 */ 1049 if (timing_config->dram_type == LPDDR4) 1050 tmp = 2; 1051 else 1052 tmp = 0; 1053 tmp = (pdram_timing->bl / 2) + 4 + 1054 (get_pi_rdlat_adj(pdram_timing) - 2) + tmp + 1055 get_pi_tdfi_phy_rdlat(pdram_timing, timing_config); 1056 mmio_clrsetbits_32(PI_REG(i, 42), 0xff, tmp); 1057 /* PI_43 PI_WRLAT_F0:RW:0:5 */ 1058 if (timing_config->dram_type == LPDDR3) { 1059 tmp = get_pi_wrlat(pdram_timing, timing_config); 1060 mmio_clrsetbits_32(PI_REG(i, 43), 0x1f, tmp); 1061 } 1062 /* PI_43 PI_ADDITIVE_LAT_F0:RW:8:6 */ 1063 mmio_clrsetbits_32(PI_REG(i, 43), 0x3f << 8, 1064 PI_ADD_LATENCY << 8); 1065 1066 /* PI_43 PI_CASLAT_LIN_F0:RW:16:7 */ 1067 mmio_clrsetbits_32(PI_REG(i, 43), 0x7f << 16, 1068 (pdram_timing->cl * 2) << 16); 1069 /* PI_46 PI_TREF_F0:RW:16:16 */ 1070 mmio_clrsetbits_32(PI_REG(i, 46), 0xffff << 16, 1071 pdram_timing->trefi << 16); 1072 /* PI_46 PI_TRFC_F0:RW:0:10 */ 1073 mmio_clrsetbits_32(PI_REG(i, 46), 0x3ff, pdram_timing->trfc); 1074 /* PI_66 PI_TODTL_2CMD_F0:RW:24:8 */ 1075 if (timing_config->dram_type == LPDDR3) { 1076 tmp = get_pi_todtoff_max(pdram_timing, timing_config); 1077 mmio_clrsetbits_32(PI_REG(i, 66), 0xff << 24, 1078 tmp << 24); 1079 } 1080 /* PI_72 PI_WR_TO_ODTH_F0:RW:16:6 */ 1081 if ((timing_config->dram_type == LPDDR3) || 1082 (timing_config->dram_type == LPDDR4)) { 1083 tmp1 = get_pi_wrlat(pdram_timing, timing_config); 1084 tmp2 = get_pi_todtoff_max(pdram_timing, timing_config); 1085 if (tmp1 > tmp2) 1086 tmp = tmp1 - tmp2; 1087 else 1088 tmp = 0; 1089 } else if (timing_config->dram_type == DDR3) { 1090 tmp = 0; 1091 } 1092 mmio_clrsetbits_32(PI_REG(i, 72), 0x3f << 16, tmp << 16); 1093 /* PI_73 PI_RD_TO_ODTH_F0:RW:8:6 */ 1094 if ((timing_config->dram_type == LPDDR3) || 1095 (timing_config->dram_type == LPDDR4)) { 1096 /* min_rl_preamble = cl + TDQSCK_MIN - 1 */ 1097 tmp1 = pdram_timing->cl; 1098 tmp1 += get_pi_todtoff_min(pdram_timing, timing_config); 1099 tmp1--; 1100 /* todtoff_max */ 1101 tmp2 = get_pi_todtoff_max(pdram_timing, timing_config); 1102 if (tmp1 > tmp2) 1103 tmp = tmp1 - tmp2; 1104 else 1105 tmp = 0; 1106 } else if (timing_config->dram_type == DDR3) { 1107 tmp = pdram_timing->cl - pdram_timing->cwl; 1108 } 1109 mmio_clrsetbits_32(PI_REG(i, 73), 0x3f << 8, tmp << 8); 1110 /* PI_89 PI_RDLAT_ADJ_F0:RW:16:8 */ 1111 tmp = get_pi_rdlat_adj(pdram_timing); 1112 mmio_clrsetbits_32(PI_REG(i, 89), 0xff << 16, tmp << 16); 1113 /* PI_90 PI_WRLAT_ADJ_F0:RW:16:8 */ 1114 tmp = get_pi_wrlat_adj(pdram_timing, timing_config); 1115 mmio_clrsetbits_32(PI_REG(i, 90), 0xff << 16, tmp << 16); 1116 /* PI_91 PI_TDFI_WRCSLAT_F0:RW:16:8 */ 1117 tmp1 = tmp; 1118 if (tmp1 == 0) 1119 tmp = 0; 1120 else if (tmp1 < 5) 1121 tmp = tmp1 - 1; 1122 else 1123 tmp = tmp1 - 5; 1124 mmio_clrsetbits_32(PI_REG(i, 91), 0xff << 16, tmp << 16); 1125 /* PI_95 PI_TDFI_CALVL_CAPTURE_F0:RW:16:10 */ 1126 tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1; 1127 if ((20000 % (1000000 / pdram_timing->mhz)) != 0) 1128 tmp1++; 1129 tmp = (tmp1 >> 1) + (tmp1 % 2) + 5; 1130 mmio_clrsetbits_32(PI_REG(i, 95), 0x3ff << 16, tmp << 16); 1131 /* PI_95 PI_TDFI_CALVL_CC_F0:RW:0:10 */ 1132 mmio_clrsetbits_32(PI_REG(i, 95), 0x3ff, tmp + 18); 1133 /* PI_102 PI_TMRZ_F0:RW:8:5 */ 1134 mmio_clrsetbits_32(PI_REG(i, 102), 0x1f << 8, 1135 pdram_timing->tmrz << 8); 1136 /* PI_111 PI_TDFI_CALVL_STROBE_F0:RW:8:4 */ 1137 tmp1 = 2 * 1000 / (1000000 / pdram_timing->mhz); 1138 if ((2 * 1000 % (1000000 / pdram_timing->mhz)) != 0) 1139 tmp1++; 1140 /* pi_tdfi_calvl_strobe=tds_train+5 */ 1141 tmp = tmp1 + 5; 1142 mmio_clrsetbits_32(PI_REG(i, 111), 0xf << 8, tmp << 8); 1143 /* PI_116 PI_TCKEHDQS_F0:RW:16:6 */ 1144 tmp = 10000 / (1000000 / pdram_timing->mhz); 1145 if ((10000 % (1000000 / pdram_timing->mhz)) != 0) 1146 tmp++; 1147 if (pdram_timing->mhz <= 100) 1148 tmp = tmp + 1; 1149 else 1150 tmp = tmp + 8; 1151 mmio_clrsetbits_32(PI_REG(i, 116), 0x3f << 16, tmp << 16); 1152 /* PI_125 PI_MR1_DATA_F0_0:RW+:8:16 */ 1153 mmio_clrsetbits_32(PI_REG(i, 125), 0xffff << 8, 1154 pdram_timing->mr[1] << 8); 1155 /* PI_133 PI_MR1_DATA_F0_1:RW+:0:16 */ 1156 mmio_clrsetbits_32(PI_REG(i, 133), 0xffff, pdram_timing->mr[1]); 1157 /* PI_140 PI_MR1_DATA_F0_2:RW+:16:16 */ 1158 mmio_clrsetbits_32(PI_REG(i, 140), 0xffff << 16, 1159 pdram_timing->mr[1] << 16); 1160 /* PI_148 PI_MR1_DATA_F0_3:RW+:0:16 */ 1161 mmio_clrsetbits_32(PI_REG(i, 148), 0xffff, pdram_timing->mr[1]); 1162 /* PI_126 PI_MR2_DATA_F0_0:RW+:0:16 */ 1163 mmio_clrsetbits_32(PI_REG(i, 126), 0xffff, pdram_timing->mr[2]); 1164 /* PI_133 PI_MR2_DATA_F0_1:RW+:16:16 */ 1165 mmio_clrsetbits_32(PI_REG(i, 133), 0xffff << 16, 1166 pdram_timing->mr[2] << 16); 1167 /* PI_141 PI_MR2_DATA_F0_2:RW+:0:16 */ 1168 mmio_clrsetbits_32(PI_REG(i, 141), 0xffff, pdram_timing->mr[2]); 1169 /* PI_148 PI_MR2_DATA_F0_3:RW+:16:16 */ 1170 mmio_clrsetbits_32(PI_REG(i, 148), 0xffff << 16, 1171 pdram_timing->mr[2] << 16); 1172 /* PI_156 PI_TFC_F0:RW:0:10 */ 1173 mmio_clrsetbits_32(PI_REG(i, 156), 0x3ff, pdram_timing->trfc); 1174 /* PI_158 PI_TWR_F0:RW:24:6 */ 1175 mmio_clrsetbits_32(PI_REG(i, 158), 0x3f << 24, 1176 pdram_timing->twr << 24); 1177 /* PI_158 PI_TWTR_F0:RW:16:6 */ 1178 mmio_clrsetbits_32(PI_REG(i, 158), 0x3f << 16, 1179 pdram_timing->twtr << 16); 1180 /* PI_158 PI_TRCD_F0:RW:8:8 */ 1181 mmio_clrsetbits_32(PI_REG(i, 158), 0xff << 8, 1182 pdram_timing->trcd << 8); 1183 /* PI_158 PI_TRP_F0:RW:0:8 */ 1184 mmio_clrsetbits_32(PI_REG(i, 158), 0xff, pdram_timing->trp); 1185 /* PI_157 PI_TRTP_F0:RW:24:8 */ 1186 mmio_clrsetbits_32(PI_REG(i, 157), 0xff << 24, 1187 pdram_timing->trtp << 24); 1188 /* PI_159 PI_TRAS_MIN_F0:RW:24:8 */ 1189 mmio_clrsetbits_32(PI_REG(i, 159), 0xff << 24, 1190 pdram_timing->tras_min << 24); 1191 /* PI_159 PI_TRAS_MAX_F0:RW:0:17 */ 1192 tmp = pdram_timing->tras_max * 99 / 100; 1193 mmio_clrsetbits_32(PI_REG(i, 159), 0x1ffff, tmp); 1194 /* PI_160 PI_TMRD_F0:RW:16:6 */ 1195 mmio_clrsetbits_32(PI_REG(i, 160), 0x3f << 16, 1196 pdram_timing->tmrd << 16); 1197 /*PI_160 PI_TDQSCK_MAX_F0:RW:0:4 */ 1198 mmio_clrsetbits_32(PI_REG(i, 160), 0xf, 1199 pdram_timing->tdqsck_max); 1200 /* PI_187 PI_TDFI_CTRLUPD_MAX_F0:RW:8:16 */ 1201 mmio_clrsetbits_32(PI_REG(i, 187), 0xffff << 8, 1202 (2 * pdram_timing->trefi) << 8); 1203 /* PI_188 PI_TDFI_CTRLUPD_INTERVAL_F0:RW:0:32 */ 1204 mmio_clrsetbits_32(PI_REG(i, 188), 0xffffffff, 1205 20 * pdram_timing->trefi); 1206 } 1207 } 1208 1209 static void gen_rk3399_pi_params_f1(struct timing_related_config *timing_config, 1210 struct dram_timing_t *pdram_timing) 1211 { 1212 uint32_t tmp, tmp1, tmp2; 1213 uint32_t i; 1214 1215 for (i = 0; i < timing_config->ch_cnt; i++) { 1216 /* PI_04 PI_TDFI_PHYMSTR_MAX_F1:RW:0:32 */ 1217 tmp = 4 * pdram_timing->trefi; 1218 mmio_write_32(PI_REG(i, 4), tmp); 1219 /* PI_05 PI_TDFI_PHYMSTR_RESP_F1:RW:0:16 */ 1220 tmp = 2 * pdram_timing->trefi; 1221 mmio_clrsetbits_32(PI_REG(i, 5), 0xffff, tmp); 1222 /* PI_12 PI_TDFI_PHYUPD_RESP_F1:RW:0:16 */ 1223 mmio_clrsetbits_32(PI_REG(i, 12), 0xffff, tmp); 1224 1225 /* PI_42 PI_TDELAY_RDWR_2_BUS_IDLE_F1:RW:8:8 */ 1226 if (timing_config->dram_type == LPDDR4) 1227 tmp = 2; 1228 else 1229 tmp = 0; 1230 tmp = (pdram_timing->bl / 2) + 4 + 1231 (get_pi_rdlat_adj(pdram_timing) - 2) + tmp + 1232 get_pi_tdfi_phy_rdlat(pdram_timing, timing_config); 1233 mmio_clrsetbits_32(PI_REG(i, 42), 0xff << 8, tmp << 8); 1234 /* PI_43 PI_WRLAT_F1:RW:24:5 */ 1235 if (timing_config->dram_type == LPDDR3) { 1236 tmp = get_pi_wrlat(pdram_timing, timing_config); 1237 mmio_clrsetbits_32(PI_REG(i, 43), 0x1f << 24, 1238 tmp << 24); 1239 } 1240 /* PI_44 PI_ADDITIVE_LAT_F1:RW:0:6 */ 1241 mmio_clrsetbits_32(PI_REG(i, 44), 0x3f, PI_ADD_LATENCY); 1242 /* PI_44 PI_CASLAT_LIN_F1:RW:8:7:=0x18 */ 1243 mmio_clrsetbits_32(PI_REG(i, 44), 0x7f << 8, 1244 pdram_timing->cl * 2); 1245 /* PI_47 PI_TREF_F1:RW:16:16 */ 1246 mmio_clrsetbits_32(PI_REG(i, 47), 0xffff << 16, 1247 pdram_timing->trefi << 16); 1248 /* PI_47 PI_TRFC_F1:RW:0:10 */ 1249 mmio_clrsetbits_32(PI_REG(i, 47), 0x3ff, pdram_timing->trfc); 1250 /* PI_67 PI_TODTL_2CMD_F1:RW:8:8 */ 1251 if (timing_config->dram_type == LPDDR3) { 1252 tmp = get_pi_todtoff_max(pdram_timing, timing_config); 1253 mmio_clrsetbits_32(PI_REG(i, 67), 0xff << 8, tmp << 8); 1254 } 1255 /* PI_72 PI_WR_TO_ODTH_F1:RW:24:6 */ 1256 if ((timing_config->dram_type == LPDDR3) || 1257 (timing_config->dram_type == LPDDR4)) { 1258 tmp1 = get_pi_wrlat(pdram_timing, timing_config); 1259 tmp2 = get_pi_todtoff_max(pdram_timing, timing_config); 1260 if (tmp1 > tmp2) 1261 tmp = tmp1 - tmp2; 1262 else 1263 tmp = 0; 1264 } else if (timing_config->dram_type == DDR3) { 1265 tmp = 0; 1266 } 1267 mmio_clrsetbits_32(PI_REG(i, 72), 0x3f << 24, tmp << 24); 1268 /* PI_73 PI_RD_TO_ODTH_F1:RW:16:6 */ 1269 if ((timing_config->dram_type == LPDDR3) || 1270 (timing_config->dram_type == LPDDR4)) { 1271 /* min_rl_preamble = cl + TDQSCK_MIN - 1 */ 1272 tmp1 = pdram_timing->cl + 1273 get_pi_todtoff_min(pdram_timing, timing_config); 1274 tmp1--; 1275 /* todtoff_max */ 1276 tmp2 = get_pi_todtoff_max(pdram_timing, timing_config); 1277 if (tmp1 > tmp2) 1278 tmp = tmp1 - tmp2; 1279 else 1280 tmp = 0; 1281 } else if (timing_config->dram_type == DDR3) 1282 tmp = pdram_timing->cl - pdram_timing->cwl; 1283 1284 mmio_clrsetbits_32(PI_REG(i, 73), 0x3f << 16, tmp << 16); 1285 /*P I_89 PI_RDLAT_ADJ_F1:RW:24:8 */ 1286 tmp = get_pi_rdlat_adj(pdram_timing); 1287 mmio_clrsetbits_32(PI_REG(i, 89), 0xff << 24, tmp << 24); 1288 /* PI_90 PI_WRLAT_ADJ_F1:RW:24:8 */ 1289 tmp = get_pi_wrlat_adj(pdram_timing, timing_config); 1290 mmio_clrsetbits_32(PI_REG(i, 90), 0xff << 24, tmp << 24); 1291 /* PI_91 PI_TDFI_WRCSLAT_F1:RW:24:8 */ 1292 tmp1 = tmp; 1293 if (tmp1 == 0) 1294 tmp = 0; 1295 else if (tmp1 < 5) 1296 tmp = tmp1 - 1; 1297 else 1298 tmp = tmp1 - 5; 1299 mmio_clrsetbits_32(PI_REG(i, 91), 0xff << 24, tmp << 24); 1300 /*PI_96 PI_TDFI_CALVL_CAPTURE_F1:RW:16:10 */ 1301 /* tadr=20ns */ 1302 tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1; 1303 if ((20000 % (1000000 / pdram_timing->mhz)) != 0) 1304 tmp1++; 1305 tmp = (tmp1 >> 1) + (tmp1 % 2) + 5; 1306 mmio_clrsetbits_32(PI_REG(i, 96), 0x3ff << 16, tmp << 16); 1307 /* PI_96 PI_TDFI_CALVL_CC_F1:RW:0:10 */ 1308 tmp = tmp + 18; 1309 mmio_clrsetbits_32(PI_REG(i, 96), 0x3ff, tmp); 1310 /*PI_103 PI_TMRZ_F1:RW:0:5 */ 1311 mmio_clrsetbits_32(PI_REG(i, 103), 0x1f, pdram_timing->tmrz); 1312 /*PI_111 PI_TDFI_CALVL_STROBE_F1:RW:16:4 */ 1313 /* tds_train=ceil(2/ns) */ 1314 tmp1 = 2 * 1000 / (1000000 / pdram_timing->mhz); 1315 if ((2 * 1000 % (1000000 / pdram_timing->mhz)) != 0) 1316 tmp1++; 1317 /* pi_tdfi_calvl_strobe=tds_train+5 */ 1318 tmp = tmp1 + 5; 1319 mmio_clrsetbits_32(PI_REG(i, 111), 0xf << 16, 1320 tmp << 16); 1321 /* PI_116 PI_TCKEHDQS_F1:RW:24:6 */ 1322 tmp = 10000 / (1000000 / pdram_timing->mhz); 1323 if ((10000 % (1000000 / pdram_timing->mhz)) != 0) 1324 tmp++; 1325 if (pdram_timing->mhz <= 100) 1326 tmp = tmp + 1; 1327 else 1328 tmp = tmp + 8; 1329 mmio_clrsetbits_32(PI_REG(i, 116), 0x3f << 24, 1330 tmp << 24); 1331 /* PI_128 PI_MR1_DATA_F1_0:RW+:0:16 */ 1332 mmio_clrsetbits_32(PI_REG(i, 128), 0xffff, pdram_timing->mr[1]); 1333 /* PI_135 PI_MR1_DATA_F1_1:RW+:8:16 */ 1334 mmio_clrsetbits_32(PI_REG(i, 135), 0xffff << 8, 1335 pdram_timing->mr[1] << 8); 1336 /* PI_143 PI_MR1_DATA_F1_2:RW+:0:16 */ 1337 mmio_clrsetbits_32(PI_REG(i, 143), 0xffff, pdram_timing->mr[1]); 1338 /* PI_150 PI_MR1_DATA_F1_3:RW+:8:16 */ 1339 mmio_clrsetbits_32(PI_REG(i, 150), 0xffff << 8, 1340 pdram_timing->mr[1] << 8); 1341 /* PI_128 PI_MR2_DATA_F1_0:RW+:16:16 */ 1342 mmio_clrsetbits_32(PI_REG(i, 128), 0xffff << 16, 1343 pdram_timing->mr[2] << 16); 1344 /* PI_136 PI_MR2_DATA_F1_1:RW+:0:16 */ 1345 mmio_clrsetbits_32(PI_REG(i, 136), 0xffff, pdram_timing->mr[2]); 1346 /* PI_143 PI_MR2_DATA_F1_2:RW+:16:16 */ 1347 mmio_clrsetbits_32(PI_REG(i, 143), 0xffff << 16, 1348 pdram_timing->mr[2] << 16); 1349 /* PI_151 PI_MR2_DATA_F1_3:RW+:0:16 */ 1350 mmio_clrsetbits_32(PI_REG(i, 151), 0xffff, pdram_timing->mr[2]); 1351 /* PI_156 PI_TFC_F1:RW:16:10 */ 1352 mmio_clrsetbits_32(PI_REG(i, 156), 0x3ff << 16, 1353 pdram_timing->trfc << 16); 1354 /* PI_162 PI_TWR_F1:RW:8:6 */ 1355 mmio_clrsetbits_32(PI_REG(i, 162), 0x3f << 8, 1356 pdram_timing->twr << 8); 1357 /* PI_162 PI_TWTR_F1:RW:0:6 */ 1358 mmio_clrsetbits_32(PI_REG(i, 162), 0x3f, pdram_timing->twtr); 1359 /* PI_161 PI_TRCD_F1:RW:24:8 */ 1360 mmio_clrsetbits_32(PI_REG(i, 161), 0xff << 24, 1361 pdram_timing->trcd << 24); 1362 /* PI_161 PI_TRP_F1:RW:16:8 */ 1363 mmio_clrsetbits_32(PI_REG(i, 161), 0xff << 16, 1364 pdram_timing->trp << 16); 1365 /* PI_161 PI_TRTP_F1:RW:8:8 */ 1366 mmio_clrsetbits_32(PI_REG(i, 161), 0xff << 8, 1367 pdram_timing->trtp << 8); 1368 /* PI_163 PI_TRAS_MIN_F1:RW:24:8 */ 1369 mmio_clrsetbits_32(PI_REG(i, 163), 0xff << 24, 1370 pdram_timing->tras_min << 24); 1371 /* PI_163 PI_TRAS_MAX_F1:RW:0:17 */ 1372 mmio_clrsetbits_32(PI_REG(i, 163), 0x1ffff, 1373 pdram_timing->tras_max * 99 / 100); 1374 /* PI_164 PI_TMRD_F1:RW:16:6 */ 1375 mmio_clrsetbits_32(PI_REG(i, 164), 0x3f << 16, 1376 pdram_timing->tmrd << 16); 1377 /* PI_164 PI_TDQSCK_MAX_F1:RW:0:4 */ 1378 mmio_clrsetbits_32(PI_REG(i, 164), 0xf, 1379 pdram_timing->tdqsck_max); 1380 /* PI_189 PI_TDFI_CTRLUPD_MAX_F1:RW:0:16 */ 1381 mmio_clrsetbits_32(PI_REG(i, 189), 0xffff, 1382 2 * pdram_timing->trefi); 1383 /* PI_190 PI_TDFI_CTRLUPD_INTERVAL_F1:RW:0:32 */ 1384 mmio_clrsetbits_32(PI_REG(i, 190), 0xffffffff, 1385 20 * pdram_timing->trefi); 1386 } 1387 } 1388 1389 static void gen_rk3399_pi_params(struct timing_related_config *timing_config, 1390 struct dram_timing_t *pdram_timing, 1391 uint32_t fn) 1392 { 1393 if (fn == 0) 1394 gen_rk3399_pi_params_f0(timing_config, pdram_timing); 1395 else 1396 gen_rk3399_pi_params_f1(timing_config, pdram_timing); 1397 } 1398 1399 static void gen_rk3399_set_odt(uint32_t odt_en) 1400 { 1401 uint32_t drv_odt_val; 1402 uint32_t i; 1403 1404 for (i = 0; i < rk3399_dram_status.timing_config.ch_cnt; i++) { 1405 drv_odt_val = (odt_en | (0 << 1) | (0 << 2)) << 16; 1406 mmio_clrsetbits_32(PHY_REG(i, 5), 0x7 << 16, drv_odt_val); 1407 mmio_clrsetbits_32(PHY_REG(i, 133), 0x7 << 16, drv_odt_val); 1408 mmio_clrsetbits_32(PHY_REG(i, 261), 0x7 << 16, drv_odt_val); 1409 mmio_clrsetbits_32(PHY_REG(i, 389), 0x7 << 16, drv_odt_val); 1410 drv_odt_val = (odt_en | (0 << 1) | (0 << 2)) << 24; 1411 mmio_clrsetbits_32(PHY_REG(i, 6), 0x7 << 24, drv_odt_val); 1412 mmio_clrsetbits_32(PHY_REG(i, 134), 0x7 << 24, drv_odt_val); 1413 mmio_clrsetbits_32(PHY_REG(i, 262), 0x7 << 24, drv_odt_val); 1414 mmio_clrsetbits_32(PHY_REG(i, 390), 0x7 << 24, drv_odt_val); 1415 } 1416 } 1417 1418 static void gen_rk3399_phy_dll_bypass(uint32_t mhz, uint32_t ch, 1419 uint32_t index, uint32_t dram_type) 1420 { 1421 uint32_t sw_master_mode = 0; 1422 uint32_t rddqs_gate_delay, rddqs_latency, total_delay; 1423 uint32_t i; 1424 1425 if (dram_type == DDR3) 1426 total_delay = PI_PAD_DELAY_PS_VALUE; 1427 else if (dram_type == LPDDR3) 1428 total_delay = PI_PAD_DELAY_PS_VALUE + 2500; 1429 else 1430 total_delay = PI_PAD_DELAY_PS_VALUE + 1500; 1431 /* total_delay + 0.55tck */ 1432 total_delay += (55 * 10000)/mhz; 1433 rddqs_latency = total_delay * mhz / 1000000; 1434 total_delay -= rddqs_latency * 1000000 / mhz; 1435 rddqs_gate_delay = total_delay * 0x200 * mhz / 1000000; 1436 if (mhz <= PHY_DLL_BYPASS_FREQ) { 1437 sw_master_mode = 0xc; 1438 mmio_setbits_32(PHY_REG(ch, 514), 1); 1439 mmio_setbits_32(PHY_REG(ch, 642), 1); 1440 mmio_setbits_32(PHY_REG(ch, 770), 1); 1441 1442 /* setting bypass mode slave delay */ 1443 for (i = 0; i < 4; i++) { 1444 /* wr dq delay = -180deg + (0x60 / 4) * 20ps */ 1445 mmio_clrsetbits_32(PHY_REG(ch, 1 + 128 * i), 0x7ff << 8, 1446 0x4a0 << 8); 1447 /* rd dqs/dq delay = (0x60 / 4) * 20ps */ 1448 mmio_clrsetbits_32(PHY_REG(ch, 11 + 128 * i), 0x3ff, 1449 0xa0); 1450 /* rd rddqs_gate delay */ 1451 mmio_clrsetbits_32(PHY_REG(ch, 2 + 128 * i), 0x3ff, 1452 rddqs_gate_delay); 1453 mmio_clrsetbits_32(PHY_REG(ch, 78 + 128 * i), 0xf, 1454 rddqs_latency); 1455 } 1456 for (i = 0; i < 3; i++) 1457 /* adr delay */ 1458 mmio_clrsetbits_32(PHY_REG(ch, 513 + 128 * i), 1459 0x7ff << 16, 0x80 << 16); 1460 1461 if ((mmio_read_32(PHY_REG(ch, 86)) & 0xc00) == 0) { 1462 /* 1463 * old status is normal mode, 1464 * and saving the wrdqs slave delay 1465 */ 1466 for (i = 0; i < 4; i++) { 1467 /* save and clear wr dqs slave delay */ 1468 wrdqs_delay_val[ch][index][i] = 0x3ff & 1469 (mmio_read_32(PHY_REG(ch, 63 + i * 128)) 1470 >> 16); 1471 mmio_clrsetbits_32(PHY_REG(ch, 63 + i * 128), 1472 0x03ff << 16, 0 << 16); 1473 /* 1474 * in normal mode the cmd may delay 1cycle by 1475 * wrlvl and in bypass mode making dqs also 1476 * delay 1cycle. 1477 */ 1478 mmio_clrsetbits_32(PHY_REG(ch, 78 + i * 128), 1479 0x07 << 8, 0x1 << 8); 1480 } 1481 } 1482 } else if (mmio_read_32(PHY_REG(ch, 86)) & 0xc00) { 1483 /* old status is bypass mode and restore wrlvl resume */ 1484 for (i = 0; i < 4; i++) { 1485 mmio_clrsetbits_32(PHY_REG(ch, 63 + i * 128), 1486 0x03ff << 16, 1487 (wrdqs_delay_val[ch][index][i] & 1488 0x3ff) << 16); 1489 /* resume phy_write_path_lat_add */ 1490 mmio_clrbits_32(PHY_REG(ch, 78 + i * 128), 0x07 << 8); 1491 } 1492 } 1493 1494 /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */ 1495 mmio_clrsetbits_32(PHY_REG(ch, 86), 0xf << 8, sw_master_mode << 8); 1496 mmio_clrsetbits_32(PHY_REG(ch, 214), 0xf << 8, sw_master_mode << 8); 1497 mmio_clrsetbits_32(PHY_REG(ch, 342), 0xf << 8, sw_master_mode << 8); 1498 mmio_clrsetbits_32(PHY_REG(ch, 470), 0xf << 8, sw_master_mode << 8); 1499 1500 /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */ 1501 mmio_clrsetbits_32(PHY_REG(ch, 547), 0xf << 16, sw_master_mode << 16); 1502 mmio_clrsetbits_32(PHY_REG(ch, 675), 0xf << 16, sw_master_mode << 16); 1503 mmio_clrsetbits_32(PHY_REG(ch, 803), 0xf << 16, sw_master_mode << 16); 1504 } 1505 1506 static void gen_rk3399_phy_params(struct timing_related_config *timing_config, 1507 struct drv_odt_lp_config *drv_config, 1508 struct dram_timing_t *pdram_timing, 1509 uint32_t fn) 1510 { 1511 uint32_t tmp, i, div, j; 1512 uint32_t mem_delay_ps, pad_delay_ps, total_delay_ps, delay_frac_ps; 1513 uint32_t trpre_min_ps, gate_delay_ps, gate_delay_frac_ps; 1514 uint32_t ie_enable, tsel_enable, cas_lat, rddata_en_ie_dly, tsel_adder; 1515 uint32_t extra_adder, delta, hs_offset; 1516 1517 for (i = 0; i < timing_config->ch_cnt; i++) { 1518 1519 pad_delay_ps = PI_PAD_DELAY_PS_VALUE; 1520 ie_enable = PI_IE_ENABLE_VALUE; 1521 tsel_enable = PI_TSEL_ENABLE_VALUE; 1522 1523 mmio_clrsetbits_32(PHY_REG(i, 896), (0x3 << 8) | 1, fn << 8); 1524 1525 /* PHY_LOW_FREQ_SEL */ 1526 /* DENALI_PHY_913 1bit offset_0 */ 1527 if (timing_config->freq > 400) 1528 mmio_clrbits_32(PHY_REG(i, 913), 1); 1529 else 1530 mmio_setbits_32(PHY_REG(i, 913), 1); 1531 1532 /* PHY_RPTR_UPDATE_x */ 1533 /* DENALI_PHY_87/215/343/471 4bit offset_16 */ 1534 tmp = 2500 / (1000000 / pdram_timing->mhz) + 3; 1535 if ((2500 % (1000000 / pdram_timing->mhz)) != 0) 1536 tmp++; 1537 mmio_clrsetbits_32(PHY_REG(i, 87), 0xf << 16, tmp << 16); 1538 mmio_clrsetbits_32(PHY_REG(i, 215), 0xf << 16, tmp << 16); 1539 mmio_clrsetbits_32(PHY_REG(i, 343), 0xf << 16, tmp << 16); 1540 mmio_clrsetbits_32(PHY_REG(i, 471), 0xf << 16, tmp << 16); 1541 1542 /* PHY_PLL_CTRL */ 1543 /* DENALI_PHY_911 13bits offset_0 */ 1544 /* PHY_LP4_BOOT_PLL_CTRL */ 1545 /* DENALI_PHY_919 13bits offset_0 */ 1546 if (pdram_timing->mhz <= 150) 1547 tmp = 3; 1548 else if (pdram_timing->mhz <= 300) 1549 tmp = 2; 1550 else if (pdram_timing->mhz <= 600) 1551 tmp = 1; 1552 else 1553 tmp = 0; 1554 tmp = (1 << 12) | (tmp << 9) | (2 << 7) | (1 << 1); 1555 mmio_clrsetbits_32(PHY_REG(i, 911), 0x1fff, tmp); 1556 mmio_clrsetbits_32(PHY_REG(i, 919), 0x1fff, tmp); 1557 1558 /* PHY_PLL_CTRL_CA */ 1559 /* DENALI_PHY_911 13bits offset_16 */ 1560 /* PHY_LP4_BOOT_PLL_CTRL_CA */ 1561 /* DENALI_PHY_919 13bits offset_16 */ 1562 if (pdram_timing->mhz <= 150) 1563 tmp = 3; 1564 else if (pdram_timing->mhz <= 300) 1565 tmp = 2; 1566 else if (pdram_timing->mhz <= 600) 1567 tmp = 1; 1568 else 1569 tmp = 0; 1570 tmp = (tmp << 9) | (2 << 7) | (1 << 5) | (1 << 1); 1571 mmio_clrsetbits_32(PHY_REG(i, 911), 0x1fff << 16, tmp << 16); 1572 mmio_clrsetbits_32(PHY_REG(i, 919), 0x1fff << 16, tmp << 16); 1573 1574 /* PHY_TCKSRE_WAIT */ 1575 /* DENALI_PHY_922 4bits offset_24 */ 1576 if (pdram_timing->mhz <= 400) 1577 tmp = 1; 1578 else if (pdram_timing->mhz <= 800) 1579 tmp = 3; 1580 else if (pdram_timing->mhz <= 1000) 1581 tmp = 4; 1582 else 1583 tmp = 5; 1584 mmio_clrsetbits_32(PHY_REG(i, 922), 0xf << 24, tmp << 24); 1585 /* PHY_CAL_CLK_SELECT_0:RW8:3 */ 1586 div = pdram_timing->mhz / (2 * 20); 1587 for (j = 2, tmp = 1; j <= 128; j <<= 1, tmp++) { 1588 if (div < j) 1589 break; 1590 } 1591 mmio_clrsetbits_32(PHY_REG(i, 947), 0x7 << 8, tmp << 8); 1592 mmio_setbits_32(PHY_REG(i, 927), (1 << 22)); 1593 1594 if (timing_config->dram_type == DDR3) { 1595 mem_delay_ps = 0; 1596 trpre_min_ps = 1000; 1597 } else if (timing_config->dram_type == LPDDR4) { 1598 mem_delay_ps = 1500; 1599 trpre_min_ps = 900; 1600 } else if (timing_config->dram_type == LPDDR3) { 1601 mem_delay_ps = 2500; 1602 trpre_min_ps = 900; 1603 } else { 1604 ERROR("gen_rk3399_phy_params:dramtype unsupport\n"); 1605 return; 1606 } 1607 total_delay_ps = mem_delay_ps + pad_delay_ps; 1608 delay_frac_ps = 1000 * total_delay_ps / 1609 (1000000 / pdram_timing->mhz); 1610 gate_delay_ps = delay_frac_ps + 1000 - (trpre_min_ps / 2); 1611 gate_delay_frac_ps = gate_delay_ps % 1000; 1612 tmp = gate_delay_frac_ps * 0x200 / 1000; 1613 /* PHY_RDDQS_GATE_SLAVE_DELAY */ 1614 /* DENALI_PHY_77/205/333/461 10bits offset_16 */ 1615 mmio_clrsetbits_32(PHY_REG(i, 77), 0x2ff << 16, tmp << 16); 1616 mmio_clrsetbits_32(PHY_REG(i, 205), 0x2ff << 16, tmp << 16); 1617 mmio_clrsetbits_32(PHY_REG(i, 333), 0x2ff << 16, tmp << 16); 1618 mmio_clrsetbits_32(PHY_REG(i, 461), 0x2ff << 16, tmp << 16); 1619 1620 tmp = gate_delay_ps / 1000; 1621 /* PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST */ 1622 /* DENALI_PHY_10/138/266/394 4bit offset_0 */ 1623 mmio_clrsetbits_32(PHY_REG(i, 10), 0xf, tmp); 1624 mmio_clrsetbits_32(PHY_REG(i, 138), 0xf, tmp); 1625 mmio_clrsetbits_32(PHY_REG(i, 266), 0xf, tmp); 1626 mmio_clrsetbits_32(PHY_REG(i, 394), 0xf, tmp); 1627 /* PHY_GTLVL_LAT_ADJ_START */ 1628 /* DENALI_PHY_80/208/336/464 4bits offset_16 */ 1629 tmp = delay_frac_ps / 1000; 1630 mmio_clrsetbits_32(PHY_REG(i, 80), 0xf << 16, tmp << 16); 1631 mmio_clrsetbits_32(PHY_REG(i, 208), 0xf << 16, tmp << 16); 1632 mmio_clrsetbits_32(PHY_REG(i, 336), 0xf << 16, tmp << 16); 1633 mmio_clrsetbits_32(PHY_REG(i, 464), 0xf << 16, tmp << 16); 1634 1635 cas_lat = pdram_timing->cl + PI_ADD_LATENCY; 1636 rddata_en_ie_dly = ie_enable / (1000000 / pdram_timing->mhz); 1637 if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0) 1638 rddata_en_ie_dly++; 1639 rddata_en_ie_dly = rddata_en_ie_dly - 1; 1640 tsel_adder = tsel_enable / (1000000 / pdram_timing->mhz); 1641 if ((tsel_enable % (1000000 / pdram_timing->mhz)) != 0) 1642 tsel_adder++; 1643 if (rddata_en_ie_dly > tsel_adder) 1644 extra_adder = rddata_en_ie_dly - tsel_adder; 1645 else 1646 extra_adder = 0; 1647 delta = cas_lat - rddata_en_ie_dly; 1648 if (PI_REGS_DIMM_SUPPORT && PI_DOUBLEFREEK) 1649 hs_offset = 2; 1650 else 1651 hs_offset = 1; 1652 if (rddata_en_ie_dly > (cas_lat - 1 - hs_offset)) 1653 tmp = 0; 1654 else if ((delta == 2) || (delta == 1)) 1655 tmp = rddata_en_ie_dly - 0 - extra_adder; 1656 else 1657 tmp = extra_adder; 1658 /* PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY */ 1659 /* DENALI_PHY_9/137/265/393 4bit offset_16 */ 1660 mmio_clrsetbits_32(PHY_REG(i, 9), 0xf << 16, tmp << 16); 1661 mmio_clrsetbits_32(PHY_REG(i, 137), 0xf << 16, tmp << 16); 1662 mmio_clrsetbits_32(PHY_REG(i, 265), 0xf << 16, tmp << 16); 1663 mmio_clrsetbits_32(PHY_REG(i, 393), 0xf << 16, tmp << 16); 1664 /* PHY_RDDATA_EN_TSEL_DLY */ 1665 /* DENALI_PHY_86/214/342/470 4bit offset_0 */ 1666 mmio_clrsetbits_32(PHY_REG(i, 86), 0xf, tmp); 1667 mmio_clrsetbits_32(PHY_REG(i, 214), 0xf, tmp); 1668 mmio_clrsetbits_32(PHY_REG(i, 342), 0xf, tmp); 1669 mmio_clrsetbits_32(PHY_REG(i, 470), 0xf, tmp); 1670 1671 if (tsel_adder > rddata_en_ie_dly) 1672 extra_adder = tsel_adder - rddata_en_ie_dly; 1673 else 1674 extra_adder = 0; 1675 if (rddata_en_ie_dly > (cas_lat - 1 - hs_offset)) 1676 tmp = tsel_adder; 1677 else 1678 tmp = rddata_en_ie_dly - 0 + extra_adder; 1679 /* PHY_LP4_BOOT_RDDATA_EN_DLY */ 1680 /* DENALI_PHY_9/137/265/393 4bit offset_8 */ 1681 mmio_clrsetbits_32(PHY_REG(i, 9), 0xf << 8, tmp << 8); 1682 mmio_clrsetbits_32(PHY_REG(i, 137), 0xf << 8, tmp << 8); 1683 mmio_clrsetbits_32(PHY_REG(i, 265), 0xf << 8, tmp << 8); 1684 mmio_clrsetbits_32(PHY_REG(i, 393), 0xf << 8, tmp << 8); 1685 /* PHY_RDDATA_EN_DLY */ 1686 /* DENALI_PHY_85/213/341/469 4bit offset_24 */ 1687 mmio_clrsetbits_32(PHY_REG(i, 85), 0xf << 24, tmp << 24); 1688 mmio_clrsetbits_32(PHY_REG(i, 213), 0xf << 24, tmp << 24); 1689 mmio_clrsetbits_32(PHY_REG(i, 341), 0xf << 24, tmp << 24); 1690 mmio_clrsetbits_32(PHY_REG(i, 469), 0xf << 24, tmp << 24); 1691 1692 if (pdram_timing->mhz <= ENPER_CS_TRAINING_FREQ) { 1693 /* 1694 * Note:Per-CS Training is not compatible at speeds 1695 * under 533 MHz. If the PHY is running at a speed 1696 * less than 533MHz, all phy_per_cs_training_en_X 1697 * parameters must be cleared to 0. 1698 */ 1699 1700 /*DENALI_PHY_84/212/340/468 1bit offset_16 */ 1701 mmio_clrbits_32(PHY_REG(i, 84), 0x1 << 16); 1702 mmio_clrbits_32(PHY_REG(i, 212), 0x1 << 16); 1703 mmio_clrbits_32(PHY_REG(i, 340), 0x1 << 16); 1704 mmio_clrbits_32(PHY_REG(i, 468), 0x1 << 16); 1705 } else { 1706 mmio_setbits_32(PHY_REG(i, 84), 0x1 << 16); 1707 mmio_setbits_32(PHY_REG(i, 212), 0x1 << 16); 1708 mmio_setbits_32(PHY_REG(i, 340), 0x1 << 16); 1709 mmio_setbits_32(PHY_REG(i, 468), 0x1 << 16); 1710 } 1711 gen_rk3399_phy_dll_bypass(pdram_timing->mhz, i, fn, 1712 timing_config->dram_type); 1713 } 1714 } 1715 1716 static int to_get_clk_index(unsigned int mhz) 1717 { 1718 int pll_cnt, i; 1719 1720 pll_cnt = ARRAY_SIZE(dpll_rates_table); 1721 1722 /* Assumming rate_table is in descending order */ 1723 for (i = 0; i < pll_cnt; i++) { 1724 if (mhz >= dpll_rates_table[i].mhz) 1725 break; 1726 } 1727 1728 /* if mhz lower than lowest frequency in table, use lowest frequency */ 1729 if (i == pll_cnt) 1730 i = pll_cnt - 1; 1731 1732 return i; 1733 } 1734 1735 uint32_t ddr_get_rate(void) 1736 { 1737 uint32_t refdiv, postdiv1, fbdiv, postdiv2; 1738 1739 refdiv = mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1)) & 0x3f; 1740 fbdiv = mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 0)) & 0xfff; 1741 postdiv1 = 1742 (mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1)) >> 8) & 0x7; 1743 postdiv2 = 1744 (mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1)) >> 12) & 0x7; 1745 1746 return (24 / refdiv * fbdiv / postdiv1 / postdiv2) * 1000 * 1000; 1747 } 1748 1749 /* 1750 * return: bit12: channel 1, external self-refresh 1751 * bit11: channel 1, stdby_mode 1752 * bit10: channel 1, self-refresh with controller and memory clock gate 1753 * bit9: channel 1, self-refresh 1754 * bit8: channel 1, power-down 1755 * 1756 * bit4: channel 1, external self-refresh 1757 * bit3: channel 0, stdby_mode 1758 * bit2: channel 0, self-refresh with controller and memory clock gate 1759 * bit1: channel 0, self-refresh 1760 * bit0: channel 0, power-down 1761 */ 1762 uint32_t exit_low_power(void) 1763 { 1764 uint32_t low_power = 0; 1765 uint32_t channel_mask; 1766 uint32_t tmp, i; 1767 1768 channel_mask = (mmio_read_32(PMUGRF_BASE + PMUGRF_OSREG(2)) >> 28) & 1769 0x3; 1770 for (i = 0; i < 2; i++) { 1771 if (!(channel_mask & (1 << i))) 1772 continue; 1773 1774 /* exit stdby mode */ 1775 mmio_write_32(CIC_BASE + CIC_CTRL1, 1776 (1 << (i + 16)) | (0 << i)); 1777 /* exit external self-refresh */ 1778 tmp = i ? 12 : 8; 1779 low_power |= ((mmio_read_32(PMU_BASE + PMU_SFT_CON) >> tmp) & 1780 0x1) << (4 + 8 * i); 1781 mmio_clrbits_32(PMU_BASE + PMU_SFT_CON, 1 << tmp); 1782 while (!(mmio_read_32(PMU_BASE + PMU_DDR_SREF_ST) & (1 << i))) 1783 ; 1784 /* exit auto low-power */ 1785 mmio_clrbits_32(CTL_REG(i, 101), 0x7); 1786 /* lp_cmd to exit */ 1787 if (((mmio_read_32(CTL_REG(i, 100)) >> 24) & 0x7f) != 1788 0x40) { 1789 while (mmio_read_32(CTL_REG(i, 200)) & 0x1) 1790 ; 1791 mmio_clrsetbits_32(CTL_REG(i, 93), 0xff << 24, 1792 0x69 << 24); 1793 while (((mmio_read_32(CTL_REG(i, 100)) >> 24) & 0x7f) != 1794 0x40) 1795 ; 1796 } 1797 } 1798 return low_power; 1799 } 1800 1801 void resume_low_power(uint32_t low_power) 1802 { 1803 uint32_t channel_mask; 1804 uint32_t tmp, i, val; 1805 1806 channel_mask = (mmio_read_32(PMUGRF_BASE + PMUGRF_OSREG(2)) >> 28) & 1807 0x3; 1808 for (i = 0; i < 2; i++) { 1809 if (!(channel_mask & (1 << i))) 1810 continue; 1811 1812 /* resume external self-refresh */ 1813 tmp = i ? 12 : 8; 1814 val = (low_power >> (4 + 8 * i)) & 0x1; 1815 mmio_setbits_32(PMU_BASE + PMU_SFT_CON, val << tmp); 1816 /* resume auto low-power */ 1817 val = (low_power >> (8 * i)) & 0x7; 1818 mmio_setbits_32(CTL_REG(i, 101), val); 1819 /* resume stdby mode */ 1820 val = (low_power >> (3 + 8 * i)) & 0x1; 1821 mmio_write_32(CIC_BASE + CIC_CTRL1, 1822 (1 << (i + 16)) | (val << i)); 1823 } 1824 } 1825 1826 static void dram_low_power_config(void) 1827 { 1828 uint32_t tmp, i; 1829 uint32_t ch_cnt = rk3399_dram_status.timing_config.ch_cnt; 1830 uint32_t dram_type = rk3399_dram_status.timing_config.dram_type; 1831 1832 if (dram_type == DDR3) 1833 tmp = (2 << 16) | (0x7 << 8); 1834 else 1835 tmp = (3 << 16) | (0x7 << 8); 1836 1837 for (i = 0; i < ch_cnt; i++) 1838 mmio_clrsetbits_32(CTL_REG(i, 101), 0x70f0f, tmp); 1839 1840 /* standby idle */ 1841 mmio_write_32(CIC_BASE + CIC_CG_WAIT_TH, 0x640008); 1842 1843 if (ch_cnt == 2) { 1844 mmio_write_32(GRF_BASE + GRF_DDRC1_CON1, 1845 (((0x1<<4) | (0x1<<5) | (0x1<<6) | 1846 (0x1<<7)) << 16) | 1847 ((0x1<<4) | (0x0<<5) | (0x1<<6) | (0x1<<7))); 1848 mmio_write_32(CIC_BASE + CIC_CTRL1, 0x002a0028); 1849 } 1850 1851 mmio_write_32(GRF_BASE + GRF_DDRC0_CON1, 1852 (((0x1<<4) | (0x1<<5) | (0x1<<6) | (0x1<<7)) << 16) | 1853 ((0x1<<4) | (0x0<<5) | (0x1<<6) | (0x1<<7))); 1854 mmio_write_32(CIC_BASE + CIC_CTRL1, 0x00150014); 1855 } 1856 1857 void dram_dfs_init(void) 1858 { 1859 uint32_t trefi0, trefi1, boot_freq; 1860 1861 /* get sdram config for os reg */ 1862 get_dram_drv_odt_val(sdram_config.dramtype, 1863 &rk3399_dram_status.drv_odt_lp_cfg); 1864 sdram_timing_cfg_init(&rk3399_dram_status.timing_config, 1865 &sdram_config, 1866 &rk3399_dram_status.drv_odt_lp_cfg); 1867 1868 trefi0 = ((mmio_read_32(CTL_REG(0, 48)) >> 16) & 0xffff) + 8; 1869 trefi1 = ((mmio_read_32(CTL_REG(0, 49)) >> 16) & 0xffff) + 8; 1870 1871 rk3399_dram_status.index_freq[0] = trefi0 * 10 / 39; 1872 rk3399_dram_status.index_freq[1] = trefi1 * 10 / 39; 1873 rk3399_dram_status.current_index = 1874 (mmio_read_32(CTL_REG(0, 111)) >> 16) & 0x3; 1875 if (rk3399_dram_status.timing_config.dram_type == DDR3) { 1876 rk3399_dram_status.index_freq[0] /= 2; 1877 rk3399_dram_status.index_freq[1] /= 2; 1878 } 1879 boot_freq = 1880 rk3399_dram_status.index_freq[rk3399_dram_status.current_index]; 1881 boot_freq = dpll_rates_table[to_get_clk_index(boot_freq)].mhz; 1882 rk3399_dram_status.boot_freq = boot_freq; 1883 rk3399_dram_status.index_freq[rk3399_dram_status.current_index] = 1884 boot_freq; 1885 rk3399_dram_status.index_freq[(rk3399_dram_status.current_index + 1) & 1886 0x1] = 0; 1887 rk3399_dram_status.low_power_stat = 0; 1888 /* 1889 * following register decide if NOC stall the access request 1890 * or return error when NOC being idled. when doing ddr frequency 1891 * scaling in M0 or DCF, we need to make sure noc stall the access 1892 * request, if return error cpu may data abort when ddr frequency 1893 * changing. it don't need to set this register every times, 1894 * so we init this register in function dram_dfs_init(). 1895 */ 1896 mmio_write_32(GRF_BASE + GRF_SOC_CON(0), 0xffffffff); 1897 mmio_write_32(GRF_BASE + GRF_SOC_CON(1), 0xffffffff); 1898 mmio_write_32(GRF_BASE + GRF_SOC_CON(2), 0xffffffff); 1899 mmio_write_32(GRF_BASE + GRF_SOC_CON(3), 0xffffffff); 1900 mmio_write_32(GRF_BASE + GRF_SOC_CON(4), 0x70007000); 1901 1902 /* Disable multicast */ 1903 mmio_clrbits_32(PHY_REG(0, 896), 1); 1904 mmio_clrbits_32(PHY_REG(1, 896), 1); 1905 1906 dram_low_power_config(); 1907 } 1908 1909 /* 1910 * arg0: bit0-7: sr_idle; bit8-15:sr_mc_gate_idle; bit16-31: standby idle 1911 * arg1: bit0-11: pd_idle; bit 16-27: srpd_lite_idle 1912 * arg2: bit0: if odt en 1913 */ 1914 uint32_t dram_set_odt_pd(uint32_t arg0, uint32_t arg1, uint32_t arg2) 1915 { 1916 struct drv_odt_lp_config *lp_cfg = &rk3399_dram_status.drv_odt_lp_cfg; 1917 uint32_t *low_power = &rk3399_dram_status.low_power_stat; 1918 uint32_t dram_type, ch_count, pd_tmp, sr_tmp, i; 1919 1920 dram_type = rk3399_dram_status.timing_config.dram_type; 1921 ch_count = rk3399_dram_status.timing_config.ch_cnt; 1922 1923 lp_cfg->sr_idle = arg0 & 0xff; 1924 lp_cfg->sr_mc_gate_idle = (arg0 >> 8) & 0xff; 1925 lp_cfg->standby_idle = (arg0 >> 16) & 0xffff; 1926 lp_cfg->pd_idle = arg1 & 0xfff; 1927 lp_cfg->srpd_lite_idle = (arg1 >> 16) & 0xfff; 1928 1929 rk3399_dram_status.timing_config.odt = arg2 & 0x1; 1930 1931 exit_low_power(); 1932 1933 *low_power = 0; 1934 1935 /* pd_idle en */ 1936 if (lp_cfg->pd_idle) 1937 *low_power |= ((1 << 0) | (1 << 8)); 1938 /* sr_idle en srpd_lite_idle */ 1939 if (lp_cfg->sr_idle | lp_cfg->srpd_lite_idle) 1940 *low_power |= ((1 << 1) | (1 << 9)); 1941 /* sr_mc_gate_idle */ 1942 if (lp_cfg->sr_mc_gate_idle) 1943 *low_power |= ((1 << 2) | (1 << 10)); 1944 /* standbyidle */ 1945 if (lp_cfg->standby_idle) { 1946 if (rk3399_dram_status.timing_config.ch_cnt == 2) 1947 *low_power |= ((1 << 3) | (1 << 11)); 1948 else 1949 *low_power |= (1 << 3); 1950 } 1951 1952 pd_tmp = arg1; 1953 if (dram_type != LPDDR4) 1954 pd_tmp = arg1 & 0xfff; 1955 sr_tmp = arg0 & 0xffff; 1956 for (i = 0; i < ch_count; i++) { 1957 mmio_write_32(CTL_REG(i, 102), pd_tmp); 1958 mmio_clrsetbits_32(CTL_REG(i, 103), 0xffff, sr_tmp); 1959 } 1960 mmio_write_32(CIC_BASE + CIC_IDLE_TH, (arg0 >> 16) & 0xffff); 1961 1962 return 0; 1963 } 1964 1965 static void m0_configure_ddr(struct pll_div pll_div, uint32_t ddr_index) 1966 { 1967 /* set PARAM to M0_FUNC_DRAM */ 1968 mmio_write_32(M0_PARAM_ADDR + PARAM_M0_FUNC, M0_FUNC_DRAM); 1969 1970 mmio_write_32(M0_PARAM_ADDR + PARAM_DPLL_CON0, FBDIV(pll_div.fbdiv)); 1971 mmio_write_32(M0_PARAM_ADDR + PARAM_DPLL_CON1, 1972 POSTDIV2(pll_div.postdiv2) | POSTDIV1(pll_div.postdiv1) | 1973 REFDIV(pll_div.refdiv)); 1974 1975 mmio_write_32(M0_PARAM_ADDR + PARAM_DRAM_FREQ, pll_div.mhz); 1976 1977 mmio_write_32(M0_PARAM_ADDR + PARAM_FREQ_SELECT, ddr_index << 4); 1978 } 1979 1980 static uint32_t prepare_ddr_timing(uint32_t mhz) 1981 { 1982 uint32_t index; 1983 struct dram_timing_t dram_timing; 1984 1985 rk3399_dram_status.timing_config.freq = mhz; 1986 1987 if (mhz < 300) 1988 rk3399_dram_status.timing_config.dllbp = 1; 1989 else 1990 rk3399_dram_status.timing_config.dllbp = 0; 1991 1992 if (rk3399_dram_status.timing_config.odt == 1) 1993 gen_rk3399_set_odt(1); 1994 1995 index = (rk3399_dram_status.current_index + 1) & 0x1; 1996 if (rk3399_dram_status.index_freq[index] == mhz) 1997 return index; 1998 1999 /* 2000 * checking if having available gate traiing timing for 2001 * target freq. 2002 */ 2003 dram_get_parameter(&rk3399_dram_status.timing_config, &dram_timing); 2004 gen_rk3399_ctl_params(&rk3399_dram_status.timing_config, 2005 &dram_timing, index); 2006 gen_rk3399_pi_params(&rk3399_dram_status.timing_config, 2007 &dram_timing, index); 2008 gen_rk3399_phy_params(&rk3399_dram_status.timing_config, 2009 &rk3399_dram_status.drv_odt_lp_cfg, 2010 &dram_timing, index); 2011 rk3399_dram_status.index_freq[index] = mhz; 2012 2013 return index; 2014 } 2015 2016 void print_dram_status_info(void) 2017 { 2018 uint32_t *p; 2019 uint32_t i; 2020 2021 p = (uint32_t *) &rk3399_dram_status.timing_config; 2022 INFO("rk3399_dram_status.timing_config:\n"); 2023 for (i = 0; i < sizeof(struct timing_related_config) / 4; i++) 2024 tf_printf("%u\n", p[i]); 2025 p = (uint32_t *) &rk3399_dram_status.drv_odt_lp_cfg; 2026 INFO("rk3399_dram_status.drv_odt_lp_cfg:\n"); 2027 for (i = 0; i < sizeof(struct drv_odt_lp_config) / 4; i++) 2028 tf_printf("%u\n", p[i]); 2029 } 2030 2031 uint32_t ddr_set_rate(uint32_t hz) 2032 { 2033 uint32_t low_power, index, ddr_index; 2034 uint32_t mhz = hz / (1000 * 1000); 2035 2036 if (mhz == 2037 rk3399_dram_status.index_freq[rk3399_dram_status.current_index]) 2038 goto out; 2039 2040 index = to_get_clk_index(mhz); 2041 mhz = dpll_rates_table[index].mhz; 2042 2043 ddr_index = prepare_ddr_timing(mhz); 2044 gen_rk3399_enable_training(rk3399_dram_status.timing_config.ch_cnt, 2045 mhz); 2046 if (ddr_index > 1) 2047 goto out; 2048 2049 m0_configure_ddr(dpll_rates_table[index], ddr_index); 2050 m0_start(); 2051 m0_wait_done(); 2052 m0_stop(); 2053 2054 if (rk3399_dram_status.timing_config.odt == 0) 2055 gen_rk3399_set_odt(0); 2056 2057 rk3399_dram_status.current_index = ddr_index; 2058 low_power = rk3399_dram_status.low_power_stat; 2059 resume_low_power(low_power); 2060 out: 2061 return mhz; 2062 } 2063 2064 uint32_t ddr_round_rate(uint32_t hz) 2065 { 2066 int index; 2067 uint32_t mhz = hz / (1000 * 1000); 2068 2069 index = to_get_clk_index(mhz); 2070 2071 return dpll_rates_table[index].mhz * 1000 * 1000; 2072 } 2073 2074 void ddr_prepare_for_sys_suspend(void) 2075 { 2076 uint32_t mhz = 2077 rk3399_dram_status.index_freq[rk3399_dram_status.current_index]; 2078 2079 /* 2080 * If we're not currently at the boot (assumed highest) frequency, we 2081 * need to change frequencies to configure out current index. 2082 */ 2083 rk3399_suspend_status.freq = mhz; 2084 exit_low_power(); 2085 rk3399_suspend_status.low_power_stat = 2086 rk3399_dram_status.low_power_stat; 2087 rk3399_suspend_status.odt = rk3399_dram_status.timing_config.odt; 2088 rk3399_dram_status.low_power_stat = 0; 2089 rk3399_dram_status.timing_config.odt = 1; 2090 if (mhz != rk3399_dram_status.boot_freq) 2091 ddr_set_rate(rk3399_dram_status.boot_freq * 1000 * 1000); 2092 2093 /* 2094 * This will configure the other index to be the same frequency as the 2095 * current one. We retrain both indices on resume, so both have to be 2096 * setup for the same frequency. 2097 */ 2098 prepare_ddr_timing(rk3399_dram_status.boot_freq); 2099 } 2100 2101 void ddr_prepare_for_sys_resume(void) 2102 { 2103 /* Disable multicast */ 2104 mmio_clrbits_32(PHY_REG(0, 896), 1); 2105 mmio_clrbits_32(PHY_REG(1, 896), 1); 2106 2107 /* The suspend code changes the current index, so reset it now. */ 2108 rk3399_dram_status.current_index = 2109 (mmio_read_32(CTL_REG(0, 111)) >> 16) & 0x3; 2110 rk3399_dram_status.low_power_stat = 2111 rk3399_suspend_status.low_power_stat; 2112 rk3399_dram_status.timing_config.odt = rk3399_suspend_status.odt; 2113 2114 /* 2115 * Set the saved frequency from suspend if it's different than the 2116 * current frequency. 2117 */ 2118 if (rk3399_suspend_status.freq != 2119 rk3399_dram_status.index_freq[rk3399_dram_status.current_index]) { 2120 ddr_set_rate(rk3399_suspend_status.freq * 1000 * 1000); 2121 return; 2122 } 2123 2124 gen_rk3399_set_odt(rk3399_dram_status.timing_config.odt); 2125 resume_low_power(rk3399_dram_status.low_power_stat); 2126 } 2127