1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <debug.h> 32 #include <mmio.h> 33 #include <plat_private.h> 34 #include "dfs.h" 35 #include "dram.h" 36 #include "dram_spec_timing.h" 37 #include "string.h" 38 #include "soc.h" 39 #include "pmu.h" 40 41 #include <delay_timer.h> 42 43 #define CTL_TRAINING (1) 44 #define PI_TRAINING (!CTL_TRAINING) 45 46 #define EN_READ_GATE_TRAINING (1) 47 #define EN_CA_TRAINING (0) 48 #define EN_WRITE_LEVELING (0) 49 #define EN_READ_LEVELING (0) 50 #define EN_WDQ_LEVELING (0) 51 52 #define ENPER_CS_TRAINING_FREQ (933) 53 54 struct pll_div { 55 unsigned int mhz; 56 unsigned int refdiv; 57 unsigned int fbdiv; 58 unsigned int postdiv1; 59 unsigned int postdiv2; 60 unsigned int frac; 61 unsigned int freq; 62 }; 63 64 static const struct pll_div dpll_rates_table[] = { 65 66 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2 */ 67 {.mhz = 933, .refdiv = 3, .fbdiv = 350, .postdiv1 = 3, .postdiv2 = 1}, 68 {.mhz = 800, .refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1}, 69 {.mhz = 732, .refdiv = 1, .fbdiv = 61, .postdiv1 = 2, .postdiv2 = 1}, 70 {.mhz = 666, .refdiv = 1, .fbdiv = 111, .postdiv1 = 4, .postdiv2 = 1}, 71 {.mhz = 600, .refdiv = 1, .fbdiv = 50, .postdiv1 = 2, .postdiv2 = 1}, 72 {.mhz = 528, .refdiv = 1, .fbdiv = 66, .postdiv1 = 3, .postdiv2 = 1}, 73 {.mhz = 400, .refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1}, 74 {.mhz = 300, .refdiv = 1, .fbdiv = 50, .postdiv1 = 4, .postdiv2 = 1}, 75 {.mhz = 200, .refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 2}, 76 }; 77 78 struct rk3399_dram_status { 79 uint32_t current_index; 80 uint32_t index_freq[2]; 81 uint32_t low_power_stat; 82 struct timing_related_config timing_config; 83 struct drv_odt_lp_config drv_odt_lp_cfg; 84 }; 85 86 static struct rk3399_dram_status rk3399_dram_status; 87 88 static struct rk3399_sdram_default_config ddr3_default_config = { 89 .bl = 8, 90 .ap = 0, 91 .burst_ref_cnt = 1, 92 .zqcsi = 0 93 }; 94 95 static struct rk3399_sdram_default_config lpddr3_default_config = { 96 .bl = 8, 97 .ap = 0, 98 .burst_ref_cnt = 1, 99 .zqcsi = 0 100 }; 101 102 static struct rk3399_sdram_default_config lpddr4_default_config = { 103 .bl = 16, 104 .ap = 0, 105 .caodt = 240, 106 .burst_ref_cnt = 1, 107 .zqcsi = 0 108 }; 109 110 uint32_t dcf_code[] = { 111 #include "dcf_code.inc" 112 }; 113 114 #define DCF_START_ADDR (SRAM_BASE + 0x1400) 115 #define DCF_PARAM_ADDR (SRAM_BASE + 0x1000) 116 117 /* DCF_PAMET */ 118 #define PARAM_DRAM_FREQ (0) 119 #define PARAM_DPLL_CON0 (4) 120 #define PARAM_DPLL_CON1 (8) 121 #define PARAM_DPLL_CON2 (0xc) 122 #define PARAM_DPLL_CON3 (0x10) 123 #define PARAM_DPLL_CON4 (0x14) 124 #define PARAM_DPLL_CON5 (0x18) 125 /* equal to fn<<4 */ 126 #define PARAM_FREQ_SELECT (0x1c) 127 128 static uint32_t get_cs_die_capability(struct rk3399_sdram_params *sdram_config, 129 uint8_t channel, uint8_t cs) 130 { 131 struct rk3399_sdram_channel *ch = &sdram_config->ch[channel]; 132 uint32_t bandwidth; 133 uint32_t die_bandwidth; 134 uint32_t die; 135 uint32_t cs_cap; 136 uint32_t row; 137 138 row = cs == 0 ? ch->cs0_row : ch->cs1_row; 139 bandwidth = 8 * (1 << ch->bw); 140 die_bandwidth = 8 * (1 << ch->dbw); 141 die = bandwidth / die_bandwidth; 142 cs_cap = (1 << (row + ((1 << ch->bk) / 4 + 1) + ch->col + 143 (bandwidth / 16))); 144 if (ch->row_3_4) 145 cs_cap = cs_cap * 3 / 4; 146 147 return (cs_cap / die); 148 } 149 150 static void get_dram_drv_odt_val(uint32_t dram_type, 151 struct drv_odt_lp_config *drv_config) 152 { 153 uint32_t tmp; 154 uint32_t mr1_val, mr3_val, mr11_val; 155 156 switch (dram_type) { 157 case DDR3: 158 mr1_val = (mmio_read_32(CTL_REG(0, 133)) >> 16) & 0xffff; 159 tmp = ((mr1_val >> 1) & 1) | ((mr1_val >> 4) & 1); 160 if (tmp) 161 drv_config->dram_side_drv = 34; 162 else 163 drv_config->dram_side_drv = 40; 164 tmp = ((mr1_val >> 2) & 1) | ((mr1_val >> 5) & 1) | 165 ((mr1_val >> 7) & 1); 166 if (tmp == 0) 167 drv_config->dram_side_dq_odt = 0; 168 else if (tmp == 1) 169 drv_config->dram_side_dq_odt = 60; 170 else if (tmp == 3) 171 drv_config->dram_side_dq_odt = 40; 172 else 173 drv_config->dram_side_dq_odt = 120; 174 break; 175 case LPDDR3: 176 mr3_val = mmio_read_32(CTL_REG(0, 138)) & 0xf; 177 mr11_val = (mmio_read_32(CTL_REG(0, 139)) >> 24) & 0x3; 178 if (mr3_val == 0xb) 179 drv_config->dram_side_drv = 3448; 180 else if (mr3_val == 0xa) 181 drv_config->dram_side_drv = 4048; 182 else if (mr3_val == 0x9) 183 drv_config->dram_side_drv = 3440; 184 else if (mr3_val == 0x4) 185 drv_config->dram_side_drv = 60; 186 else if (mr3_val == 0x3) 187 drv_config->dram_side_drv = 48; 188 else if (mr3_val == 0x2) 189 drv_config->dram_side_drv = 40; 190 else 191 drv_config->dram_side_drv = 34; 192 193 if (mr11_val == 1) 194 drv_config->dram_side_dq_odt = 60; 195 else if (mr11_val == 2) 196 drv_config->dram_side_dq_odt = 120; 197 else if (mr11_val == 0) 198 drv_config->dram_side_dq_odt = 0; 199 else 200 drv_config->dram_side_dq_odt = 240; 201 break; 202 case LPDDR4: 203 default: 204 mr3_val = (mmio_read_32(CTL_REG(0, 138)) >> 3) & 0x7; 205 mr11_val = (mmio_read_32(CTL_REG(0, 139)) >> 24) & 0xff; 206 207 if ((mr3_val == 0) || (mr3_val == 7)) 208 drv_config->dram_side_drv = 40; 209 else 210 drv_config->dram_side_drv = 240 / mr3_val; 211 212 tmp = mr11_val & 0x7; 213 if ((tmp == 7) || (tmp == 0)) 214 drv_config->dram_side_dq_odt = 0; 215 else 216 drv_config->dram_side_dq_odt = 240 / tmp; 217 218 tmp = (mr11_val >> 4) & 0x7; 219 if ((tmp == 7) || (tmp == 0)) 220 drv_config->dram_side_ca_odt = 0; 221 else 222 drv_config->dram_side_ca_odt = 240 / tmp; 223 break; 224 } 225 } 226 227 static void sdram_timing_cfg_init(struct timing_related_config *ptiming_config, 228 struct rk3399_sdram_params *sdram_params, 229 struct drv_odt_lp_config *drv_config) 230 { 231 uint32_t i, j; 232 233 for (i = 0; i < sdram_params->num_channels; i++) { 234 ptiming_config->dram_info[i].speed_rate = DDR3_DEFAULT; 235 ptiming_config->dram_info[i].cs_cnt = sdram_params->ch[i].rank; 236 for (j = 0; j < sdram_params->ch[i].rank; j++) { 237 ptiming_config->dram_info[i].per_die_capability[j] = 238 get_cs_die_capability(sdram_params, i, j); 239 } 240 } 241 ptiming_config->dram_type = sdram_params->dramtype; 242 ptiming_config->ch_cnt = sdram_params->num_channels; 243 switch (sdram_params->dramtype) { 244 case DDR3: 245 ptiming_config->bl = ddr3_default_config.bl; 246 ptiming_config->ap = ddr3_default_config.ap; 247 break; 248 case LPDDR3: 249 ptiming_config->bl = lpddr3_default_config.bl; 250 ptiming_config->ap = lpddr3_default_config.ap; 251 break; 252 case LPDDR4: 253 ptiming_config->bl = lpddr4_default_config.bl; 254 ptiming_config->ap = lpddr4_default_config.ap; 255 ptiming_config->rdbi = 0; 256 ptiming_config->wdbi = 0; 257 break; 258 } 259 ptiming_config->dramds = drv_config->dram_side_drv; 260 ptiming_config->dramodt = drv_config->dram_side_dq_odt; 261 ptiming_config->caodt = drv_config->dram_side_ca_odt; 262 } 263 264 struct lat_adj_pair { 265 uint32_t cl; 266 uint32_t rdlat_adj; 267 uint32_t cwl; 268 uint32_t wrlat_adj; 269 }; 270 271 const struct lat_adj_pair ddr3_lat_adj[] = { 272 {6, 5, 5, 4}, 273 {8, 7, 6, 5}, 274 {10, 9, 7, 6}, 275 {11, 9, 8, 7}, 276 {13, 0xb, 9, 8}, 277 {14, 0xb, 0xa, 9} 278 }; 279 280 const struct lat_adj_pair lpddr3_lat_adj[] = { 281 {3, 2, 1, 0}, 282 {6, 5, 3, 2}, 283 {8, 7, 4, 3}, 284 {9, 8, 5, 4}, 285 {10, 9, 6, 5}, 286 {11, 9, 6, 5}, 287 {12, 0xa, 6, 5}, 288 {14, 0xc, 8, 7}, 289 {16, 0xd, 8, 7} 290 }; 291 292 const struct lat_adj_pair lpddr4_lat_adj[] = { 293 {6, 5, 4, 2}, 294 {10, 9, 6, 4}, 295 {14, 0xc, 8, 6}, 296 {20, 0x11, 0xa, 8}, 297 {24, 0x15, 0xc, 0xa}, 298 {28, 0x18, 0xe, 0xc}, 299 {32, 0x1b, 0x10, 0xe}, 300 {36, 0x1e, 0x12, 0x10} 301 }; 302 303 static uint32_t get_rdlat_adj(uint32_t dram_type, uint32_t cl) 304 { 305 const struct lat_adj_pair *p; 306 uint32_t cnt; 307 uint32_t i; 308 309 if (dram_type == DDR3) { 310 p = ddr3_lat_adj; 311 cnt = ARRAY_SIZE(ddr3_lat_adj); 312 } else if (dram_type == LPDDR3) { 313 p = lpddr3_lat_adj; 314 cnt = ARRAY_SIZE(lpddr3_lat_adj); 315 } else { 316 p = lpddr4_lat_adj; 317 cnt = ARRAY_SIZE(lpddr4_lat_adj); 318 } 319 320 for (i = 0; i < cnt; i++) { 321 if (cl == p[i].cl) 322 return p[i].rdlat_adj; 323 } 324 /* fail */ 325 return 0xff; 326 } 327 328 static uint32_t get_wrlat_adj(uint32_t dram_type, uint32_t cwl) 329 { 330 const struct lat_adj_pair *p; 331 uint32_t cnt; 332 uint32_t i; 333 334 if (dram_type == DDR3) { 335 p = ddr3_lat_adj; 336 cnt = ARRAY_SIZE(ddr3_lat_adj); 337 } else if (dram_type == LPDDR3) { 338 p = lpddr3_lat_adj; 339 cnt = ARRAY_SIZE(lpddr3_lat_adj); 340 } else { 341 p = lpddr4_lat_adj; 342 cnt = ARRAY_SIZE(lpddr4_lat_adj); 343 } 344 345 for (i = 0; i < cnt; i++) { 346 if (cwl == p[i].cwl) 347 return p[i].wrlat_adj; 348 } 349 /* fail */ 350 return 0xff; 351 } 352 353 #define PI_REGS_DIMM_SUPPORT (0) 354 #define PI_ADD_LATENCY (0) 355 #define PI_DOUBLEFREEK (1) 356 357 #define PI_PAD_DELAY_PS_VALUE (1000) 358 #define PI_IE_ENABLE_VALUE (3000) 359 #define PI_TSEL_ENABLE_VALUE (700) 360 361 static uint32_t get_pi_rdlat_adj(struct dram_timing_t *pdram_timing) 362 { 363 /*[DLLSUBTYPE2] == "STD_DENALI_HS" */ 364 uint32_t rdlat, delay_adder, ie_enable, hs_offset, tsel_adder, 365 extra_adder, tsel_enable; 366 367 ie_enable = PI_IE_ENABLE_VALUE; 368 tsel_enable = PI_TSEL_ENABLE_VALUE; 369 370 rdlat = pdram_timing->cl + PI_ADD_LATENCY; 371 delay_adder = ie_enable / (1000000 / pdram_timing->mhz); 372 if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0) 373 delay_adder++; 374 hs_offset = 0; 375 tsel_adder = 0; 376 extra_adder = 0; 377 /* rdlat = rdlat - (PREAMBLE_SUPPORT & 0x1); */ 378 tsel_adder = tsel_enable / (1000000 / pdram_timing->mhz); 379 if ((tsel_enable % (1000000 / pdram_timing->mhz)) != 0) 380 tsel_adder++; 381 delay_adder = delay_adder - 1; 382 if (tsel_adder > delay_adder) 383 extra_adder = tsel_adder - delay_adder; 384 else 385 extra_adder = 0; 386 if (PI_REGS_DIMM_SUPPORT && PI_DOUBLEFREEK) 387 hs_offset = 2; 388 else 389 hs_offset = 1; 390 391 if (delay_adder > (rdlat - 1 - hs_offset)) { 392 rdlat = rdlat - tsel_adder; 393 } else { 394 if ((rdlat - delay_adder) < 2) 395 rdlat = 2; 396 else 397 rdlat = rdlat - delay_adder - extra_adder; 398 } 399 400 return rdlat; 401 } 402 403 static uint32_t get_pi_wrlat(struct dram_timing_t *pdram_timing, 404 struct timing_related_config *timing_config) 405 { 406 uint32_t tmp; 407 408 if (timing_config->dram_type == LPDDR3) { 409 tmp = pdram_timing->cl; 410 if (tmp >= 14) 411 tmp = 8; 412 else if (tmp >= 10) 413 tmp = 6; 414 else if (tmp == 9) 415 tmp = 5; 416 else if (tmp == 8) 417 tmp = 4; 418 else if (tmp == 6) 419 tmp = 3; 420 else 421 tmp = 1; 422 } else { 423 tmp = 1; 424 } 425 426 return tmp; 427 } 428 429 static uint32_t get_pi_wrlat_adj(struct dram_timing_t *pdram_timing, 430 struct timing_related_config *timing_config) 431 { 432 return get_pi_wrlat(pdram_timing, timing_config) + PI_ADD_LATENCY - 1; 433 } 434 435 static uint32_t get_pi_tdfi_phy_rdlat(struct dram_timing_t *pdram_timing, 436 struct timing_related_config *timing_config) 437 { 438 /* [DLLSUBTYPE2] == "STD_DENALI_HS" */ 439 uint32_t cas_lat, delay_adder, ie_enable, hs_offset, ie_delay_adder; 440 uint32_t mem_delay_ps, round_trip_ps; 441 uint32_t phy_internal_delay, lpddr_adder, dfi_adder, rdlat_delay; 442 443 ie_enable = PI_IE_ENABLE_VALUE; 444 445 delay_adder = ie_enable / (1000000 / pdram_timing->mhz); 446 if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0) 447 delay_adder++; 448 delay_adder = delay_adder - 1; 449 if (PI_REGS_DIMM_SUPPORT && PI_DOUBLEFREEK) 450 hs_offset = 2; 451 else 452 hs_offset = 1; 453 454 cas_lat = pdram_timing->cl + PI_ADD_LATENCY; 455 456 if (delay_adder > (cas_lat - 1 - hs_offset)) { 457 ie_delay_adder = 0; 458 } else { 459 ie_delay_adder = ie_enable / (1000000 / pdram_timing->mhz); 460 if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0) 461 ie_delay_adder++; 462 } 463 464 if (timing_config->dram_type == DDR3) { 465 mem_delay_ps = 0; 466 } else if (timing_config->dram_type == LPDDR4) { 467 mem_delay_ps = 3600; 468 } else if (timing_config->dram_type == LPDDR3) { 469 mem_delay_ps = 5500; 470 } else { 471 printf("get_pi_tdfi_phy_rdlat:dramtype unsupport\n"); 472 return 0; 473 } 474 round_trip_ps = 1100 + 500 + mem_delay_ps + 500 + 600; 475 delay_adder = round_trip_ps / (1000000 / pdram_timing->mhz); 476 if ((round_trip_ps % (1000000 / pdram_timing->mhz)) != 0) 477 delay_adder++; 478 479 phy_internal_delay = 5 + 2 + 4; 480 lpddr_adder = mem_delay_ps / (1000000 / pdram_timing->mhz); 481 if ((mem_delay_ps % (1000000 / pdram_timing->mhz)) != 0) 482 lpddr_adder++; 483 dfi_adder = 0; 484 phy_internal_delay = phy_internal_delay + 2; 485 rdlat_delay = delay_adder + phy_internal_delay + 486 ie_delay_adder + lpddr_adder + dfi_adder; 487 488 rdlat_delay = rdlat_delay + 2; 489 return rdlat_delay; 490 } 491 492 static uint32_t get_pi_todtoff_min(struct dram_timing_t *pdram_timing, 493 struct timing_related_config *timing_config) 494 { 495 uint32_t tmp, todtoff_min_ps; 496 497 if (timing_config->dram_type == LPDDR3) 498 todtoff_min_ps = 2500; 499 else if (timing_config->dram_type == LPDDR4) 500 todtoff_min_ps = 1500; 501 else 502 todtoff_min_ps = 0; 503 /* todtoff_min */ 504 tmp = todtoff_min_ps / (1000000 / pdram_timing->mhz); 505 if ((todtoff_min_ps % (1000000 / pdram_timing->mhz)) != 0) 506 tmp++; 507 return tmp; 508 } 509 510 static uint32_t get_pi_todtoff_max(struct dram_timing_t *pdram_timing, 511 struct timing_related_config *timing_config) 512 { 513 uint32_t tmp, todtoff_max_ps; 514 515 if ((timing_config->dram_type == LPDDR4) 516 || (timing_config->dram_type == LPDDR3)) 517 todtoff_max_ps = 3500; 518 else 519 todtoff_max_ps = 0; 520 521 /* todtoff_max */ 522 tmp = todtoff_max_ps / (1000000 / pdram_timing->mhz); 523 if ((todtoff_max_ps % (1000000 / pdram_timing->mhz)) != 0) 524 tmp++; 525 return tmp; 526 } 527 528 static void gen_rk3399_ctl_params_f0(struct timing_related_config 529 *timing_config, 530 struct dram_timing_t *pdram_timing) 531 { 532 uint32_t i; 533 uint32_t tmp, tmp1; 534 535 for (i = 0; i < timing_config->ch_cnt; i++) { 536 if (timing_config->dram_type == DDR3) { 537 tmp = ((700000 + 10) * timing_config->freq + 538 999) / 1000; 539 tmp += pdram_timing->txsnr + (pdram_timing->tmrd * 3) + 540 pdram_timing->tmod + pdram_timing->tzqinit; 541 mmio_write_32(CTL_REG(i, 5), tmp); 542 543 mmio_clrsetbits_32(CTL_REG(i, 22), 0xffff, 544 pdram_timing->tdllk); 545 546 mmio_write_32(CTL_REG(i, 32), 547 (pdram_timing->tmod << 8) | 548 pdram_timing->tmrd); 549 550 mmio_clrsetbits_32(CTL_REG(i, 59), 0xffff << 16, 551 (pdram_timing->txsr - 552 pdram_timing->trcd) << 16); 553 } else if (timing_config->dram_type == LPDDR4) { 554 mmio_write_32(CTL_REG(i, 5), pdram_timing->tinit1 + 555 pdram_timing->tinit3); 556 mmio_write_32(CTL_REG(i, 32), 557 (pdram_timing->tmrd << 8) | 558 pdram_timing->tmrd); 559 mmio_clrsetbits_32(CTL_REG(i, 59), 0xffff << 16, 560 pdram_timing->txsr << 16); 561 } else { 562 mmio_write_32(CTL_REG(i, 5), pdram_timing->tinit1); 563 mmio_write_32(CTL_REG(i, 7), pdram_timing->tinit4); 564 mmio_write_32(CTL_REG(i, 32), 565 (pdram_timing->tmrd << 8) | 566 pdram_timing->tmrd); 567 mmio_clrsetbits_32(CTL_REG(i, 59), 0xffff << 16, 568 pdram_timing->txsr << 16); 569 } 570 mmio_write_32(CTL_REG(i, 6), pdram_timing->tinit3); 571 mmio_write_32(CTL_REG(i, 8), pdram_timing->tinit5); 572 mmio_clrsetbits_32(CTL_REG(i, 23), (0x7f << 16), 573 ((pdram_timing->cl * 2) << 16)); 574 mmio_clrsetbits_32(CTL_REG(i, 23), (0x1f << 24), 575 (pdram_timing->cwl << 24)); 576 mmio_clrsetbits_32(CTL_REG(i, 24), 0x3f, pdram_timing->al); 577 mmio_clrsetbits_32(CTL_REG(i, 26), 0xffff << 16, 578 (pdram_timing->trc << 24) | 579 (pdram_timing->trrd << 16)); 580 mmio_write_32(CTL_REG(i, 27), 581 (pdram_timing->tfaw << 24) | 582 (pdram_timing->trppb << 16) | 583 (pdram_timing->twtr << 8) | 584 pdram_timing->tras_min); 585 586 mmio_clrsetbits_32(CTL_REG(i, 31), 0xff << 24, 587 max(4, pdram_timing->trtp) << 24); 588 mmio_write_32(CTL_REG(i, 33), (pdram_timing->tcke << 24) | 589 pdram_timing->tras_max); 590 mmio_clrsetbits_32(CTL_REG(i, 34), 0xff, 591 max(1, pdram_timing->tckesr)); 592 mmio_clrsetbits_32(CTL_REG(i, 39), 593 (0x3f << 16) | (0xff << 8), 594 (pdram_timing->twr << 16) | 595 (pdram_timing->trcd << 8)); 596 mmio_clrsetbits_32(CTL_REG(i, 42), 0x1f << 16, 597 pdram_timing->tmrz << 16); 598 tmp = pdram_timing->tdal ? pdram_timing->tdal : 599 (pdram_timing->twr + pdram_timing->trp); 600 mmio_clrsetbits_32(CTL_REG(i, 44), 0xff, tmp); 601 mmio_clrsetbits_32(CTL_REG(i, 45), 0xff, pdram_timing->trp); 602 mmio_write_32(CTL_REG(i, 48), 603 ((pdram_timing->trefi - 8) << 16) | 604 pdram_timing->trfc); 605 mmio_clrsetbits_32(CTL_REG(i, 52), 0xffff, pdram_timing->txp); 606 mmio_clrsetbits_32(CTL_REG(i, 53), 0xffff << 16, 607 pdram_timing->txpdll << 16); 608 mmio_clrsetbits_32(CTL_REG(i, 55), 0xf << 24, 609 pdram_timing->tcscke << 24); 610 mmio_clrsetbits_32(CTL_REG(i, 55), 0xff, pdram_timing->tmrri); 611 mmio_write_32(CTL_REG(i, 56), 612 (pdram_timing->tzqcke << 24) | 613 (pdram_timing->tmrwckel << 16) | 614 (pdram_timing->tckehcs << 8) | 615 pdram_timing->tckelcs); 616 mmio_clrsetbits_32(CTL_REG(i, 60), 0xffff, pdram_timing->txsnr); 617 mmio_clrsetbits_32(CTL_REG(i, 62), 0xffff << 16, 618 (pdram_timing->tckehcmd << 24) | 619 (pdram_timing->tckelcmd << 16)); 620 mmio_write_32(CTL_REG(i, 63), 621 (pdram_timing->tckelpd << 24) | 622 (pdram_timing->tescke << 16) | 623 (pdram_timing->tsr << 8) | 624 pdram_timing->tckckel); 625 mmio_clrsetbits_32(CTL_REG(i, 64), 0xfff, 626 (pdram_timing->tcmdcke << 8) | 627 pdram_timing->tcsckeh); 628 mmio_clrsetbits_32(CTL_REG(i, 92), 0xffff << 8, 629 (pdram_timing->tcksrx << 16) | 630 (pdram_timing->tcksre << 8)); 631 mmio_clrsetbits_32(CTL_REG(i, 108), 0x1 << 24, 632 (timing_config->dllbp << 24)); 633 mmio_clrsetbits_32(CTL_REG(i, 122), 0x3ff << 16, 634 (pdram_timing->tvrcg_enable << 16)); 635 mmio_write_32(CTL_REG(i, 123), (pdram_timing->tfc_long << 16) | 636 pdram_timing->tvrcg_disable); 637 mmio_write_32(CTL_REG(i, 124), 638 (pdram_timing->tvref_long << 16) | 639 (pdram_timing->tckfspx << 8) | 640 pdram_timing->tckfspe); 641 mmio_write_32(CTL_REG(i, 133), (pdram_timing->mr[1] << 16) | 642 pdram_timing->mr[0]); 643 mmio_clrsetbits_32(CTL_REG(i, 134), 0xffff, 644 pdram_timing->mr[2]); 645 mmio_clrsetbits_32(CTL_REG(i, 138), 0xffff, 646 pdram_timing->mr[3]); 647 mmio_clrsetbits_32(CTL_REG(i, 139), 0xff << 24, 648 pdram_timing->mr11 << 24); 649 mmio_write_32(CTL_REG(i, 147), 650 (pdram_timing->mr[1] << 16) | 651 pdram_timing->mr[0]); 652 mmio_clrsetbits_32(CTL_REG(i, 148), 0xffff, 653 pdram_timing->mr[2]); 654 mmio_clrsetbits_32(CTL_REG(i, 152), 0xffff, 655 pdram_timing->mr[3]); 656 mmio_clrsetbits_32(CTL_REG(i, 153), 0xff << 24, 657 pdram_timing->mr11 << 24); 658 if (timing_config->dram_type == LPDDR4) { 659 mmio_clrsetbits_32(CTL_REG(i, 140), 0xffff << 16, 660 pdram_timing->mr12 << 16); 661 mmio_clrsetbits_32(CTL_REG(i, 142), 0xffff << 16, 662 pdram_timing->mr14 << 16); 663 mmio_clrsetbits_32(CTL_REG(i, 145), 0xffff << 16, 664 pdram_timing->mr22 << 16); 665 mmio_clrsetbits_32(CTL_REG(i, 154), 0xffff << 16, 666 pdram_timing->mr12 << 16); 667 mmio_clrsetbits_32(CTL_REG(i, 156), 0xffff << 16, 668 pdram_timing->mr14 << 16); 669 mmio_clrsetbits_32(CTL_REG(i, 159), 0xffff << 16, 670 pdram_timing->mr22 << 16); 671 } 672 mmio_clrsetbits_32(CTL_REG(i, 179), 0xfff << 8, 673 pdram_timing->tzqinit << 8); 674 mmio_write_32(CTL_REG(i, 180), (pdram_timing->tzqcs << 16) | 675 (pdram_timing->tzqinit / 2)); 676 mmio_write_32(CTL_REG(i, 181), (pdram_timing->tzqlat << 16) | 677 pdram_timing->tzqcal); 678 mmio_clrsetbits_32(CTL_REG(i, 212), 0xff << 8, 679 pdram_timing->todton << 8); 680 681 if (timing_config->odt) { 682 mmio_setbits_32(CTL_REG(i, 213), 1 << 16); 683 if (timing_config->freq < 400) 684 tmp = 4 << 24; 685 else 686 tmp = 8 << 24; 687 } else { 688 mmio_clrbits_32(CTL_REG(i, 213), 1 << 16); 689 tmp = 2 << 24; 690 } 691 692 mmio_clrsetbits_32(CTL_REG(i, 216), 0x1f << 24, tmp); 693 mmio_clrsetbits_32(CTL_REG(i, 221), (0x3 << 16) | (0xf << 8), 694 (pdram_timing->tdqsck << 16) | 695 (pdram_timing->tdqsck_max << 8)); 696 tmp = 697 (get_wrlat_adj(timing_config->dram_type, pdram_timing->cwl) 698 << 8) | get_rdlat_adj(timing_config->dram_type, 699 pdram_timing->cl); 700 mmio_clrsetbits_32(CTL_REG(i, 284), 0xffff, tmp); 701 mmio_clrsetbits_32(CTL_REG(i, 82), 0xffff << 16, 702 (4 * pdram_timing->trefi) << 16); 703 704 mmio_clrsetbits_32(CTL_REG(i, 83), 0xffff, 705 (2 * pdram_timing->trefi) & 0xffff); 706 707 if ((timing_config->dram_type == LPDDR3) || 708 (timing_config->dram_type == LPDDR4)) { 709 tmp = get_pi_wrlat(pdram_timing, timing_config); 710 tmp1 = get_pi_todtoff_max(pdram_timing, timing_config); 711 tmp = (tmp > tmp1) ? (tmp - tmp1) : 0; 712 } else { 713 tmp = 0; 714 } 715 mmio_clrsetbits_32(CTL_REG(i, 214), 0x3f << 16, 716 (tmp & 0x3f) << 16); 717 718 if ((timing_config->dram_type == LPDDR3) || 719 (timing_config->dram_type == LPDDR4)) { 720 /* min_rl_preamble = cl+TDQSCK_MIN -1 */ 721 tmp = pdram_timing->cl + 722 get_pi_todtoff_min(pdram_timing, timing_config) - 1; 723 /* todtoff_max */ 724 tmp1 = get_pi_todtoff_max(pdram_timing, timing_config); 725 tmp = (tmp > tmp1) ? (tmp - tmp1) : 0; 726 } else { 727 tmp = pdram_timing->cl - pdram_timing->cwl; 728 } 729 mmio_clrsetbits_32(CTL_REG(i, 215), 0x3f << 8, 730 (tmp & 0x3f) << 8); 731 732 mmio_clrsetbits_32(CTL_REG(i, 275), 0xff << 16, 733 (get_pi_tdfi_phy_rdlat(pdram_timing, 734 timing_config) & 735 0xff) << 16); 736 737 mmio_clrsetbits_32(CTL_REG(i, 277), 0xffff, 738 (2 * pdram_timing->trefi) & 0xffff); 739 740 mmio_clrsetbits_32(CTL_REG(i, 282), 0xffff, 741 (2 * pdram_timing->trefi) & 0xffff); 742 743 mmio_write_32(CTL_REG(i, 283), 20 * pdram_timing->trefi); 744 745 /* CTL_308 TDFI_CALVL_CAPTURE_F0:RW:16:10 */ 746 tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1; 747 if ((20000 % (1000000 / pdram_timing->mhz)) != 0) 748 tmp1++; 749 tmp = (tmp1 >> 1) + (tmp1 % 2) + 5; 750 mmio_clrsetbits_32(CTL_REG(i, 308), 0x3ff << 16, tmp << 16); 751 752 /* CTL_308 TDFI_CALVL_CC_F0:RW:0:10 */ 753 tmp = tmp + 18; 754 mmio_clrsetbits_32(CTL_REG(i, 308), 0x3ff, tmp); 755 756 /* CTL_314 TDFI_WRCSLAT_F0:RW:8:8 */ 757 tmp1 = get_pi_wrlat_adj(pdram_timing, timing_config); 758 if (timing_config->freq <= ENPER_CS_TRAINING_FREQ) { 759 if (tmp1 == 0) 760 tmp = 0; 761 else if (tmp1 < 5) 762 tmp = tmp1 - 1; 763 else 764 tmp = tmp1 - 5; 765 } else { 766 tmp = tmp1 - 2; 767 } 768 mmio_clrsetbits_32(CTL_REG(i, 314), 0xff << 8, tmp << 8); 769 770 /* CTL_314 TDFI_RDCSLAT_F0:RW:0:8 */ 771 if ((timing_config->freq <= ENPER_CS_TRAINING_FREQ) && 772 (pdram_timing->cl >= 5)) 773 tmp = pdram_timing->cl - 5; 774 else 775 tmp = pdram_timing->cl - 2; 776 mmio_clrsetbits_32(CTL_REG(i, 314), 0xff, tmp); 777 } 778 } 779 780 static void gen_rk3399_ctl_params_f1(struct timing_related_config 781 *timing_config, 782 struct dram_timing_t *pdram_timing) 783 { 784 uint32_t i; 785 uint32_t tmp, tmp1; 786 787 for (i = 0; i < timing_config->ch_cnt; i++) { 788 if (timing_config->dram_type == DDR3) { 789 tmp = 790 ((700000 + 10) * timing_config->freq + 999) / 1000; 791 tmp += pdram_timing->txsnr + (pdram_timing->tmrd * 3) + 792 pdram_timing->tmod + pdram_timing->tzqinit; 793 mmio_write_32(CTL_REG(i, 9), tmp); 794 mmio_clrsetbits_32(CTL_REG(i, 22), 0xffff << 16, 795 pdram_timing->tdllk << 16); 796 mmio_clrsetbits_32(CTL_REG(i, 34), 0xffffff00, 797 (pdram_timing->tmod << 24) | 798 (pdram_timing->tmrd << 16) | 799 (pdram_timing->trtp << 8)); 800 mmio_clrsetbits_32(CTL_REG(i, 60), 0xffff << 16, 801 (pdram_timing->txsr - 802 pdram_timing->trcd) << 16); 803 } else if (timing_config->dram_type == LPDDR4) { 804 mmio_write_32(CTL_REG(i, 9), pdram_timing->tinit1 + 805 pdram_timing->tinit3); 806 mmio_clrsetbits_32(CTL_REG(i, 34), 0xffffff00, 807 (pdram_timing->tmrd << 24) | 808 (pdram_timing->tmrd << 16) | 809 (pdram_timing->trtp << 8)); 810 mmio_clrsetbits_32(CTL_REG(i, 60), 0xffff << 16, 811 pdram_timing->txsr << 16); 812 } else { 813 mmio_write_32(CTL_REG(i, 9), pdram_timing->tinit1); 814 mmio_write_32(CTL_REG(i, 11), pdram_timing->tinit4); 815 mmio_clrsetbits_32(CTL_REG(i, 34), 0xffffff00, 816 (pdram_timing->tmrd << 24) | 817 (pdram_timing->tmrd << 16) | 818 (pdram_timing->trtp << 8)); 819 mmio_clrsetbits_32(CTL_REG(i, 60), 0xffff << 16, 820 pdram_timing->txsr << 16); 821 } 822 mmio_write_32(CTL_REG(i, 10), pdram_timing->tinit3); 823 mmio_write_32(CTL_REG(i, 12), pdram_timing->tinit5); 824 mmio_clrsetbits_32(CTL_REG(i, 24), (0x7f << 8), 825 ((pdram_timing->cl * 2) << 8)); 826 mmio_clrsetbits_32(CTL_REG(i, 24), (0x1f << 16), 827 (pdram_timing->cwl << 16)); 828 mmio_clrsetbits_32(CTL_REG(i, 24), 0x3f << 24, 829 pdram_timing->al << 24); 830 mmio_clrsetbits_32(CTL_REG(i, 28), 0xffffff00, 831 (pdram_timing->tras_min << 24) | 832 (pdram_timing->trc << 16) | 833 (pdram_timing->trrd << 8)); 834 mmio_clrsetbits_32(CTL_REG(i, 29), 0xffffff, 835 (pdram_timing->tfaw << 16) | 836 (pdram_timing->trppb << 8) | 837 pdram_timing->twtr); 838 mmio_write_32(CTL_REG(i, 35), (pdram_timing->tcke << 24) | 839 pdram_timing->tras_max); 840 mmio_clrsetbits_32(CTL_REG(i, 36), 0xff, 841 max(1, pdram_timing->tckesr)); 842 mmio_clrsetbits_32(CTL_REG(i, 39), (0xff << 24), 843 (pdram_timing->trcd << 24)); 844 mmio_clrsetbits_32(CTL_REG(i, 40), 0x3f, pdram_timing->twr); 845 mmio_clrsetbits_32(CTL_REG(i, 42), 0x1f << 24, 846 pdram_timing->tmrz << 24); 847 tmp = pdram_timing->tdal ? pdram_timing->tdal : 848 (pdram_timing->twr + pdram_timing->trp); 849 mmio_clrsetbits_32(CTL_REG(i, 44), 0xff << 8, tmp << 8); 850 mmio_clrsetbits_32(CTL_REG(i, 45), 0xff << 8, 851 pdram_timing->trp << 8); 852 mmio_write_32(CTL_REG(i, 49), 853 ((pdram_timing->trefi - 8) << 16) | 854 pdram_timing->trfc); 855 mmio_clrsetbits_32(CTL_REG(i, 52), 0xffff << 16, 856 pdram_timing->txp << 16); 857 mmio_clrsetbits_32(CTL_REG(i, 54), 0xffff, 858 pdram_timing->txpdll); 859 mmio_clrsetbits_32(CTL_REG(i, 55), 0xff << 8, 860 pdram_timing->tmrri << 8); 861 mmio_write_32(CTL_REG(i, 57), (pdram_timing->tmrwckel << 24) | 862 (pdram_timing->tckehcs << 16) | 863 (pdram_timing->tckelcs << 8) | 864 pdram_timing->tcscke); 865 mmio_clrsetbits_32(CTL_REG(i, 58), 0xf, pdram_timing->tzqcke); 866 mmio_clrsetbits_32(CTL_REG(i, 61), 0xffff, pdram_timing->txsnr); 867 mmio_clrsetbits_32(CTL_REG(i, 64), 0xffff << 16, 868 (pdram_timing->tckehcmd << 24) | 869 (pdram_timing->tckelcmd << 16)); 870 mmio_write_32(CTL_REG(i, 65), (pdram_timing->tckelpd << 24) | 871 (pdram_timing->tescke << 16) | 872 (pdram_timing->tsr << 8) | 873 pdram_timing->tckckel); 874 mmio_clrsetbits_32(CTL_REG(i, 66), 0xfff, 875 (pdram_timing->tcmdcke << 8) | 876 pdram_timing->tcsckeh); 877 mmio_clrsetbits_32(CTL_REG(i, 92), (0xff << 24), 878 (pdram_timing->tcksre << 24)); 879 mmio_clrsetbits_32(CTL_REG(i, 93), 0xff, 880 pdram_timing->tcksrx); 881 mmio_clrsetbits_32(CTL_REG(i, 108), (0x1 << 25), 882 (timing_config->dllbp << 25)); 883 mmio_write_32(CTL_REG(i, 125), 884 (pdram_timing->tvrcg_disable << 16) | 885 pdram_timing->tvrcg_enable); 886 mmio_write_32(CTL_REG(i, 126), (pdram_timing->tckfspx << 24) | 887 (pdram_timing->tckfspe << 16) | 888 pdram_timing->tfc_long); 889 mmio_clrsetbits_32(CTL_REG(i, 127), 0xffff, 890 pdram_timing->tvref_long); 891 mmio_clrsetbits_32(CTL_REG(i, 134), 0xffff << 16, 892 pdram_timing->mr[0] << 16); 893 mmio_write_32(CTL_REG(i, 135), (pdram_timing->mr[2] << 16) | 894 pdram_timing->mr[1]); 895 mmio_clrsetbits_32(CTL_REG(i, 138), 0xffff << 16, 896 pdram_timing->mr[3] << 16); 897 mmio_clrsetbits_32(CTL_REG(i, 140), 0xff, pdram_timing->mr11); 898 mmio_clrsetbits_32(CTL_REG(i, 148), 0xffff << 16, 899 pdram_timing->mr[0] << 16); 900 mmio_write_32(CTL_REG(i, 149), (pdram_timing->mr[2] << 16) | 901 pdram_timing->mr[1]); 902 mmio_clrsetbits_32(CTL_REG(i, 152), 0xffff << 16, 903 pdram_timing->mr[3] << 16); 904 mmio_clrsetbits_32(CTL_REG(i, 154), 0xff, pdram_timing->mr11); 905 if (timing_config->dram_type == LPDDR4) { 906 mmio_clrsetbits_32(CTL_REG(i, 141), 0xffff, 907 pdram_timing->mr12); 908 mmio_clrsetbits_32(CTL_REG(i, 143), 0xffff, 909 pdram_timing->mr14); 910 mmio_clrsetbits_32(CTL_REG(i, 146), 0xffff, 911 pdram_timing->mr22); 912 mmio_clrsetbits_32(CTL_REG(i, 155), 0xffff, 913 pdram_timing->mr12); 914 mmio_clrsetbits_32(CTL_REG(i, 157), 0xffff, 915 pdram_timing->mr14); 916 mmio_clrsetbits_32(CTL_REG(i, 160), 0xffff, 917 pdram_timing->mr22); 918 } 919 mmio_write_32(CTL_REG(i, 182), 920 ((pdram_timing->tzqinit / 2) << 16) | 921 pdram_timing->tzqinit); 922 mmio_write_32(CTL_REG(i, 183), (pdram_timing->tzqcal << 16) | 923 pdram_timing->tzqcs); 924 mmio_clrsetbits_32(CTL_REG(i, 184), 0x3f, pdram_timing->tzqlat); 925 mmio_clrsetbits_32(CTL_REG(i, 188), 0xfff, 926 pdram_timing->tzqreset); 927 mmio_clrsetbits_32(CTL_REG(i, 212), 0xff << 16, 928 pdram_timing->todton << 16); 929 930 if (timing_config->odt) { 931 mmio_setbits_32(CTL_REG(i, 213), (1 << 24)); 932 if (timing_config->freq < 400) 933 tmp = 4 << 24; 934 else 935 tmp = 8 << 24; 936 } else { 937 mmio_clrbits_32(CTL_REG(i, 213), (1 << 24)); 938 tmp = 2 << 24; 939 } 940 mmio_clrsetbits_32(CTL_REG(i, 217), 0x1f << 24, tmp); 941 mmio_clrsetbits_32(CTL_REG(i, 221), 0xf << 24, 942 (pdram_timing->tdqsck_max << 24)); 943 mmio_clrsetbits_32(CTL_REG(i, 222), 0x3, pdram_timing->tdqsck); 944 mmio_clrsetbits_32(CTL_REG(i, 291), 0xffff, 945 (get_wrlat_adj(timing_config->dram_type, 946 pdram_timing->cwl) << 8) | 947 get_rdlat_adj(timing_config->dram_type, 948 pdram_timing->cl)); 949 950 mmio_clrsetbits_32(CTL_REG(i, 84), 0xffff, 951 (4 * pdram_timing->trefi) & 0xffff); 952 953 mmio_clrsetbits_32(CTL_REG(i, 84), 0xffff << 16, 954 ((2 * pdram_timing->trefi) & 0xffff) << 16); 955 956 if ((timing_config->dram_type == LPDDR3) || 957 (timing_config->dram_type == LPDDR4)) { 958 tmp = get_pi_wrlat(pdram_timing, timing_config); 959 tmp1 = get_pi_todtoff_max(pdram_timing, timing_config); 960 tmp = (tmp > tmp1) ? (tmp - tmp1) : 0; 961 } else { 962 tmp = 0; 963 } 964 mmio_clrsetbits_32(CTL_REG(i, 214), 0x3f << 24, 965 (tmp & 0x3f) << 24); 966 967 if ((timing_config->dram_type == LPDDR3) || 968 (timing_config->dram_type == LPDDR4)) { 969 /* min_rl_preamble = cl + TDQSCK_MIN - 1 */ 970 tmp = pdram_timing->cl + 971 get_pi_todtoff_min(pdram_timing, timing_config); 972 tmp--; 973 /* todtoff_max */ 974 tmp1 = get_pi_todtoff_max(pdram_timing, timing_config); 975 tmp = (tmp > tmp1) ? (tmp - tmp1) : 0; 976 } else { 977 tmp = pdram_timing->cl - pdram_timing->cwl; 978 } 979 mmio_clrsetbits_32(CTL_REG(i, 215), 0x3f << 16, 980 (tmp & 0x3f) << 16); 981 982 mmio_clrsetbits_32(CTL_REG(i, 275), 0xff << 24, 983 (get_pi_tdfi_phy_rdlat(pdram_timing, 984 timing_config) & 985 0xff) << 24); 986 987 mmio_clrsetbits_32(CTL_REG(i, 284), 0xffff << 16, 988 ((2 * pdram_timing->trefi) & 0xffff) << 16); 989 990 mmio_clrsetbits_32(CTL_REG(i, 289), 0xffff, 991 (2 * pdram_timing->trefi) & 0xffff); 992 993 mmio_write_32(CTL_REG(i, 290), 20 * pdram_timing->trefi); 994 995 /* CTL_309 TDFI_CALVL_CAPTURE_F1:RW:16:10 */ 996 tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1; 997 if ((20000 % (1000000 / pdram_timing->mhz)) != 0) 998 tmp1++; 999 tmp = (tmp1 >> 1) + (tmp1 % 2) + 5; 1000 mmio_clrsetbits_32(CTL_REG(i, 309), 0x3ff << 16, tmp << 16); 1001 1002 /* CTL_309 TDFI_CALVL_CC_F1:RW:0:10 */ 1003 tmp = tmp + 18; 1004 mmio_clrsetbits_32(CTL_REG(i, 309), 0x3ff, tmp); 1005 1006 /* CTL_314 TDFI_WRCSLAT_F1:RW:24:8 */ 1007 tmp1 = get_pi_wrlat_adj(pdram_timing, timing_config); 1008 if (timing_config->freq <= ENPER_CS_TRAINING_FREQ) { 1009 if (tmp1 == 0) 1010 tmp = 0; 1011 else if (tmp1 < 5) 1012 tmp = tmp1 - 1; 1013 else 1014 tmp = tmp1 - 5; 1015 } else { 1016 tmp = tmp1 - 2; 1017 } 1018 1019 mmio_clrsetbits_32(CTL_REG(i, 314), 0xff << 24, tmp << 24); 1020 1021 /* CTL_314 TDFI_RDCSLAT_F1:RW:16:8 */ 1022 if ((timing_config->freq <= ENPER_CS_TRAINING_FREQ) && 1023 (pdram_timing->cl >= 5)) 1024 tmp = pdram_timing->cl - 5; 1025 else 1026 tmp = pdram_timing->cl - 2; 1027 mmio_clrsetbits_32(CTL_REG(i, 314), 0xff << 16, tmp << 16); 1028 } 1029 } 1030 1031 static void gen_rk3399_ctl_params(struct timing_related_config *timing_config, 1032 struct dram_timing_t *pdram_timing, 1033 uint32_t fn) 1034 { 1035 if (fn == 0) 1036 gen_rk3399_ctl_params_f0(timing_config, pdram_timing); 1037 else 1038 gen_rk3399_ctl_params_f1(timing_config, pdram_timing); 1039 1040 #if CTL_TRAINING 1041 uint32_t i, tmp0, tmp1; 1042 1043 tmp0 = tmp1 = 0; 1044 #if EN_READ_GATE_TRAINING 1045 tmp1 = 1; 1046 #endif 1047 1048 #if EN_CA_TRAINING 1049 tmp0 |= (1 << 8); 1050 #endif 1051 1052 #if EN_WRITE_LEVELING 1053 tmp0 |= (1 << 16); 1054 #endif 1055 1056 #if EN_READ_LEVELING 1057 tmp0 |= (1 << 24); 1058 #endif 1059 for (i = 0; i < timing_config->ch_cnt; i++) { 1060 if (tmp0 | tmp1) 1061 mmio_setbits_32(CTL_REG(i, 305), 1 << 16); 1062 if (tmp0) 1063 mmio_setbits_32(CTL_REG(i, 70), tmp0); 1064 if (tmp1) 1065 mmio_setbits_32(CTL_REG(i, 71), tmp1); 1066 } 1067 #endif 1068 } 1069 1070 static void gen_rk3399_pi_params_f0(struct timing_related_config *timing_config, 1071 struct dram_timing_t *pdram_timing) 1072 { 1073 uint32_t tmp, tmp1, tmp2; 1074 uint32_t i; 1075 1076 for (i = 0; i < timing_config->ch_cnt; i++) { 1077 /* PI_02 PI_TDFI_PHYMSTR_MAX_F0:RW:0:32 */ 1078 tmp = 4 * pdram_timing->trefi; 1079 mmio_write_32(PI_REG(i, 2), tmp); 1080 /* PI_03 PI_TDFI_PHYMSTR_RESP_F0:RW:0:16 */ 1081 tmp = 2 * pdram_timing->trefi; 1082 mmio_clrsetbits_32(PI_REG(i, 3), 0xffff, tmp); 1083 /* PI_07 PI_TDFI_PHYUPD_RESP_F0:RW:16:16 */ 1084 mmio_clrsetbits_32(PI_REG(i, 7), 0xffff << 16, tmp << 16); 1085 1086 /* PI_42 PI_TDELAY_RDWR_2_BUS_IDLE_F0:RW:0:8 */ 1087 if (timing_config->dram_type == LPDDR4) 1088 tmp = 2; 1089 else 1090 tmp = 0; 1091 tmp = (pdram_timing->bl / 2) + 4 + 1092 (get_pi_rdlat_adj(pdram_timing) - 2) + tmp + 1093 get_pi_tdfi_phy_rdlat(pdram_timing, timing_config); 1094 mmio_clrsetbits_32(PI_REG(i, 42), 0xff, tmp); 1095 /* PI_43 PI_WRLAT_F0:RW:0:5 */ 1096 if (timing_config->dram_type == LPDDR3) { 1097 tmp = get_pi_wrlat(pdram_timing, timing_config); 1098 mmio_clrsetbits_32(PI_REG(i, 43), 0x1f, tmp); 1099 } 1100 /* PI_43 PI_ADDITIVE_LAT_F0:RW:8:6 */ 1101 mmio_clrsetbits_32(PI_REG(i, 43), 0x3f << 8, 1102 PI_ADD_LATENCY << 8); 1103 1104 /* PI_43 PI_CASLAT_LIN_F0:RW:16:7 */ 1105 mmio_clrsetbits_32(PI_REG(i, 43), 0x7f << 16, 1106 (pdram_timing->cl * 2) << 16); 1107 /* PI_46 PI_TREF_F0:RW:16:16 */ 1108 mmio_clrsetbits_32(PI_REG(i, 46), 0xffff << 16, 1109 pdram_timing->trefi << 16); 1110 /* PI_46 PI_TRFC_F0:RW:0:10 */ 1111 mmio_clrsetbits_32(PI_REG(i, 46), 0x3ff, pdram_timing->trfc); 1112 /* PI_66 PI_TODTL_2CMD_F0:RW:24:8 */ 1113 if (timing_config->dram_type == LPDDR3) { 1114 tmp = get_pi_todtoff_max(pdram_timing, timing_config); 1115 mmio_clrsetbits_32(PI_REG(i, 66), 0xff << 24, 1116 tmp << 24); 1117 } 1118 /* PI_72 PI_WR_TO_ODTH_F0:RW:16:6 */ 1119 if ((timing_config->dram_type == LPDDR3) || 1120 (timing_config->dram_type == LPDDR4)) { 1121 tmp1 = get_pi_wrlat(pdram_timing, timing_config); 1122 tmp2 = get_pi_todtoff_max(pdram_timing, timing_config); 1123 if (tmp1 > tmp2) 1124 tmp = tmp1 - tmp2; 1125 else 1126 tmp = 0; 1127 } else if (timing_config->dram_type == DDR3) { 1128 tmp = 0; 1129 } 1130 mmio_clrsetbits_32(PI_REG(i, 72), 0x3f << 16, tmp << 16); 1131 /* PI_73 PI_RD_TO_ODTH_F0:RW:8:6 */ 1132 if ((timing_config->dram_type == LPDDR3) || 1133 (timing_config->dram_type == LPDDR4)) { 1134 /* min_rl_preamble = cl + TDQSCK_MIN - 1 */ 1135 tmp1 = pdram_timing->cl; 1136 tmp1 += get_pi_todtoff_min(pdram_timing, timing_config); 1137 tmp1--; 1138 /* todtoff_max */ 1139 tmp2 = get_pi_todtoff_max(pdram_timing, timing_config); 1140 if (tmp1 > tmp2) 1141 tmp = tmp1 - tmp2; 1142 else 1143 tmp = 0; 1144 } else if (timing_config->dram_type == DDR3) { 1145 tmp = pdram_timing->cl - pdram_timing->cwl; 1146 } 1147 mmio_clrsetbits_32(PI_REG(i, 73), 0x3f << 8, tmp << 8); 1148 /* PI_89 PI_RDLAT_ADJ_F0:RW:16:8 */ 1149 tmp = get_pi_rdlat_adj(pdram_timing); 1150 mmio_clrsetbits_32(PI_REG(i, 89), 0xff << 16, tmp << 16); 1151 /* PI_90 PI_WRLAT_ADJ_F0:RW:16:8 */ 1152 tmp = get_pi_wrlat_adj(pdram_timing, timing_config); 1153 mmio_clrsetbits_32(PI_REG(i, 90), 0xff << 16, tmp << 16); 1154 /* PI_91 PI_TDFI_WRCSLAT_F0:RW:16:8 */ 1155 tmp1 = tmp; 1156 if (tmp1 == 0) 1157 tmp = 0; 1158 else if (tmp1 < 5) 1159 tmp = tmp1 - 1; 1160 else 1161 tmp = tmp1 - 5; 1162 mmio_clrsetbits_32(PI_REG(i, 91), 0xff << 16, tmp << 16); 1163 /* PI_95 PI_TDFI_CALVL_CAPTURE_F0:RW:16:10 */ 1164 tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1; 1165 if ((20000 % (1000000 / pdram_timing->mhz)) != 0) 1166 tmp1++; 1167 tmp = (tmp1 >> 1) + (tmp1 % 2) + 5; 1168 mmio_clrsetbits_32(PI_REG(i, 95), 0x3ff << 16, tmp << 16); 1169 /* PI_95 PI_TDFI_CALVL_CC_F0:RW:0:10 */ 1170 mmio_clrsetbits_32(PI_REG(i, 95), 0x3ff, tmp + 18); 1171 /* PI_102 PI_TMRZ_F0:RW:8:5 */ 1172 mmio_clrsetbits_32(PI_REG(i, 102), 0x1f << 8, 1173 pdram_timing->tmrz << 8); 1174 /* PI_111 PI_TDFI_CALVL_STROBE_F0:RW:8:4 */ 1175 tmp1 = 2 * 1000 / (1000000 / pdram_timing->mhz); 1176 if ((2 * 1000 % (1000000 / pdram_timing->mhz)) != 0) 1177 tmp1++; 1178 /* pi_tdfi_calvl_strobe=tds_train+5 */ 1179 tmp = tmp1 + 5; 1180 mmio_clrsetbits_32(PI_REG(i, 111), 0xf << 8, tmp << 8); 1181 /* PI_116 PI_TCKEHDQS_F0:RW:16:6 */ 1182 tmp = 10000 / (1000000 / pdram_timing->mhz); 1183 if ((10000 % (1000000 / pdram_timing->mhz)) != 0) 1184 tmp++; 1185 if (pdram_timing->mhz <= 100) 1186 tmp = tmp + 1; 1187 else 1188 tmp = tmp + 8; 1189 mmio_clrsetbits_32(PI_REG(i, 116), 0x3f << 16, tmp << 16); 1190 /* PI_125 PI_MR1_DATA_F0_0:RW+:8:16 */ 1191 mmio_clrsetbits_32(PI_REG(i, 125), 0xffff << 8, 1192 pdram_timing->mr[1] << 8); 1193 /* PI_133 PI_MR1_DATA_F0_1:RW+:0:16 */ 1194 mmio_clrsetbits_32(PI_REG(i, 133), 0xffff, pdram_timing->mr[1]); 1195 /* PI_140 PI_MR1_DATA_F0_2:RW+:16:16 */ 1196 mmio_clrsetbits_32(PI_REG(i, 140), 0xffff << 16, 1197 pdram_timing->mr[1] << 16); 1198 /* PI_148 PI_MR1_DATA_F0_3:RW+:0:16 */ 1199 mmio_clrsetbits_32(PI_REG(i, 148), 0xffff, pdram_timing->mr[1]); 1200 /* PI_126 PI_MR2_DATA_F0_0:RW+:0:16 */ 1201 mmio_clrsetbits_32(PI_REG(i, 126), 0xffff, pdram_timing->mr[2]); 1202 /* PI_133 PI_MR2_DATA_F0_1:RW+:16:16 */ 1203 mmio_clrsetbits_32(PI_REG(i, 133), 0xffff << 16, 1204 pdram_timing->mr[2] << 16); 1205 /* PI_141 PI_MR2_DATA_F0_2:RW+:0:16 */ 1206 mmio_clrsetbits_32(PI_REG(i, 141), 0xffff, pdram_timing->mr[2]); 1207 /* PI_148 PI_MR2_DATA_F0_3:RW+:16:16 */ 1208 mmio_clrsetbits_32(PI_REG(i, 148), 0xffff << 16, 1209 pdram_timing->mr[2] << 16); 1210 /* PI_156 PI_TFC_F0:RW:0:10 */ 1211 mmio_clrsetbits_32(PI_REG(i, 156), 0x3ff, pdram_timing->trfc); 1212 /* PI_158 PI_TWR_F0:RW:24:6 */ 1213 mmio_clrsetbits_32(PI_REG(i, 158), 0x3f << 24, 1214 pdram_timing->twr << 24); 1215 /* PI_158 PI_TWTR_F0:RW:16:6 */ 1216 mmio_clrsetbits_32(PI_REG(i, 158), 0x3f << 16, 1217 pdram_timing->twtr << 16); 1218 /* PI_158 PI_TRCD_F0:RW:8:8 */ 1219 mmio_clrsetbits_32(PI_REG(i, 158), 0xff << 8, 1220 pdram_timing->trcd << 8); 1221 /* PI_158 PI_TRP_F0:RW:0:8 */ 1222 mmio_clrsetbits_32(PI_REG(i, 158), 0xff, pdram_timing->trp); 1223 /* PI_157 PI_TRTP_F0:RW:24:8 */ 1224 mmio_clrsetbits_32(PI_REG(i, 157), 0xff << 24, 1225 pdram_timing->trtp << 24); 1226 /* PI_159 PI_TRAS_MIN_F0:RW:24:8 */ 1227 mmio_clrsetbits_32(PI_REG(i, 159), 0xff << 24, 1228 pdram_timing->tras_min << 24); 1229 /* PI_159 PI_TRAS_MAX_F0:RW:0:17 */ 1230 tmp = pdram_timing->tras_max * 99 / 100; 1231 mmio_clrsetbits_32(PI_REG(i, 159), 0x1ffff, tmp); 1232 /* PI_160 PI_TMRD_F0:RW:16:6 */ 1233 mmio_clrsetbits_32(PI_REG(i, 160), 0x3f << 16, 1234 pdram_timing->tmrd << 16); 1235 /*PI_160 PI_TDQSCK_MAX_F0:RW:0:4 */ 1236 mmio_clrsetbits_32(PI_REG(i, 160), 0xf, 1237 pdram_timing->tdqsck_max); 1238 /* PI_187 PI_TDFI_CTRLUPD_MAX_F0:RW:8:16 */ 1239 mmio_clrsetbits_32(PI_REG(i, 187), 0xffff << 8, 1240 (2 * pdram_timing->trefi) << 8); 1241 /* PI_188 PI_TDFI_CTRLUPD_INTERVAL_F0:RW:0:32 */ 1242 mmio_clrsetbits_32(PI_REG(i, 188), 0xffffffff, 1243 20 * pdram_timing->trefi); 1244 } 1245 } 1246 1247 static void gen_rk3399_pi_params_f1(struct timing_related_config *timing_config, 1248 struct dram_timing_t *pdram_timing) 1249 { 1250 uint32_t tmp, tmp1, tmp2; 1251 uint32_t i; 1252 1253 for (i = 0; i < timing_config->ch_cnt; i++) { 1254 /* PI_04 PI_TDFI_PHYMSTR_MAX_F1:RW:0:32 */ 1255 tmp = 4 * pdram_timing->trefi; 1256 mmio_write_32(PI_REG(i, 4), tmp); 1257 /* PI_05 PI_TDFI_PHYMSTR_RESP_F1:RW:0:16 */ 1258 tmp = 2 * pdram_timing->trefi; 1259 mmio_clrsetbits_32(PI_REG(i, 5), 0xffff, tmp); 1260 /* PI_12 PI_TDFI_PHYUPD_RESP_F1:RW:0:16 */ 1261 mmio_clrsetbits_32(PI_REG(i, 12), 0xffff, tmp); 1262 1263 /* PI_42 PI_TDELAY_RDWR_2_BUS_IDLE_F1:RW:8:8 */ 1264 if (timing_config->dram_type == LPDDR4) 1265 tmp = 2; 1266 else 1267 tmp = 0; 1268 tmp = (pdram_timing->bl / 2) + 4 + 1269 (get_pi_rdlat_adj(pdram_timing) - 2) + tmp + 1270 get_pi_tdfi_phy_rdlat(pdram_timing, timing_config); 1271 mmio_clrsetbits_32(PI_REG(i, 42), 0xff << 8, tmp << 8); 1272 /* PI_43 PI_WRLAT_F1:RW:24:5 */ 1273 if (timing_config->dram_type == LPDDR3) { 1274 tmp = get_pi_wrlat(pdram_timing, timing_config); 1275 mmio_clrsetbits_32(PI_REG(i, 43), 0x1f << 24, 1276 tmp << 24); 1277 } 1278 /* PI_44 PI_ADDITIVE_LAT_F1:RW:0:6 */ 1279 mmio_clrsetbits_32(PI_REG(i, 44), 0x3f, PI_ADD_LATENCY); 1280 /* PI_44 PI_CASLAT_LIN_F1:RW:8:7:=0x18 */ 1281 mmio_clrsetbits_32(PI_REG(i, 44), 0x7f << 8, 1282 pdram_timing->cl * 2); 1283 /* PI_47 PI_TREF_F1:RW:16:16 */ 1284 mmio_clrsetbits_32(PI_REG(i, 47), 0xffff << 16, 1285 pdram_timing->trefi << 16); 1286 /* PI_47 PI_TRFC_F1:RW:0:10 */ 1287 mmio_clrsetbits_32(PI_REG(i, 47), 0x3ff, pdram_timing->trfc); 1288 /* PI_67 PI_TODTL_2CMD_F1:RW:8:8 */ 1289 if (timing_config->dram_type == LPDDR3) { 1290 tmp = get_pi_todtoff_max(pdram_timing, timing_config); 1291 mmio_clrsetbits_32(PI_REG(i, 67), 0xff << 8, tmp << 8); 1292 } 1293 /* PI_72 PI_WR_TO_ODTH_F1:RW:24:6 */ 1294 if ((timing_config->dram_type == LPDDR3) || 1295 (timing_config->dram_type == LPDDR4)) { 1296 tmp1 = get_pi_wrlat(pdram_timing, timing_config); 1297 tmp2 = get_pi_todtoff_max(pdram_timing, timing_config); 1298 if (tmp1 > tmp2) 1299 tmp = tmp1 - tmp2; 1300 else 1301 tmp = 0; 1302 } else if (timing_config->dram_type == DDR3) { 1303 tmp = 0; 1304 } 1305 mmio_clrsetbits_32(PI_REG(i, 72), 0x3f << 24, tmp << 24); 1306 /* PI_73 PI_RD_TO_ODTH_F1:RW:16:6 */ 1307 if ((timing_config->dram_type == LPDDR3) || 1308 (timing_config->dram_type == LPDDR4)) { 1309 /* min_rl_preamble = cl + TDQSCK_MIN - 1 */ 1310 tmp1 = pdram_timing->cl + 1311 get_pi_todtoff_min(pdram_timing, timing_config); 1312 tmp1--; 1313 /* todtoff_max */ 1314 tmp2 = get_pi_todtoff_max(pdram_timing, timing_config); 1315 if (tmp1 > tmp2) 1316 tmp = tmp1 - tmp2; 1317 else 1318 tmp = 0; 1319 } else if (timing_config->dram_type == DDR3) 1320 tmp = pdram_timing->cl - pdram_timing->cwl; 1321 1322 mmio_clrsetbits_32(PI_REG(i, 73), 0x3f << 16, tmp << 16); 1323 /*P I_89 PI_RDLAT_ADJ_F1:RW:24:8 */ 1324 tmp = get_pi_rdlat_adj(pdram_timing); 1325 mmio_clrsetbits_32(PI_REG(i, 89), 0xff << 24, tmp << 24); 1326 /* PI_90 PI_WRLAT_ADJ_F1:RW:24:8 */ 1327 tmp = get_pi_wrlat_adj(pdram_timing, timing_config); 1328 mmio_clrsetbits_32(PI_REG(i, 90), 0xff << 24, tmp << 24); 1329 /* PI_91 PI_TDFI_WRCSLAT_F1:RW:24:8 */ 1330 tmp1 = tmp; 1331 if (tmp1 == 0) 1332 tmp = 0; 1333 else if (tmp1 < 5) 1334 tmp = tmp1 - 1; 1335 else 1336 tmp = tmp1 - 5; 1337 mmio_clrsetbits_32(PI_REG(i, 91), 0xff << 24, tmp << 24); 1338 /*PI_96 PI_TDFI_CALVL_CAPTURE_F1:RW:16:10 */ 1339 /* tadr=20ns */ 1340 tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1; 1341 if ((20000 % (1000000 / pdram_timing->mhz)) != 0) 1342 tmp1++; 1343 tmp = (tmp1 >> 1) + (tmp1 % 2) + 5; 1344 mmio_clrsetbits_32(PI_REG(i, 96), 0x3ff << 16, tmp << 16); 1345 /* PI_96 PI_TDFI_CALVL_CC_F1:RW:0:10 */ 1346 tmp = tmp + 18; 1347 mmio_clrsetbits_32(PI_REG(i, 96), 0x3ff, tmp); 1348 /*PI_103 PI_TMRZ_F1:RW:0:5 */ 1349 mmio_clrsetbits_32(PI_REG(i, 103), 0x1f, pdram_timing->tmrz); 1350 /*PI_111 PI_TDFI_CALVL_STROBE_F1:RW:16:4 */ 1351 /* tds_train=ceil(2/ns) */ 1352 tmp1 = 2 * 1000 / (1000000 / pdram_timing->mhz); 1353 if ((2 * 1000 % (1000000 / pdram_timing->mhz)) != 0) 1354 tmp1++; 1355 /* pi_tdfi_calvl_strobe=tds_train+5 */ 1356 tmp = tmp1 + 5; 1357 mmio_clrsetbits_32(PI_REG(i, 111), 0xf << 16, 1358 tmp << 16); 1359 /* PI_116 PI_TCKEHDQS_F1:RW:24:6 */ 1360 tmp = 10000 / (1000000 / pdram_timing->mhz); 1361 if ((10000 % (1000000 / pdram_timing->mhz)) != 0) 1362 tmp++; 1363 if (pdram_timing->mhz <= 100) 1364 tmp = tmp + 1; 1365 else 1366 tmp = tmp + 8; 1367 mmio_clrsetbits_32(PI_REG(i, 116), 0x3f << 24, 1368 tmp << 24); 1369 /* PI_128 PI_MR1_DATA_F1_0:RW+:0:16 */ 1370 mmio_clrsetbits_32(PI_REG(i, 128), 0xffff, pdram_timing->mr[1]); 1371 /* PI_135 PI_MR1_DATA_F1_1:RW+:8:16 */ 1372 mmio_clrsetbits_32(PI_REG(i, 135), 0xffff << 8, 1373 pdram_timing->mr[1] << 8); 1374 /* PI_143 PI_MR1_DATA_F1_2:RW+:0:16 */ 1375 mmio_clrsetbits_32(PI_REG(i, 143), 0xffff, pdram_timing->mr[1]); 1376 /* PI_150 PI_MR1_DATA_F1_3:RW+:8:16 */ 1377 mmio_clrsetbits_32(PI_REG(i, 150), 0xffff << 8, 1378 pdram_timing->mr[1] << 8); 1379 /* PI_128 PI_MR2_DATA_F1_0:RW+:16:16 */ 1380 mmio_clrsetbits_32(PI_REG(i, 128), 0xffff << 16, 1381 pdram_timing->mr[2] << 16); 1382 /* PI_136 PI_MR2_DATA_F1_1:RW+:0:16 */ 1383 mmio_clrsetbits_32(PI_REG(i, 136), 0xffff, pdram_timing->mr[2]); 1384 /* PI_143 PI_MR2_DATA_F1_2:RW+:16:16 */ 1385 mmio_clrsetbits_32(PI_REG(i, 143), 0xffff << 16, 1386 pdram_timing->mr[2] << 16); 1387 /* PI_151 PI_MR2_DATA_F1_3:RW+:0:16 */ 1388 mmio_clrsetbits_32(PI_REG(i, 151), 0xffff, pdram_timing->mr[2]); 1389 /* PI_156 PI_TFC_F1:RW:16:10 */ 1390 mmio_clrsetbits_32(PI_REG(i, 156), 0x3ff << 16, 1391 pdram_timing->trfc << 16); 1392 /* PI_162 PI_TWR_F1:RW:8:6 */ 1393 mmio_clrsetbits_32(PI_REG(i, 162), 0x3f << 8, 1394 pdram_timing->twr << 8); 1395 /* PI_162 PI_TWTR_F1:RW:0:6 */ 1396 mmio_clrsetbits_32(PI_REG(i, 162), 0x3f, pdram_timing->twtr); 1397 /* PI_161 PI_TRCD_F1:RW:24:8 */ 1398 mmio_clrsetbits_32(PI_REG(i, 161), 0xff << 24, 1399 pdram_timing->trcd << 24); 1400 /* PI_161 PI_TRP_F1:RW:16:8 */ 1401 mmio_clrsetbits_32(PI_REG(i, 161), 0xff << 16, 1402 pdram_timing->trp << 16); 1403 /* PI_161 PI_TRTP_F1:RW:8:8 */ 1404 mmio_clrsetbits_32(PI_REG(i, 161), 0xff << 8, 1405 pdram_timing->trtp << 8); 1406 /* PI_163 PI_TRAS_MIN_F1:RW:24:8 */ 1407 mmio_clrsetbits_32(PI_REG(i, 163), 0xff << 24, 1408 pdram_timing->tras_min << 24); 1409 /* PI_163 PI_TRAS_MAX_F1:RW:0:17 */ 1410 mmio_clrsetbits_32(PI_REG(i, 163), 0x1ffff, 1411 pdram_timing->tras_max * 99 / 100); 1412 /* PI_164 PI_TMRD_F1:RW:16:6 */ 1413 mmio_clrsetbits_32(PI_REG(i, 164), 0x3f << 16, 1414 pdram_timing->tmrd << 16); 1415 /* PI_164 PI_TDQSCK_MAX_F1:RW:0:4 */ 1416 mmio_clrsetbits_32(PI_REG(i, 164), 0xf, 1417 pdram_timing->tdqsck_max); 1418 /* PI_189 PI_TDFI_CTRLUPD_MAX_F1:RW:0:16 */ 1419 mmio_clrsetbits_32(PI_REG(i, 189), 0xffff, 1420 2 * pdram_timing->trefi); 1421 /* PI_190 PI_TDFI_CTRLUPD_INTERVAL_F1:RW:0:32 */ 1422 mmio_clrsetbits_32(PI_REG(i, 190), 0xffffffff, 1423 20 * pdram_timing->trefi); 1424 } 1425 } 1426 1427 static void gen_rk3399_pi_params(struct timing_related_config *timing_config, 1428 struct dram_timing_t *pdram_timing, 1429 uint32_t fn) 1430 { 1431 if (fn == 0) 1432 gen_rk3399_pi_params_f0(timing_config, pdram_timing); 1433 else 1434 gen_rk3399_pi_params_f1(timing_config, pdram_timing); 1435 1436 #if PI_TRAINING 1437 uint32_t i; 1438 1439 for (i = 0; i < timing_config->ch_cnt; i++) { 1440 #if EN_READ_GATE_TRAINING 1441 mmio_clrsetbits_32(PI_REG(i, 80), 3 << 24, 2 << 24); 1442 #endif 1443 1444 #if EN_CA_TRAINING 1445 mmio_clrsetbits_32(PI_REG(i, 100), 3 << 8, 2 << 8); 1446 #endif 1447 1448 #if EN_WRITE_LEVELING 1449 mmio_clrsetbits_32(PI_REG(i, 60), 3 << 8, 2 << 8); 1450 #endif 1451 1452 #if EN_READ_LEVELING 1453 mmio_clrsetbits_32(PI_REG(i, 80), 3 << 16, 2 << 16); 1454 #endif 1455 1456 #if EN_WDQ_LEVELING 1457 mmio_clrsetbits_32(PI_REG(i, 124), 3 << 16, 2 << 16); 1458 #endif 1459 } 1460 #endif 1461 } 1462 1463 static void gen_rk3399_set_odt(uint32_t odt_en) 1464 { 1465 uint32_t drv_odt_val; 1466 uint32_t i; 1467 1468 for (i = 0; i < rk3399_dram_status.timing_config.ch_cnt; i++) { 1469 drv_odt_val = (odt_en | (0 << 1) | (0 << 2)) << 16; 1470 mmio_clrsetbits_32(PHY_REG(i, 5), 0x7 << 16, drv_odt_val); 1471 mmio_clrsetbits_32(PHY_REG(i, 133), 0x7 << 16, drv_odt_val); 1472 mmio_clrsetbits_32(PHY_REG(i, 261), 0x7 << 16, drv_odt_val); 1473 mmio_clrsetbits_32(PHY_REG(i, 389), 0x7 << 16, drv_odt_val); 1474 drv_odt_val = (odt_en | (0 << 1) | (0 << 2)) << 24; 1475 mmio_clrsetbits_32(PHY_REG(i, 6), 0x7 << 24, drv_odt_val); 1476 mmio_clrsetbits_32(PHY_REG(i, 134), 0x7 << 24, drv_odt_val); 1477 mmio_clrsetbits_32(PHY_REG(i, 262), 0x7 << 24, drv_odt_val); 1478 mmio_clrsetbits_32(PHY_REG(i, 390), 0x7 << 24, drv_odt_val); 1479 } 1480 } 1481 1482 static void gen_rk3399_phy_params(struct timing_related_config *timing_config, 1483 struct drv_odt_lp_config *drv_config, 1484 struct dram_timing_t *pdram_timing, 1485 uint32_t fn) 1486 { 1487 uint32_t tmp, i, div, j; 1488 uint32_t mem_delay_ps, pad_delay_ps, total_delay_ps, delay_frac_ps; 1489 uint32_t trpre_min_ps, gate_delay_ps, gate_delay_frac_ps; 1490 uint32_t ie_enable, tsel_enable, cas_lat, rddata_en_ie_dly, tsel_adder; 1491 uint32_t extra_adder, delta, hs_offset; 1492 1493 for (i = 0; i < timing_config->ch_cnt; i++) { 1494 1495 pad_delay_ps = PI_PAD_DELAY_PS_VALUE; 1496 ie_enable = PI_IE_ENABLE_VALUE; 1497 tsel_enable = PI_TSEL_ENABLE_VALUE; 1498 1499 mmio_clrsetbits_32(PHY_REG(i, 896), (0x3 << 8) | 1, fn << 8); 1500 1501 /* PHY_LOW_FREQ_SEL */ 1502 /* DENALI_PHY_913 1bit offset_0 */ 1503 if (timing_config->freq > 400) 1504 mmio_clrbits_32(PHY_REG(i, 913), 1); 1505 else 1506 mmio_setbits_32(PHY_REG(i, 913), 1); 1507 1508 /* PHY_RPTR_UPDATE_x */ 1509 /* DENALI_PHY_87/215/343/471 4bit offset_16 */ 1510 tmp = 2500 / (1000000 / pdram_timing->mhz) + 3; 1511 if ((2500 % (1000000 / pdram_timing->mhz)) != 0) 1512 tmp++; 1513 mmio_clrsetbits_32(PHY_REG(i, 87), 0xf << 16, tmp << 16); 1514 mmio_clrsetbits_32(PHY_REG(i, 215), 0xf << 16, tmp << 16); 1515 mmio_clrsetbits_32(PHY_REG(i, 343), 0xf << 16, tmp << 16); 1516 mmio_clrsetbits_32(PHY_REG(i, 471), 0xf << 16, tmp << 16); 1517 1518 /* PHY_PLL_CTRL */ 1519 /* DENALI_PHY_911 13bits offset_0 */ 1520 /* PHY_LP4_BOOT_PLL_CTRL */ 1521 /* DENALI_PHY_919 13bits offset_0 */ 1522 if (pdram_timing->mhz <= 150) 1523 tmp = 3; 1524 else if (pdram_timing->mhz <= 300) 1525 tmp = 2; 1526 else if (pdram_timing->mhz <= 600) 1527 tmp = 1; 1528 else 1529 tmp = 0; 1530 tmp = (1 << 12) | (tmp << 9) | (2 << 7) | (1 << 1); 1531 mmio_clrsetbits_32(PHY_REG(i, 911), 0x1fff, tmp); 1532 mmio_clrsetbits_32(PHY_REG(i, 919), 0x1fff, tmp); 1533 1534 /* PHY_PLL_CTRL_CA */ 1535 /* DENALI_PHY_911 13bits offset_16 */ 1536 /* PHY_LP4_BOOT_PLL_CTRL_CA */ 1537 /* DENALI_PHY_919 13bits offset_16 */ 1538 if (pdram_timing->mhz <= 150) 1539 tmp = 3; 1540 else if (pdram_timing->mhz <= 300) 1541 tmp = 2; 1542 else if (pdram_timing->mhz <= 600) 1543 tmp = 1; 1544 else 1545 tmp = 0; 1546 tmp = (tmp << 9) | (2 << 7) | (1 << 5) | (1 << 1); 1547 mmio_clrsetbits_32(PHY_REG(i, 911), 0x1fff << 16, tmp << 16); 1548 mmio_clrsetbits_32(PHY_REG(i, 919), 0x1fff << 16, tmp << 16); 1549 1550 /* PHY_TCKSRE_WAIT */ 1551 /* DENALI_PHY_922 4bits offset_24 */ 1552 if (pdram_timing->mhz <= 400) 1553 tmp = 1; 1554 else if (pdram_timing->mhz <= 800) 1555 tmp = 3; 1556 else if (pdram_timing->mhz <= 1000) 1557 tmp = 4; 1558 else 1559 tmp = 5; 1560 mmio_clrsetbits_32(PHY_REG(i, 922), 0xf << 24, tmp << 24); 1561 /* PHY_CAL_CLK_SELECT_0:RW8:3 */ 1562 div = pdram_timing->mhz / (2 * 20); 1563 for (j = 2, tmp = 1; j <= 128; j <<= 1, tmp++) { 1564 if (div < j) 1565 break; 1566 } 1567 mmio_clrsetbits_32(PHY_REG(i, 947), 0x7 << 8, tmp << 8); 1568 mmio_setbits_32(PHY_REG(i, 927), (1 << 22)); 1569 1570 if (timing_config->dram_type == DDR3) { 1571 mem_delay_ps = 0; 1572 trpre_min_ps = 1000; 1573 } else if (timing_config->dram_type == LPDDR4) { 1574 mem_delay_ps = 1500; 1575 trpre_min_ps = 900; 1576 } else if (timing_config->dram_type == LPDDR3) { 1577 mem_delay_ps = 2500; 1578 trpre_min_ps = 900; 1579 } else { 1580 ERROR("gen_rk3399_phy_params:dramtype unsupport\n"); 1581 return; 1582 } 1583 total_delay_ps = mem_delay_ps + pad_delay_ps; 1584 delay_frac_ps = 1000 * total_delay_ps / 1585 (1000000 / pdram_timing->mhz); 1586 gate_delay_ps = delay_frac_ps + 1000 - (trpre_min_ps / 2); 1587 gate_delay_frac_ps = gate_delay_ps % 1000; 1588 tmp = gate_delay_frac_ps * 0x200 / 1000; 1589 /* PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY */ 1590 /* DENALI_PHY_2/130/258/386 10bits offset_0 */ 1591 mmio_clrsetbits_32(PHY_REG(i, 2), 0x2ff, tmp); 1592 mmio_clrsetbits_32(PHY_REG(i, 130), 0x2ff, tmp); 1593 mmio_clrsetbits_32(PHY_REG(i, 258), 0x2ff, tmp); 1594 mmio_clrsetbits_32(PHY_REG(i, 386), 0x2ff, tmp); 1595 /* PHY_RDDQS_GATE_SLAVE_DELAY */ 1596 /* DENALI_PHY_77/205/333/461 10bits offset_16 */ 1597 mmio_clrsetbits_32(PHY_REG(i, 77), 0x2ff << 16, tmp << 16); 1598 mmio_clrsetbits_32(PHY_REG(i, 205), 0x2ff << 16, tmp << 16); 1599 mmio_clrsetbits_32(PHY_REG(i, 333), 0x2ff << 16, tmp << 16); 1600 mmio_clrsetbits_32(PHY_REG(i, 461), 0x2ff << 16, tmp << 16); 1601 1602 tmp = gate_delay_ps / 1000; 1603 /* PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST */ 1604 /* DENALI_PHY_10/138/266/394 4bit offset_0 */ 1605 mmio_clrsetbits_32(PHY_REG(i, 10), 0xf, tmp); 1606 mmio_clrsetbits_32(PHY_REG(i, 138), 0xf, tmp); 1607 mmio_clrsetbits_32(PHY_REG(i, 266), 0xf, tmp); 1608 mmio_clrsetbits_32(PHY_REG(i, 394), 0xf, tmp); 1609 /* PHY_RDDQS_LATENCY_ADJUST */ 1610 /* DENALI_PHY_78/206/334/462 4bits offset_0 */ 1611 mmio_clrsetbits_32(PHY_REG(i, 78), 0xf, tmp); 1612 mmio_clrsetbits_32(PHY_REG(i, 206), 0xf, tmp); 1613 mmio_clrsetbits_32(PHY_REG(i, 334), 0xf, tmp); 1614 mmio_clrsetbits_32(PHY_REG(i, 462), 0xf, tmp); 1615 /* PHY_GTLVL_LAT_ADJ_START */ 1616 /* DENALI_PHY_80/208/336/464 4bits offset_16 */ 1617 tmp = delay_frac_ps / 1000; 1618 mmio_clrsetbits_32(PHY_REG(i, 80), 0xf << 16, tmp << 16); 1619 mmio_clrsetbits_32(PHY_REG(i, 208), 0xf << 16, tmp << 16); 1620 mmio_clrsetbits_32(PHY_REG(i, 336), 0xf << 16, tmp << 16); 1621 mmio_clrsetbits_32(PHY_REG(i, 464), 0xf << 16, tmp << 16); 1622 1623 cas_lat = pdram_timing->cl + PI_ADD_LATENCY; 1624 rddata_en_ie_dly = ie_enable / (1000000 / pdram_timing->mhz); 1625 if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0) 1626 rddata_en_ie_dly++; 1627 rddata_en_ie_dly = rddata_en_ie_dly - 1; 1628 tsel_adder = tsel_enable / (1000000 / pdram_timing->mhz); 1629 if ((tsel_enable % (1000000 / pdram_timing->mhz)) != 0) 1630 tsel_adder++; 1631 if (rddata_en_ie_dly > tsel_adder) 1632 extra_adder = rddata_en_ie_dly - tsel_adder; 1633 else 1634 extra_adder = 0; 1635 delta = cas_lat - rddata_en_ie_dly; 1636 if (PI_REGS_DIMM_SUPPORT && PI_DOUBLEFREEK) 1637 hs_offset = 2; 1638 else 1639 hs_offset = 1; 1640 if (rddata_en_ie_dly > (cas_lat - 1 - hs_offset)) 1641 tmp = 0; 1642 else if ((delta == 2) || (delta == 1)) 1643 tmp = rddata_en_ie_dly - 0 - extra_adder; 1644 else 1645 tmp = extra_adder; 1646 /* PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY */ 1647 /* DENALI_PHY_9/137/265/393 4bit offset_16 */ 1648 mmio_clrsetbits_32(PHY_REG(i, 9), 0xf << 16, tmp << 16); 1649 mmio_clrsetbits_32(PHY_REG(i, 137), 0xf << 16, tmp << 16); 1650 mmio_clrsetbits_32(PHY_REG(i, 265), 0xf << 16, tmp << 16); 1651 mmio_clrsetbits_32(PHY_REG(i, 393), 0xf << 16, tmp << 16); 1652 /* PHY_RDDATA_EN_TSEL_DLY */ 1653 /* DENALI_PHY_86/214/342/470 4bit offset_0 */ 1654 mmio_clrsetbits_32(PHY_REG(i, 86), 0xf, tmp); 1655 mmio_clrsetbits_32(PHY_REG(i, 214), 0xf, tmp); 1656 mmio_clrsetbits_32(PHY_REG(i, 342), 0xf, tmp); 1657 mmio_clrsetbits_32(PHY_REG(i, 470), 0xf, tmp); 1658 1659 if (tsel_adder > rddata_en_ie_dly) 1660 extra_adder = tsel_adder - rddata_en_ie_dly; 1661 else 1662 extra_adder = 0; 1663 if (rddata_en_ie_dly > (cas_lat - 1 - hs_offset)) 1664 tmp = tsel_adder; 1665 else 1666 tmp = rddata_en_ie_dly - 0 + extra_adder; 1667 /* PHY_LP4_BOOT_RDDATA_EN_DLY */ 1668 /* DENALI_PHY_9/137/265/393 4bit offset_8 */ 1669 mmio_clrsetbits_32(PHY_REG(i, 9), 0xf << 8, tmp << 8); 1670 mmio_clrsetbits_32(PHY_REG(i, 137), 0xf << 8, tmp << 8); 1671 mmio_clrsetbits_32(PHY_REG(i, 265), 0xf << 8, tmp << 8); 1672 mmio_clrsetbits_32(PHY_REG(i, 393), 0xf << 8, tmp << 8); 1673 /* PHY_RDDATA_EN_DLY */ 1674 /* DENALI_PHY_85/213/341/469 4bit offset_24 */ 1675 mmio_clrsetbits_32(PHY_REG(i, 85), 0xf << 24, tmp << 24); 1676 mmio_clrsetbits_32(PHY_REG(i, 213), 0xf << 24, tmp << 24); 1677 mmio_clrsetbits_32(PHY_REG(i, 341), 0xf << 24, tmp << 24); 1678 mmio_clrsetbits_32(PHY_REG(i, 469), 0xf << 24, tmp << 24); 1679 1680 if (pdram_timing->mhz <= ENPER_CS_TRAINING_FREQ) { 1681 /* 1682 * Note:Per-CS Training is not compatible at speeds 1683 * under 533 MHz. If the PHY is running at a speed 1684 * less than 533MHz, all phy_per_cs_training_en_X 1685 * parameters must be cleared to 0. 1686 */ 1687 1688 /*DENALI_PHY_84/212/340/468 1bit offset_16 */ 1689 mmio_clrbits_32(PHY_REG(i, 84), 0x1 << 16); 1690 mmio_clrbits_32(PHY_REG(i, 212), 0x1 << 16); 1691 mmio_clrbits_32(PHY_REG(i, 340), 0x1 << 16); 1692 mmio_clrbits_32(PHY_REG(i, 468), 0x1 << 16); 1693 } else { 1694 mmio_setbits_32(PHY_REG(i, 84), 0x1 << 16); 1695 mmio_setbits_32(PHY_REG(i, 212), 0x1 << 16); 1696 mmio_setbits_32(PHY_REG(i, 340), 0x1 << 16); 1697 mmio_setbits_32(PHY_REG(i, 468), 0x1 << 16); 1698 } 1699 } 1700 } 1701 1702 static int to_get_clk_index(unsigned int mhz) 1703 { 1704 int pll_cnt, i; 1705 1706 pll_cnt = ARRAY_SIZE(dpll_rates_table); 1707 1708 /* Assumming rate_table is in descending order */ 1709 for (i = 0; i < pll_cnt; i++) { 1710 if (mhz >= dpll_rates_table[i].mhz) 1711 break; 1712 } 1713 1714 /* if mhz lower than lowest frequency in table, use lowest frequency */ 1715 if (i == pll_cnt) 1716 i = pll_cnt - 1; 1717 1718 return i; 1719 } 1720 1721 uint32_t rkclk_prepare_pll_timing(unsigned int mhz) 1722 { 1723 unsigned int refdiv, postdiv1, fbdiv, postdiv2; 1724 int index; 1725 1726 index = to_get_clk_index(mhz); 1727 refdiv = dpll_rates_table[index].refdiv; 1728 fbdiv = dpll_rates_table[index].fbdiv; 1729 postdiv1 = dpll_rates_table[index].postdiv1; 1730 postdiv2 = dpll_rates_table[index].postdiv2; 1731 mmio_write_32(DCF_PARAM_ADDR + PARAM_DPLL_CON0, FBDIV(fbdiv)); 1732 mmio_write_32(DCF_PARAM_ADDR + PARAM_DPLL_CON1, 1733 POSTDIV2(postdiv2) | POSTDIV1(postdiv1) | REFDIV(refdiv)); 1734 return (24 * fbdiv) / refdiv / postdiv1 / postdiv2; 1735 } 1736 1737 uint32_t ddr_get_rate(void) 1738 { 1739 uint32_t refdiv, postdiv1, fbdiv, postdiv2; 1740 1741 refdiv = mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1)) & 0x3f; 1742 fbdiv = mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 0)) & 0xfff; 1743 postdiv1 = 1744 (mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1)) >> 8) & 0x7; 1745 postdiv2 = 1746 (mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1)) >> 12) & 0x7; 1747 1748 return (24 / refdiv * fbdiv / postdiv1 / postdiv2) * 1000 * 1000; 1749 } 1750 1751 /* 1752 * return: bit12: channel 1, external self-refresh 1753 * bit11: channel 1, stdby_mode 1754 * bit10: channel 1, self-refresh with controller and memory clock gate 1755 * bit9: channel 1, self-refresh 1756 * bit8: channel 1, power-down 1757 * 1758 * bit4: channel 1, external self-refresh 1759 * bit3: channel 0, stdby_mode 1760 * bit2: channel 0, self-refresh with controller and memory clock gate 1761 * bit1: channel 0, self-refresh 1762 * bit0: channel 0, power-down 1763 */ 1764 uint32_t exit_low_power(void) 1765 { 1766 uint32_t low_power = 0; 1767 uint32_t channel_mask; 1768 uint32_t tmp, i; 1769 1770 channel_mask = (mmio_read_32(PMUGRF_BASE + PMUGRF_OSREG(2)) >> 28) & 1771 0x3; 1772 for (i = 0; i < 2; i++) { 1773 if (!(channel_mask & (1 << i))) 1774 continue; 1775 1776 /* exit stdby mode */ 1777 mmio_write_32(CIC_BASE + CIC_CTRL1, 1778 (1 << (i + 16)) | (0 << i)); 1779 /* exit external self-refresh */ 1780 tmp = i ? 12 : 8; 1781 low_power |= ((mmio_read_32(PMU_BASE + PMU_SFT_CON) >> tmp) & 1782 0x1) << (4 + 8 * i); 1783 mmio_clrbits_32(PMU_BASE + PMU_SFT_CON, 1 << tmp); 1784 while (!(mmio_read_32(PMU_BASE + PMU_DDR_SREF_ST) & (1 << i))) 1785 ; 1786 /* exit auto low-power */ 1787 mmio_clrbits_32(CTL_REG(i, 101), 0x7); 1788 /* lp_cmd to exit */ 1789 if (((mmio_read_32(CTL_REG(i, 100)) >> 24) & 0x7f) != 1790 0x40) { 1791 while (mmio_read_32(CTL_REG(i, 200)) & 0x1) 1792 ; 1793 mmio_clrsetbits_32(CTL_REG(i, 93), 0xff << 24, 1794 0x69 << 24); 1795 while (((mmio_read_32(CTL_REG(i, 100)) >> 24) & 0x7f) != 1796 0x40) 1797 ; 1798 } 1799 } 1800 return low_power; 1801 } 1802 1803 void resume_low_power(uint32_t low_power) 1804 { 1805 uint32_t channel_mask; 1806 uint32_t tmp, i, val; 1807 1808 channel_mask = (mmio_read_32(PMUGRF_BASE + PMUGRF_OSREG(2)) >> 28) & 1809 0x3; 1810 for (i = 0; i < 2; i++) { 1811 if (!(channel_mask & (1 << i))) 1812 continue; 1813 1814 /* resume external self-refresh */ 1815 tmp = i ? 12 : 8; 1816 val = (low_power >> (4 + 8 * i)) & 0x1; 1817 mmio_setbits_32(PMU_BASE + PMU_SFT_CON, val << tmp); 1818 /* resume auto low-power */ 1819 val = (low_power >> (8 * i)) & 0x7; 1820 mmio_setbits_32(CTL_REG(i, 101), val); 1821 /* resume stdby mode */ 1822 val = (low_power >> (3 + 8 * i)) & 0x1; 1823 mmio_write_32(CIC_BASE + CIC_CTRL1, 1824 (1 << (i + 16)) | (val << i)); 1825 } 1826 } 1827 1828 static void wait_dcf_done(void) 1829 { 1830 while ((mmio_read_32(DCF_BASE + DCF_DCF_ISR) & (DCF_DONE)) == 0) 1831 continue; 1832 } 1833 1834 void clr_dcf_irq(void) 1835 { 1836 /* clear dcf irq status */ 1837 mmio_write_32(DCF_BASE + DCF_DCF_ISR, DCF_TIMEOUT | DCF_ERR | DCF_DONE); 1838 } 1839 1840 static void enable_dcf(uint32_t dcf_addr) 1841 { 1842 /* config DCF start addr */ 1843 mmio_write_32(DCF_BASE + DCF_DCF_ADDR, dcf_addr); 1844 /* wait dcf done */ 1845 while (mmio_read_32(DCF_BASE + DCF_DCF_CTRL) & 1) 1846 continue; 1847 /* clear dcf irq status */ 1848 mmio_write_32(DCF_BASE + DCF_DCF_ISR, DCF_TIMEOUT | DCF_ERR | DCF_DONE); 1849 /* DCF start */ 1850 mmio_setbits_32(DCF_BASE + DCF_DCF_CTRL, DCF_START); 1851 } 1852 1853 static void dcf_start(uint32_t freq, uint32_t index) 1854 { 1855 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 1856 (0x1 << (1 + 16)) | (1 << 1)); 1857 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(11), 1858 (0x1 << (0 + 16)) | (1 << 0)); 1859 mmio_write_32(DCF_PARAM_ADDR + PARAM_FREQ_SELECT, index << 4); 1860 1861 mmio_write_32(DCF_PARAM_ADDR + PARAM_DRAM_FREQ, freq); 1862 1863 rkclk_prepare_pll_timing(freq); 1864 udelay(10); 1865 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 1866 (0x1 << (1 + 16)) | (0 << 1)); 1867 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(11), 1868 (0x1 << (0 + 16)) | (0 << 0)); 1869 udelay(10); 1870 enable_dcf(DCF_START_ADDR); 1871 } 1872 1873 static void dram_low_power_config(void) 1874 { 1875 uint32_t tmp, i; 1876 uint32_t ch_cnt = rk3399_dram_status.timing_config.ch_cnt; 1877 uint32_t dram_type = rk3399_dram_status.timing_config.dram_type; 1878 1879 if (dram_type == DDR3) 1880 tmp = (2 << 16) | (0x7 << 8); 1881 else 1882 tmp = (3 << 16) | (0x7 << 8); 1883 1884 for (i = 0; i < ch_cnt; i++) 1885 mmio_clrsetbits_32(CTL_REG(i, 101), 0x70f0f, tmp); 1886 1887 /* standby idle */ 1888 mmio_write_32(CIC_BASE + CIC_CG_WAIT_TH, 0x640008); 1889 1890 if (ch_cnt == 2) { 1891 mmio_write_32(GRF_BASE + GRF_DDRC1_CON1, 1892 (((0x1<<4) | (0x1<<5) | (0x1<<6) | 1893 (0x1<<7)) << 16) | 1894 ((0x1<<4) | (0x0<<5) | (0x1<<6) | (0x1<<7))); 1895 mmio_write_32(CIC_BASE + CIC_CTRL1, 0x002a0028); 1896 } 1897 1898 mmio_write_32(GRF_BASE + GRF_DDRC0_CON1, 1899 (((0x1<<4) | (0x1<<5) | (0x1<<6) | (0x1<<7)) << 16) | 1900 ((0x1<<4) | (0x0<<5) | (0x1<<6) | (0x1<<7))); 1901 mmio_write_32(CIC_BASE + CIC_CTRL1, 0x00150014); 1902 } 1903 1904 void dram_dfs_init(void) 1905 { 1906 uint32_t trefi0, trefi1; 1907 1908 /* get sdram config for os reg */ 1909 get_dram_drv_odt_val(sdram_config.dramtype, 1910 &rk3399_dram_status.drv_odt_lp_cfg); 1911 sdram_timing_cfg_init(&rk3399_dram_status.timing_config, 1912 &sdram_config, 1913 &rk3399_dram_status.drv_odt_lp_cfg); 1914 1915 trefi0 = ((mmio_read_32(CTL_REG(0, 48)) >> 16) & 0xffff) + 8; 1916 trefi1 = ((mmio_read_32(CTL_REG(0, 49)) >> 16) & 0xffff) + 8; 1917 1918 rk3399_dram_status.index_freq[0] = trefi0 * 10 / 39; 1919 rk3399_dram_status.index_freq[1] = trefi1 * 10 / 39; 1920 rk3399_dram_status.current_index = 1921 (mmio_read_32(CTL_REG(0, 111)) >> 16) & 0x3; 1922 if (rk3399_dram_status.timing_config.dram_type == DDR3) { 1923 rk3399_dram_status.index_freq[0] /= 2; 1924 rk3399_dram_status.index_freq[1] /= 2; 1925 } 1926 rk3399_dram_status.index_freq[(rk3399_dram_status.current_index + 1) 1927 & 0x1] = 0; 1928 dram_low_power_config(); 1929 } 1930 1931 /* 1932 * arg0: bit0-7: sr_idle; bit8-15:sr_mc_gate_idle; bit16-31: standby idle 1933 * arg1: bit0-11: pd_idle; bit 16-27: srpd_lite_idle 1934 * arg2: bit0: if odt en 1935 */ 1936 uint32_t dram_set_odt_pd(uint32_t arg0, uint32_t arg1, uint32_t arg2) 1937 { 1938 struct drv_odt_lp_config *lp_cfg = &rk3399_dram_status.drv_odt_lp_cfg; 1939 uint32_t *low_power = &rk3399_dram_status.low_power_stat; 1940 uint32_t dram_type, ch_count, pd_tmp, sr_tmp, i; 1941 1942 dram_type = rk3399_dram_status.timing_config.dram_type; 1943 ch_count = rk3399_dram_status.timing_config.ch_cnt; 1944 1945 lp_cfg->sr_idle = arg0 & 0xff; 1946 lp_cfg->sr_mc_gate_idle = (arg0 >> 8) & 0xff; 1947 lp_cfg->standby_idle = (arg0 >> 16) & 0xffff; 1948 lp_cfg->pd_idle = arg1 & 0xfff; 1949 lp_cfg->srpd_lite_idle = (arg1 >> 16) & 0xfff; 1950 1951 rk3399_dram_status.timing_config.odt = arg2 & 0x1; 1952 1953 exit_low_power(); 1954 1955 *low_power = 0; 1956 1957 /* pd_idle en */ 1958 if (lp_cfg->pd_idle) 1959 *low_power |= ((1 << 0) | (1 << 8)); 1960 /* sr_idle en srpd_lite_idle */ 1961 if (lp_cfg->sr_idle | lp_cfg->srpd_lite_idle) 1962 *low_power |= ((1 << 1) | (1 << 9)); 1963 /* sr_mc_gate_idle */ 1964 if (lp_cfg->sr_mc_gate_idle) 1965 *low_power |= ((1 << 2) | (1 << 10)); 1966 /* standbyidle */ 1967 if (lp_cfg->standby_idle) { 1968 if (rk3399_dram_status.timing_config.ch_cnt == 2) 1969 *low_power |= ((1 << 3) | (1 << 11)); 1970 else 1971 *low_power |= (1 << 3); 1972 } 1973 1974 pd_tmp = arg1; 1975 if (dram_type != LPDDR4) 1976 pd_tmp = arg1 & 0xfff; 1977 sr_tmp = arg0 & 0xffff; 1978 for (i = 0; i < ch_count; i++) { 1979 mmio_write_32(CTL_REG(i, 102), pd_tmp); 1980 mmio_clrsetbits_32(CTL_REG(i, 103), 0xffff, sr_tmp); 1981 } 1982 mmio_write_32(CIC_BASE + CIC_IDLE_TH, (arg0 >> 16) & 0xffff); 1983 1984 return 0; 1985 } 1986 1987 static uint32_t prepare_ddr_timing(uint32_t mhz) 1988 { 1989 uint32_t index; 1990 struct dram_timing_t dram_timing; 1991 1992 rk3399_dram_status.timing_config.freq = mhz; 1993 1994 if (mhz < 300) 1995 rk3399_dram_status.timing_config.dllbp = 1; 1996 else 1997 rk3399_dram_status.timing_config.dllbp = 0; 1998 1999 if (rk3399_dram_status.timing_config.odt == 1) 2000 gen_rk3399_set_odt(1); 2001 2002 index = (rk3399_dram_status.current_index + 1) & 0x1; 2003 if (rk3399_dram_status.index_freq[index] == mhz) 2004 goto out; 2005 2006 /* 2007 * checking if having available gate traiing timing for 2008 * target freq. 2009 */ 2010 dram_get_parameter(&rk3399_dram_status.timing_config, &dram_timing); 2011 gen_rk3399_ctl_params(&rk3399_dram_status.timing_config, 2012 &dram_timing, index); 2013 gen_rk3399_pi_params(&rk3399_dram_status.timing_config, 2014 &dram_timing, index); 2015 gen_rk3399_phy_params(&rk3399_dram_status.timing_config, 2016 &rk3399_dram_status.drv_odt_lp_cfg, 2017 &dram_timing, index); 2018 rk3399_dram_status.index_freq[index] = mhz; 2019 2020 out: 2021 return index; 2022 } 2023 2024 void print_dram_status_info(void) 2025 { 2026 uint32_t *p; 2027 uint32_t i; 2028 2029 p = (uint32_t *) &rk3399_dram_status.timing_config; 2030 INFO("rk3399_dram_status.timing_config:\n"); 2031 for (i = 0; i < sizeof(struct timing_related_config) / 4; i++) 2032 tf_printf("%u\n", p[i]); 2033 p = (uint32_t *) &rk3399_dram_status.drv_odt_lp_cfg; 2034 INFO("rk3399_dram_status.drv_odt_lp_cfg:\n"); 2035 for (i = 0; i < sizeof(struct drv_odt_lp_config) / 4; i++) 2036 tf_printf("%u\n", p[i]); 2037 } 2038 2039 uint32_t ddr_set_rate(uint32_t hz) 2040 { 2041 uint32_t low_power, index; 2042 uint32_t mhz = hz / (1000 * 1000); 2043 2044 if (mhz == 2045 rk3399_dram_status.index_freq[rk3399_dram_status.current_index]) 2046 goto out; 2047 2048 index = to_get_clk_index(mhz); 2049 mhz = dpll_rates_table[index].mhz; 2050 2051 index = prepare_ddr_timing(mhz); 2052 if (index > 1) 2053 goto out; 2054 2055 dcf_start(mhz, index); 2056 wait_dcf_done(); 2057 if (rk3399_dram_status.timing_config.odt == 0) 2058 gen_rk3399_set_odt(0); 2059 2060 rk3399_dram_status.current_index = index; 2061 low_power = rk3399_dram_status.low_power_stat; 2062 resume_low_power(low_power); 2063 out: 2064 return mhz; 2065 } 2066 2067 uint32_t ddr_round_rate(uint32_t hz) 2068 { 2069 int index; 2070 uint32_t mhz = hz / (1000 * 1000); 2071 2072 index = to_get_clk_index(mhz); 2073 2074 return dpll_rates_table[index].mhz * 1000 * 1000; 2075 } 2076