| d1d06275 | 02-May-2019 |
kenny liang <kenny.liang@mediatek.com> |
mediatek: mt8173: apply MULTI_CONSOLE framework
- Switch uart driver from Mediatek 8250 to TI 16550
- Enable MULTI_CONSOLE
Signed-off-by: kenny liang <kenny.liang@mediatek.com>
Change-Id: Ie3948d9e
mediatek: mt8173: apply MULTI_CONSOLE framework
- Switch uart driver from Mediatek 8250 to TI 16550
- Enable MULTI_CONSOLE
Signed-off-by: kenny liang <kenny.liang@mediatek.com>
Change-Id: Ie3948d9e64d05d29a1f69592792e277b680c4ed4
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| 36305c82 | 12-Sep-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge "Add python configuration for editorconfig" into integration |
| 88b69fcc | 12-Sep-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge "Tegra: memctrl_v2: fix "overflow before widen" coverity issue" into integration |
| f52f73b3 | 12-Sep-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge "Invalidate dcache build option for bl2 entry at EL3" into integration |
| 6a415a50 | 09-Sep-2019 |
Justin Chadwell <justin.chadwell@arm.com> |
Remove RSA PKCS#1 v1.5 support from cert_tool
Support for PKCS#1 v1.5 was deprecated in SHA 1001202 and fully removed
in SHA fe199e3, however, cert_tool is still able to generate
certificates in tha
Remove RSA PKCS#1 v1.5 support from cert_tool
Support for PKCS#1 v1.5 was deprecated in SHA 1001202 and fully removed
in SHA fe199e3, however, cert_tool is still able to generate
certificates in that form. This patch fully removes the ability for
cert_tool to generate these certificates.
Additionally, this patch also fixes a bug where the issuing certificate
was a RSA and the issued certificate was EcDSA. In this case, the issued
certificate would be signed using PKCS#1 v1.5 instead of RSAPSS per
PKCS#1 v2.1, preventing TF-A from verifying the image signatures. Now
that PKCS#1 v1.5 support is removed, all certificates that are signed
with RSA now use the more modern padding scheme.
Change-Id: Id87d7d915be594a1876a73080528d968e65c4e9a
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
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| f29213d9 | 29-Jul-2019 |
Justin Chadwell <justin.chadwell@arm.com> |
Add documentation for new KEY_SIZE option
This patch adds documentation for the new KEY_SIZE build option that is
exposed by cert_create, and instructions on how to use it.
Change-Id: I09b9b052bfde
Add documentation for new KEY_SIZE option
This patch adds documentation for the new KEY_SIZE build option that is
exposed by cert_create, and instructions on how to use it.
Change-Id: I09b9b052bfdeeaca837e0f0026e2b01144f2472c
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
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| dfe0f4c2 | 29-Jul-2019 |
Justin Chadwell <justin.chadwell@arm.com> |
Add cert_create tool support for RSA key sizes
cert_tool is now able to accept a command line option for specifying the
key size. It now supports the following options: 1024, 2048 (default),
3072 an
Add cert_create tool support for RSA key sizes
cert_tool is now able to accept a command line option for specifying the
key size. It now supports the following options: 1024, 2048 (default),
3072 and 4096. This is also modifiable by TFA using the build flag
KEY_SIZE.
Change-Id: Ifadecf84ade3763249ee8cc7123a8178f606f0e5
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
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| aacff749 | 29-Jul-2019 |
Justin Chadwell <justin.chadwell@arm.com> |
Support larger RSA key sizes when using MBEDTLS
Previously, TF-A could not support large RSA key sizes as the
configuration options passed to MBEDTLS prevented storing and performing
calculations wi
Support larger RSA key sizes when using MBEDTLS
Previously, TF-A could not support large RSA key sizes as the
configuration options passed to MBEDTLS prevented storing and performing
calculations with the larger, higher-precision numbers required. With
these changes to the arguments passed to MBEDTLS, TF-A now supports
using 3072 (3K) and 4096 (4K) keys in certificates.
Change-Id: Ib73a6773145d2faa25c28d04f9a42e86f2fd555f
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
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| b90f207a | 20-Aug-2019 |
Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> |
Invalidate dcache build option for bl2 entry at EL3
Some of the platform (ie. Agilex) make use of CCU IPs which will only be
initialized during bl2_el3_early_platform_setup. Any operation to the
cac
Invalidate dcache build option for bl2 entry at EL3
Some of the platform (ie. Agilex) make use of CCU IPs which will only be
initialized during bl2_el3_early_platform_setup. Any operation to the
cache beforehand will crash the platform. Hence, this will provide an
option to skip the data cache invalidation upon bl2 entry at EL3
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I2c924ed0589a72d0034714c31be8fe57237d1f06
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| 2fc6ffc4 | 12-Sep-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge "libc: fix sparse warning for __assert()" into integration |
| 4210af0f | 12-Sep-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge "doc: Updated user guide with new Mbed TLS version number" into integration |
| 8911a32a | 12-Sep-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge "intel: agilex: Fix psci power domain off" into integration |
| 91624b7f | 12-Sep-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "jc/mte_enable" into integration
* changes:
Add documentation for CTX_INCLUDE_MTE_REGS
Enable MTE support in both secure and non-secure worlds |
| 5beeec79 | 12-Sep-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge "plat: xilinx: zynqmp: Initialize IPI table from zynqmp_config_setup()" into integration |
| 18eb0025 | 12-Sep-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge "Zeus: apply the MSR SSBS instruction" into integration |
| 684b3a02 | 12-Sep-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge "Add UBSAN support and handlers" into integration |
| f38e5182 | 12-Sep-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes I072c0f61,I798401f4,I9648ef55,I7225d9fa,Ife682288, ... into integration
* changes:
rcar_gen3: drivers: ddr_b: Update DDR setting for H3, M3, M3N
rcar_gen3: drivers: qos: update QoS
Merge changes I072c0f61,I798401f4,I9648ef55,I7225d9fa,Ife682288, ... into integration
* changes:
rcar_gen3: drivers: ddr_b: Update DDR setting for H3, M3, M3N
rcar_gen3: drivers: qos: update QoS setting
rcar_gen3: drivers: ddr_b: Fix checkpatch errors in headers
rcar_gen3: drivers: ddr_b: Fix line-over-80s
rcar_gen3: drivers: ddr_b: Further checkpatch cleanups
rcar_gen3: drivers: ddr_b: Clean up camel case
rcar_get3: drivers: ddr_b: Basic checkpatch fixes
rcar_get3: drivers: ddr: Partly unify register macros between DDR A and B
rcar_get3: drivers: ddr: Clean up common code
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| 9af73b36 | 12-Sep-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "amlogic-refactoring" into integration
* changes:
amlogic: Fix includes order
amlogic: Fix header guards
amlogic: Fix prefixes in the SoC specific files
amlogic: Fix
Merge changes from topic "amlogic-refactoring" into integration
* changes:
amlogic: Fix includes order
amlogic: Fix header guards
amlogic: Fix prefixes in the SoC specific files
amlogic: Fix prefixes in the PM code
amlogic: Fix prefixes in the SCPI related code
amlogic: Fix prefixes in the MHU code
amlogic: Fix prefixes in the SIP/SVC code
amlogic: Fix prefixes in the thermal driver
amlogic: Fix prefixes in the private header file
amlogic: Fix prefixes in the efuse driver
amlogic: Fix prefixes in the platform macros file
amlogic: Fix prefixes in the helpers file
amlogic: Rework Makefiles
amlogic: Move the SIP SVC code to common directory
amlogic: Move topology file to common directory
amlogic: Move thermal code to common directory
amlogic: Move MHU code to common directory
amlogic: Move efuse code to common directory
amlogic: Move platform macros assembly file to common directory
amlogic: Introduce unified private header file
amlogic: Move SCPI code to common directory
amlogic: Move the SHA256 DMA driver to common directory
amlogic: Move assembly helpers to common directory
amlogic: Introduce directory parameters in the makefiles
meson: Rename platform directory to amlogic
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| afac9681 | 12-Sep-2019 |
Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> |
intel: agilex: Fix psci power domain off
Disable gic cpu interface for powered down cpu. This patch also removes
core reset during power off as core reset will be done during power on
Signed-off-by
intel: agilex: Fix psci power domain off
Disable gic cpu interface for powered down cpu. This patch also removes
core reset during power off as core reset will be done during power on
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I2ca96d876b6e71e56d24a9a7e184b6d6226b8673
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| b5621874 | 03-Sep-2019 |
Carlo Caione <ccaione@baylibre.com> |
amlogic: Fix includes order
As part of the code refactoring fix the order of the include files
across all the source files.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: Ice72f687cc
amlogic: Fix includes order
As part of the code refactoring fix the order of the include files
across all the source files.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: Ice72f687cc26ee881a9051168149467688100cfb
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| 421b67b6 | 28-Aug-2019 |
Carlo Caione <ccaione@baylibre.com> |
amlogic: Fix header guards
Make the header guards more generic and contextually remove the
GXBB_BL31_PLAT_PARAM_VAL value that is unused on the GXL platform.
Signed-off-by: Carlo Caione <ccaione@ba
amlogic: Fix header guards
Make the header guards more generic and contextually remove the
GXBB_BL31_PLAT_PARAM_VAL value that is unused on the GXL platform.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: I842fa2e084e71280ae17b39c67877e844821a171
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| 749b3346 | 11-Sep-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge "mbedtls: use #include <...> instead of "..."" into integration |
| cd3c5b4c | 13-Aug-2019 |
John Tsichritzis <john.tsichritzis@arm.com> |
Modify FVP makefile for cores that support both AArch64/32
Some cores support only AArch64 from EL1 and above, e.g. A76, N1 etc. If
TF-A is compiled with CTX_INCLUDE_AARCH32_REGS=0 so as to properly
Modify FVP makefile for cores that support both AArch64/32
Some cores support only AArch64 from EL1 and above, e.g. A76, N1 etc. If
TF-A is compiled with CTX_INCLUDE_AARCH32_REGS=0 so as to properly
handle those cores, only the AArch64 cores' assembly is included in the
TF-A binary. In other words, for FVP, TF-A assumes that AArch64 only
cores will never exist in the same cluster with cores that also support
AArch32.
However, A55 and A75 can be used as AArch64 only cores, despite
supporting AArch32, too. This patch enables A55 and A75 to exist in
clusters together with AArch64 cores.
Change-Id: I58750ad6c3d76ce77eb354784c2a42f2c179031d
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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| 07f979bc | 13-Aug-2019 |
John Tsichritzis <john.tsichritzis@arm.com> |
Zeus: apply the MSR SSBS instruction
Zeus supports the SSBS mechanism and also the new MSR instruction to
immediately apply the mitigation. Hence, the new instruction is utilised
in the Zeus-specifi
Zeus: apply the MSR SSBS instruction
Zeus supports the SSBS mechanism and also the new MSR instruction to
immediately apply the mitigation. Hence, the new instruction is utilised
in the Zeus-specific reset function.
Change-Id: I962747c28afe85a15207a0eba4146f9a115b27e7
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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| 1f461979 | 20-Aug-2019 |
Justin Chadwell <justin.chadwell@arm.com> |
Add UBSAN support and handlers
This patch adds support for the Undefined Behaviour sanitizer. There are
two types of support offered - minimalistic trapping support which
essentially immediately cra
Add UBSAN support and handlers
This patch adds support for the Undefined Behaviour sanitizer. There are
two types of support offered - minimalistic trapping support which
essentially immediately crashes on undefined behaviour and full support
with full debug messages.
The full support relies on ubsan.c which has been adapted from code used
by OPTEE.
Change-Id: I417c810f4fc43dcb56db6a6a555bfd0b38440727
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
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