1 /* 2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <arch.h> 9 #include <arch_helpers.h> 10 #include <common/bl_common.h> 11 #include <common/debug.h> 12 #include <drivers/console.h> 13 #include <drivers/delay_timer.h> 14 #include <drivers/arm/gic_common.h> 15 #include <drivers/arm/gicv2.h> 16 #include <drivers/ti/uart/uart_16550.h> 17 #include <drivers/generic_delay_timer.h> 18 #include <drivers/arm/gicv2.h> 19 #include <lib/xlat_tables/xlat_tables.h> 20 #include <lib/mmio.h> 21 #include <plat/common/platform.h> 22 #include <platform_def.h> 23 24 #include "socfpga_private.h" 25 #include "s10_reset_manager.h" 26 #include "s10_memory_controller.h" 27 #include "s10_pinmux.h" 28 #include "s10_clock_manager.h" 29 #include "s10_system_manager.h" 30 31 static entry_point_info_t bl32_image_ep_info; 32 static entry_point_info_t bl33_image_ep_info; 33 34 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 35 { 36 entry_point_info_t *next_image_info; 37 38 next_image_info = (type == NON_SECURE) ? 39 &bl33_image_ep_info : &bl32_image_ep_info; 40 41 /* None of the images on this platform can have 0x0 as the entrypoint */ 42 if (next_image_info->pc) 43 return next_image_info; 44 else 45 return NULL; 46 } 47 48 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 49 u_register_t arg2, u_register_t arg3) 50 { 51 static console_16550_t console; 52 53 console_16550_register(PLAT_UART0_BASE, PLAT_UART_CLOCK, PLAT_BAUDRATE, 54 &console); 55 /* 56 * Check params passed from BL31 should not be NULL, 57 */ 58 void *from_bl2 = (void *) arg0; 59 60 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 61 62 assert(params_from_bl2 != NULL); 63 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 64 assert(params_from_bl2->h.version >= VERSION_2); 65 66 /* 67 * Copy BL32 (if populated by BL31) and BL33 entry point information. 68 * They are stored in Secure RAM, in BL31's address space. 69 */ 70 71 bl_params_node_t *bl_params = params_from_bl2->head; 72 73 while (bl_params) { 74 if (bl_params->image_id == BL33_IMAGE_ID) 75 bl33_image_ep_info = *bl_params->ep_info; 76 77 bl_params = bl_params->next_params_info; 78 } 79 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 80 } 81 82 static const interrupt_prop_t s10_interrupt_props[] = { 83 PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(GICV2_INTR_GROUP0), 84 PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(GICV2_INTR_GROUP0) 85 }; 86 87 static unsigned int target_mask_array[PLATFORM_CORE_COUNT]; 88 89 static const gicv2_driver_data_t plat_gicv2_gic_data = { 90 .gicd_base = PLAT_INTEL_SOCFPGA_GICD_BASE, 91 .gicc_base = PLAT_INTEL_SOCFPGA_GICC_BASE, 92 .interrupt_props = s10_interrupt_props, 93 .interrupt_props_num = ARRAY_SIZE(s10_interrupt_props), 94 .target_masks = target_mask_array, 95 .target_masks_num = ARRAY_SIZE(target_mask_array), 96 }; 97 98 /******************************************************************************* 99 * Perform any BL3-1 platform setup code 100 ******************************************************************************/ 101 void bl31_platform_setup(void) 102 { 103 /* Initialize the gic cpu and distributor interfaces */ 104 gicv2_driver_init(&plat_gicv2_gic_data); 105 gicv2_distif_init(); 106 gicv2_pcpu_distif_init(); 107 gicv2_cpuif_enable(); 108 } 109 110 const mmap_region_t plat_stratix10_mmap[] = { 111 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, 112 MT_MEMORY | MT_RW | MT_NS), 113 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, 114 MT_DEVICE | MT_RW | MT_NS), 115 MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, 116 MT_DEVICE | MT_RW | MT_SECURE), 117 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE, 118 MT_NON_CACHEABLE | MT_RW | MT_SECURE), 119 MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE, 120 MT_DEVICE | MT_RW | MT_SECURE), 121 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, 122 MT_DEVICE | MT_RW | MT_NS), 123 MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE, 124 MT_DEVICE | MT_RW | MT_NS), 125 {0} 126 }; 127 128 /******************************************************************************* 129 * Perform the very early platform specific architectural setup here. At the 130 * moment this is only intializes the mmu in a quick and dirty way. 131 ******************************************************************************/ 132 void bl31_plat_arch_setup(void) 133 { 134 const mmap_region_t bl_regions[] = { 135 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, 136 MT_MEMORY | MT_RW | MT_SECURE), 137 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 138 MT_CODE | MT_SECURE), 139 MAP_REGION_FLAT(BL_RO_DATA_BASE, 140 BL_RO_DATA_END - BL_RO_DATA_BASE, 141 MT_RO_DATA | MT_SECURE), 142 #if USE_COHERENT_MEM 143 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, 144 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 145 MT_DEVICE | MT_RW | MT_SECURE), 146 #endif 147 {0} 148 }; 149 150 setup_page_tables(bl_regions, plat_stratix10_mmap); 151 enable_mmu_el3(0); 152 } 153 154