1 /* 2 * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <common/bl_common.h> 8 #include <common/debug.h> 9 #include <smmu.h> 10 #include <tegra_def.h> 11 12 #define BOARD_SYSTEM_FPGA_BASE U(1) 13 #define BASE_CONFIG_SMMU_DEVICES U(2) 14 #define MAX_NUM_SMMU_DEVICES U(3) 15 16 static uint32_t tegra_misc_read_32(uint32_t off) 17 { 18 return mmio_read_32(TEGRA_MISC_BASE + off); 19 } 20 21 /******************************************************************************* 22 * Array to hold SMMU context for Tegra186 23 ******************************************************************************/ 24 static __attribute__((aligned(16))) smmu_regs_t tegra194_smmu_context[] = { 25 _START_OF_TABLE_, 26 mc_make_sid_security_cfg(HDAR), 27 mc_make_sid_security_cfg(HOST1XDMAR), 28 mc_make_sid_security_cfg(NVENCSRD), 29 mc_make_sid_security_cfg(SATAR), 30 mc_make_sid_security_cfg(NVENCSWR), 31 mc_make_sid_security_cfg(HDAW), 32 mc_make_sid_security_cfg(SATAW), 33 mc_make_sid_security_cfg(ISPRA), 34 mc_make_sid_security_cfg(ISPFALR), 35 mc_make_sid_security_cfg(ISPWA), 36 mc_make_sid_security_cfg(ISPWB), 37 mc_make_sid_security_cfg(XUSB_HOSTR), 38 mc_make_sid_security_cfg(XUSB_HOSTW), 39 mc_make_sid_security_cfg(XUSB_DEVR), 40 mc_make_sid_security_cfg(XUSB_DEVW), 41 mc_make_sid_security_cfg(TSECSRD), 42 mc_make_sid_security_cfg(TSECSWR), 43 mc_make_sid_security_cfg(SDMMCRA), 44 mc_make_sid_security_cfg(SDMMCR), 45 mc_make_sid_security_cfg(SDMMCRAB), 46 mc_make_sid_security_cfg(SDMMCWA), 47 mc_make_sid_security_cfg(SDMMCW), 48 mc_make_sid_security_cfg(SDMMCWAB), 49 mc_make_sid_security_cfg(VICSRD), 50 mc_make_sid_security_cfg(VICSWR), 51 mc_make_sid_security_cfg(VIW), 52 mc_make_sid_security_cfg(NVDECSRD), 53 mc_make_sid_security_cfg(NVDECSWR), 54 mc_make_sid_security_cfg(APER), 55 mc_make_sid_security_cfg(APEW), 56 mc_make_sid_security_cfg(NVJPGSRD), 57 mc_make_sid_security_cfg(NVJPGSWR), 58 mc_make_sid_security_cfg(SESRD), 59 mc_make_sid_security_cfg(SESWR), 60 mc_make_sid_security_cfg(AXIAPR), 61 mc_make_sid_security_cfg(AXIAPW), 62 mc_make_sid_security_cfg(ETRR), 63 mc_make_sid_security_cfg(ETRW), 64 mc_make_sid_security_cfg(TSECSRDB), 65 mc_make_sid_security_cfg(TSECSWRB), 66 mc_make_sid_security_cfg(AXISR), 67 mc_make_sid_security_cfg(AXISW), 68 mc_make_sid_security_cfg(EQOSR), 69 mc_make_sid_security_cfg(EQOSW), 70 mc_make_sid_security_cfg(UFSHCR), 71 mc_make_sid_security_cfg(UFSHCW), 72 mc_make_sid_security_cfg(NVDISPLAYR), 73 mc_make_sid_security_cfg(BPMPR), 74 mc_make_sid_security_cfg(BPMPW), 75 mc_make_sid_security_cfg(BPMPDMAR), 76 mc_make_sid_security_cfg(BPMPDMAW), 77 mc_make_sid_security_cfg(AONR), 78 mc_make_sid_security_cfg(AONW), 79 mc_make_sid_security_cfg(AONDMAR), 80 mc_make_sid_security_cfg(AONDMAW), 81 mc_make_sid_security_cfg(SCER), 82 mc_make_sid_security_cfg(SCEW), 83 mc_make_sid_security_cfg(SCEDMAR), 84 mc_make_sid_security_cfg(SCEDMAW), 85 mc_make_sid_security_cfg(APEDMAR), 86 mc_make_sid_security_cfg(APEDMAW), 87 mc_make_sid_security_cfg(NVDISPLAYR1), 88 mc_make_sid_security_cfg(VICSRD1), 89 mc_make_sid_security_cfg(NVDECSRD1), 90 mc_make_sid_security_cfg(VIFALR), 91 mc_make_sid_security_cfg(VIFALW), 92 mc_make_sid_security_cfg(DLA0RDA), 93 mc_make_sid_security_cfg(DLA0FALRDB), 94 mc_make_sid_security_cfg(DLA0WRA), 95 mc_make_sid_security_cfg(DLA0FALWRB), 96 mc_make_sid_security_cfg(DLA1RDA), 97 mc_make_sid_security_cfg(DLA1FALRDB), 98 mc_make_sid_security_cfg(DLA1WRA), 99 mc_make_sid_security_cfg(DLA1FALWRB), 100 mc_make_sid_security_cfg(PVA0RDA), 101 mc_make_sid_security_cfg(PVA0RDB), 102 mc_make_sid_security_cfg(PVA0RDC), 103 mc_make_sid_security_cfg(PVA0WRA), 104 mc_make_sid_security_cfg(PVA0WRB), 105 mc_make_sid_security_cfg(PVA0WRC), 106 mc_make_sid_security_cfg(PVA1RDA), 107 mc_make_sid_security_cfg(PVA1RDB), 108 mc_make_sid_security_cfg(PVA1RDC), 109 mc_make_sid_security_cfg(PVA1WRA), 110 mc_make_sid_security_cfg(PVA1WRB), 111 mc_make_sid_security_cfg(PVA1WRC), 112 mc_make_sid_security_cfg(RCER), 113 mc_make_sid_security_cfg(RCEW), 114 mc_make_sid_security_cfg(RCEDMAR), 115 mc_make_sid_security_cfg(RCEDMAW), 116 mc_make_sid_security_cfg(NVENC1SRD), 117 mc_make_sid_security_cfg(NVENC1SWR), 118 mc_make_sid_security_cfg(PCIE0R), 119 mc_make_sid_security_cfg(PCIE0W), 120 mc_make_sid_security_cfg(PCIE1R), 121 mc_make_sid_security_cfg(PCIE1W), 122 mc_make_sid_security_cfg(PCIE2AR), 123 mc_make_sid_security_cfg(PCIE2AW), 124 mc_make_sid_security_cfg(PCIE3R), 125 mc_make_sid_security_cfg(PCIE3W), 126 mc_make_sid_security_cfg(PCIE4R), 127 mc_make_sid_security_cfg(PCIE4W), 128 mc_make_sid_security_cfg(PCIE5R), 129 mc_make_sid_security_cfg(PCIE5W), 130 mc_make_sid_security_cfg(ISPFALW), 131 mc_make_sid_security_cfg(DLA0RDA1), 132 mc_make_sid_security_cfg(DLA1RDA1), 133 mc_make_sid_security_cfg(PVA0RDA1), 134 mc_make_sid_security_cfg(PVA0RDB1), 135 mc_make_sid_security_cfg(PVA1RDA1), 136 mc_make_sid_security_cfg(PVA1RDB1), 137 mc_make_sid_security_cfg(PCIE5R1), 138 mc_make_sid_security_cfg(NVENCSRD1), 139 mc_make_sid_security_cfg(NVENC1SRD1), 140 mc_make_sid_security_cfg(ISPRA1), 141 mc_make_sid_security_cfg(MIU0R), 142 mc_make_sid_security_cfg(MIU0W), 143 mc_make_sid_security_cfg(MIU1R), 144 mc_make_sid_security_cfg(MIU1W), 145 mc_make_sid_security_cfg(MIU2R), 146 mc_make_sid_security_cfg(MIU2W), 147 mc_make_sid_security_cfg(MIU3R), 148 mc_make_sid_security_cfg(MIU3W), 149 mc_make_sid_override_cfg(HDAR), 150 mc_make_sid_override_cfg(HOST1XDMAR), 151 mc_make_sid_override_cfg(NVENCSRD), 152 mc_make_sid_override_cfg(SATAR), 153 mc_make_sid_override_cfg(NVENCSWR), 154 mc_make_sid_override_cfg(HDAW), 155 mc_make_sid_override_cfg(SATAW), 156 mc_make_sid_override_cfg(ISPRA), 157 mc_make_sid_override_cfg(ISPFALR), 158 mc_make_sid_override_cfg(ISPWA), 159 mc_make_sid_override_cfg(ISPWB), 160 mc_make_sid_override_cfg(XUSB_HOSTR), 161 mc_make_sid_override_cfg(XUSB_HOSTW), 162 mc_make_sid_override_cfg(XUSB_DEVR), 163 mc_make_sid_override_cfg(XUSB_DEVW), 164 mc_make_sid_override_cfg(TSECSRD), 165 mc_make_sid_override_cfg(TSECSWR), 166 mc_make_sid_override_cfg(SDMMCRA), 167 mc_make_sid_override_cfg(SDMMCR), 168 mc_make_sid_override_cfg(SDMMCRAB), 169 mc_make_sid_override_cfg(SDMMCWA), 170 mc_make_sid_override_cfg(SDMMCW), 171 mc_make_sid_override_cfg(SDMMCWAB), 172 mc_make_sid_override_cfg(VICSRD), 173 mc_make_sid_override_cfg(VICSWR), 174 mc_make_sid_override_cfg(VIW), 175 mc_make_sid_override_cfg(NVDECSRD), 176 mc_make_sid_override_cfg(NVDECSWR), 177 mc_make_sid_override_cfg(APER), 178 mc_make_sid_override_cfg(APEW), 179 mc_make_sid_override_cfg(NVJPGSRD), 180 mc_make_sid_override_cfg(NVJPGSWR), 181 mc_make_sid_override_cfg(SESRD), 182 mc_make_sid_override_cfg(SESWR), 183 mc_make_sid_override_cfg(AXIAPR), 184 mc_make_sid_override_cfg(AXIAPW), 185 mc_make_sid_override_cfg(ETRR), 186 mc_make_sid_override_cfg(ETRW), 187 mc_make_sid_override_cfg(TSECSRDB), 188 mc_make_sid_override_cfg(TSECSWRB), 189 mc_make_sid_override_cfg(AXISR), 190 mc_make_sid_override_cfg(AXISW), 191 mc_make_sid_override_cfg(EQOSR), 192 mc_make_sid_override_cfg(EQOSW), 193 mc_make_sid_override_cfg(UFSHCR), 194 mc_make_sid_override_cfg(UFSHCW), 195 mc_make_sid_override_cfg(NVDISPLAYR), 196 mc_make_sid_override_cfg(BPMPR), 197 mc_make_sid_override_cfg(BPMPW), 198 mc_make_sid_override_cfg(BPMPDMAR), 199 mc_make_sid_override_cfg(BPMPDMAW), 200 mc_make_sid_override_cfg(AONR), 201 mc_make_sid_override_cfg(AONW), 202 mc_make_sid_override_cfg(AONDMAR), 203 mc_make_sid_override_cfg(AONDMAW), 204 mc_make_sid_override_cfg(SCER), 205 mc_make_sid_override_cfg(SCEW), 206 mc_make_sid_override_cfg(SCEDMAR), 207 mc_make_sid_override_cfg(SCEDMAW), 208 mc_make_sid_override_cfg(APEDMAR), 209 mc_make_sid_override_cfg(APEDMAW), 210 mc_make_sid_override_cfg(NVDISPLAYR1), 211 mc_make_sid_override_cfg(VICSRD1), 212 mc_make_sid_override_cfg(NVDECSRD1), 213 mc_make_sid_override_cfg(VIFALR), 214 mc_make_sid_override_cfg(VIFALW), 215 mc_make_sid_override_cfg(DLA0RDA), 216 mc_make_sid_override_cfg(DLA0FALRDB), 217 mc_make_sid_override_cfg(DLA0WRA), 218 mc_make_sid_override_cfg(DLA0FALWRB), 219 mc_make_sid_override_cfg(DLA1RDA), 220 mc_make_sid_override_cfg(DLA1FALRDB), 221 mc_make_sid_override_cfg(DLA1WRA), 222 mc_make_sid_override_cfg(DLA1FALWRB), 223 mc_make_sid_override_cfg(PVA0RDA), 224 mc_make_sid_override_cfg(PVA0RDB), 225 mc_make_sid_override_cfg(PVA0RDC), 226 mc_make_sid_override_cfg(PVA0WRA), 227 mc_make_sid_override_cfg(PVA0WRB), 228 mc_make_sid_override_cfg(PVA0WRC), 229 mc_make_sid_override_cfg(PVA1RDA), 230 mc_make_sid_override_cfg(PVA1RDB), 231 mc_make_sid_override_cfg(PVA1RDC), 232 mc_make_sid_override_cfg(PVA1WRA), 233 mc_make_sid_override_cfg(PVA1WRB), 234 mc_make_sid_override_cfg(PVA1WRC), 235 mc_make_sid_override_cfg(RCER), 236 mc_make_sid_override_cfg(RCEW), 237 mc_make_sid_override_cfg(RCEDMAR), 238 mc_make_sid_override_cfg(RCEDMAW), 239 mc_make_sid_override_cfg(NVENC1SRD), 240 mc_make_sid_override_cfg(NVENC1SWR), 241 mc_make_sid_override_cfg(PCIE0R), 242 mc_make_sid_override_cfg(PCIE0W), 243 mc_make_sid_override_cfg(PCIE1R), 244 mc_make_sid_override_cfg(PCIE1W), 245 mc_make_sid_override_cfg(PCIE2AR), 246 mc_make_sid_override_cfg(PCIE2AW), 247 mc_make_sid_override_cfg(PCIE3R), 248 mc_make_sid_override_cfg(PCIE3W), 249 mc_make_sid_override_cfg(PCIE4R), 250 mc_make_sid_override_cfg(PCIE4W), 251 mc_make_sid_override_cfg(PCIE5R), 252 mc_make_sid_override_cfg(PCIE5W), 253 mc_make_sid_override_cfg(ISPFALW), 254 mc_make_sid_override_cfg(DLA0RDA1), 255 mc_make_sid_override_cfg(DLA1RDA1), 256 mc_make_sid_override_cfg(PVA0RDA1), 257 mc_make_sid_override_cfg(PVA0RDB1), 258 mc_make_sid_override_cfg(PVA1RDA1), 259 mc_make_sid_override_cfg(PVA1RDB1), 260 mc_make_sid_override_cfg(PCIE5R1), 261 mc_make_sid_override_cfg(NVENCSRD1), 262 mc_make_sid_override_cfg(NVENC1SRD1), 263 mc_make_sid_override_cfg(ISPRA1), 264 mc_make_sid_override_cfg(MIU0R), 265 mc_make_sid_override_cfg(MIU0W), 266 mc_make_sid_override_cfg(MIU1R), 267 mc_make_sid_override_cfg(MIU1W), 268 mc_make_sid_override_cfg(MIU2R), 269 mc_make_sid_override_cfg(MIU2W), 270 mc_make_sid_override_cfg(MIU3R), 271 mc_make_sid_override_cfg(MIU3W), 272 smmu_make_gnsr0_nsec_cfg(CR0), 273 smmu_make_gnsr0_sec_cfg(IDR0), 274 smmu_make_gnsr0_sec_cfg(IDR1), 275 smmu_make_gnsr0_sec_cfg(IDR2), 276 smmu_make_gnsr0_nsec_cfg(GFSR), 277 smmu_make_gnsr0_nsec_cfg(GFSYNR0), 278 smmu_make_gnsr0_nsec_cfg(GFSYNR1), 279 smmu_make_gnsr0_nsec_cfg(TLBGSTATUS), 280 smmu_make_gnsr0_nsec_cfg(PIDR2), 281 smmu_make_smrg_group(0), 282 smmu_make_smrg_group(1), 283 smmu_make_smrg_group(2), 284 smmu_make_smrg_group(3), 285 smmu_make_smrg_group(4), 286 smmu_make_smrg_group(5), 287 smmu_make_smrg_group(6), 288 smmu_make_smrg_group(7), 289 smmu_make_smrg_group(8), 290 smmu_make_smrg_group(9), 291 smmu_make_smrg_group(10), 292 smmu_make_smrg_group(11), 293 smmu_make_smrg_group(12), 294 smmu_make_smrg_group(13), 295 smmu_make_smrg_group(14), 296 smmu_make_smrg_group(15), 297 smmu_make_smrg_group(16), 298 smmu_make_smrg_group(17), 299 smmu_make_smrg_group(18), 300 smmu_make_smrg_group(19), 301 smmu_make_smrg_group(20), 302 smmu_make_smrg_group(21), 303 smmu_make_smrg_group(22), 304 smmu_make_smrg_group(23), 305 smmu_make_smrg_group(24), 306 smmu_make_smrg_group(25), 307 smmu_make_smrg_group(26), 308 smmu_make_smrg_group(27), 309 smmu_make_smrg_group(28), 310 smmu_make_smrg_group(29), 311 smmu_make_smrg_group(30), 312 smmu_make_smrg_group(31), 313 smmu_make_smrg_group(32), 314 smmu_make_smrg_group(33), 315 smmu_make_smrg_group(34), 316 smmu_make_smrg_group(35), 317 smmu_make_smrg_group(36), 318 smmu_make_smrg_group(37), 319 smmu_make_smrg_group(38), 320 smmu_make_smrg_group(39), 321 smmu_make_smrg_group(40), 322 smmu_make_smrg_group(41), 323 smmu_make_smrg_group(42), 324 smmu_make_smrg_group(43), 325 smmu_make_smrg_group(44), 326 smmu_make_smrg_group(45), 327 smmu_make_smrg_group(46), 328 smmu_make_smrg_group(47), 329 smmu_make_smrg_group(48), 330 smmu_make_smrg_group(49), 331 smmu_make_smrg_group(50), 332 smmu_make_smrg_group(51), 333 smmu_make_smrg_group(52), 334 smmu_make_smrg_group(53), 335 smmu_make_smrg_group(54), 336 smmu_make_smrg_group(55), 337 smmu_make_smrg_group(56), 338 smmu_make_smrg_group(57), 339 smmu_make_smrg_group(58), 340 smmu_make_smrg_group(59), 341 smmu_make_smrg_group(60), 342 smmu_make_smrg_group(61), 343 smmu_make_smrg_group(62), 344 smmu_make_smrg_group(63), 345 smmu_make_cb_group(0), 346 smmu_make_cb_group(1), 347 smmu_make_cb_group(2), 348 smmu_make_cb_group(3), 349 smmu_make_cb_group(4), 350 smmu_make_cb_group(5), 351 smmu_make_cb_group(6), 352 smmu_make_cb_group(7), 353 smmu_make_cb_group(8), 354 smmu_make_cb_group(9), 355 smmu_make_cb_group(10), 356 smmu_make_cb_group(11), 357 smmu_make_cb_group(12), 358 smmu_make_cb_group(13), 359 smmu_make_cb_group(14), 360 smmu_make_cb_group(15), 361 smmu_make_cb_group(16), 362 smmu_make_cb_group(17), 363 smmu_make_cb_group(18), 364 smmu_make_cb_group(19), 365 smmu_make_cb_group(20), 366 smmu_make_cb_group(21), 367 smmu_make_cb_group(22), 368 smmu_make_cb_group(23), 369 smmu_make_cb_group(24), 370 smmu_make_cb_group(25), 371 smmu_make_cb_group(26), 372 smmu_make_cb_group(27), 373 smmu_make_cb_group(28), 374 smmu_make_cb_group(29), 375 smmu_make_cb_group(30), 376 smmu_make_cb_group(31), 377 smmu_make_cb_group(32), 378 smmu_make_cb_group(33), 379 smmu_make_cb_group(34), 380 smmu_make_cb_group(35), 381 smmu_make_cb_group(36), 382 smmu_make_cb_group(37), 383 smmu_make_cb_group(38), 384 smmu_make_cb_group(39), 385 smmu_make_cb_group(40), 386 smmu_make_cb_group(41), 387 smmu_make_cb_group(42), 388 smmu_make_cb_group(43), 389 smmu_make_cb_group(44), 390 smmu_make_cb_group(45), 391 smmu_make_cb_group(46), 392 smmu_make_cb_group(47), 393 smmu_make_cb_group(48), 394 smmu_make_cb_group(49), 395 smmu_make_cb_group(50), 396 smmu_make_cb_group(51), 397 smmu_make_cb_group(52), 398 smmu_make_cb_group(53), 399 smmu_make_cb_group(54), 400 smmu_make_cb_group(55), 401 smmu_make_cb_group(56), 402 smmu_make_cb_group(57), 403 smmu_make_cb_group(58), 404 smmu_make_cb_group(59), 405 smmu_make_cb_group(60), 406 smmu_make_cb_group(61), 407 smmu_make_cb_group(62), 408 smmu_make_cb_group(63), 409 smmu_bypass_cfg, /* TBU settings */ 410 _END_OF_TABLE_, 411 }; 412 413 /******************************************************************************* 414 * Handler to return the pointer to the SMMU's context struct 415 ******************************************************************************/ 416 smmu_regs_t *plat_get_smmu_ctx(void) 417 { 418 /* index of _END_OF_TABLE_ */ 419 tegra194_smmu_context[0].val = ARRAY_SIZE(tegra194_smmu_context) - 1; 420 421 return tegra194_smmu_context; 422 } 423 424 /******************************************************************************* 425 * Handler to return the support SMMU devices number 426 ******************************************************************************/ 427 uint32_t plat_get_num_smmu_devices(void) 428 { 429 uint32_t ret_num = MAX_NUM_SMMU_DEVICES; 430 uint32_t board_revid = ((tegra_misc_read_32(MISCREG_EMU_REVID) >> \ 431 BOARD_SHIFT_BITS) && BOARD_MASK_BITS); 432 433 if (board_revid == BOARD_SYSTEM_FPGA_BASE) { 434 ret_num = BASE_CONFIG_SMMU_DEVICES; 435 } 436 437 return ret_num; 438 } 439