1 /* 2 * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <common/bl_common.h> 11 #include <lib/el3_runtime/context_mgmt.h> 12 #include <common/debug.h> 13 #include <errno.h> 14 #include <mce.h> 15 #include <memctrl.h> 16 #include <common/runtime_svc.h> 17 #include <tegra_private.h> 18 #include <tegra_platform.h> 19 #include <stdbool.h> 20 21 extern uint32_t tegra186_system_powerdn_state; 22 23 extern bool tegra_fake_system_suspend; 24 25 /******************************************************************************* 26 * Tegra186 SiP SMCs 27 ******************************************************************************/ 28 #define TEGRA_SIP_SYSTEM_SHUTDOWN_STATE 0xC2FFFE01 29 #define TEGRA_SIP_GET_ACTMON_CLK_COUNTERS 0xC2FFFE02 30 #define TEGRA_SIP_ENABLE_FAKE_SYSTEM_SUSPEND 0xC2FFFE03 31 #define TEGRA_SIP_MCE_CMD_ENTER_CSTATE 0xC2FFFF00 32 #define TEGRA_SIP_MCE_CMD_UPDATE_CSTATE_INFO 0xC2FFFF01 33 #define TEGRA_SIP_MCE_CMD_UPDATE_CROSSOVER_TIME 0xC2FFFF02 34 #define TEGRA_SIP_MCE_CMD_READ_CSTATE_STATS 0xC2FFFF03 35 #define TEGRA_SIP_MCE_CMD_WRITE_CSTATE_STATS 0xC2FFFF04 36 #define TEGRA_SIP_MCE_CMD_IS_SC7_ALLOWED 0xC2FFFF05 37 #define TEGRA_SIP_MCE_CMD_ONLINE_CORE 0xC2FFFF06 38 #define TEGRA_SIP_MCE_CMD_CC3_CTRL 0xC2FFFF07 39 #define TEGRA_SIP_MCE_CMD_ECHO_DATA 0xC2FFFF08 40 #define TEGRA_SIP_MCE_CMD_READ_VERSIONS 0xC2FFFF09 41 #define TEGRA_SIP_MCE_CMD_ENUM_FEATURES 0xC2FFFF0A 42 #define TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE_TRBITS 0xC2FFFF0B 43 #define TEGRA_SIP_MCE_CMD_ENUM_READ_MCA 0xC2FFFF0C 44 #define TEGRA_SIP_MCE_CMD_ENUM_WRITE_MCA 0xC2FFFF0D 45 #define TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE 0xC2FFFF0E 46 #define TEGRA_SIP_MCE_CMD_ROC_CLEAN_CACHE 0xC2FFFF0F 47 #define TEGRA_SIP_MCE_CMD_ENABLE_LATIC 0xC2FFFF10 48 #define TEGRA_SIP_MCE_CMD_UNCORE_PERFMON_REQ 0xC2FFFF11 49 #define TEGRA_SIP_MCE_CMD_MISC_CCPLEX 0xC2FFFF12 50 51 /******************************************************************************* 52 * This function is responsible for handling all T186 SiP calls 53 ******************************************************************************/ 54 int plat_sip_handler(uint32_t smc_fid, 55 uint64_t x1, 56 uint64_t x2, 57 uint64_t x3, 58 uint64_t x4, 59 const void *cookie, 60 void *handle, 61 uint64_t flags) 62 { 63 int mce_ret; 64 65 /* 66 * Convert SMC FID to SMC64 until the linux driver uses 67 * SMC64 encoding. 68 */ 69 smc_fid |= (SMC_64 << FUNCID_CC_SHIFT); 70 71 switch (smc_fid) { 72 73 /* 74 * Micro Coded Engine (MCE) commands reside in the 0x82FFFF00 - 75 * 0x82FFFFFF SiP SMC space 76 */ 77 case TEGRA_SIP_MCE_CMD_ENTER_CSTATE: 78 case TEGRA_SIP_MCE_CMD_UPDATE_CSTATE_INFO: 79 case TEGRA_SIP_MCE_CMD_UPDATE_CROSSOVER_TIME: 80 case TEGRA_SIP_MCE_CMD_READ_CSTATE_STATS: 81 case TEGRA_SIP_MCE_CMD_WRITE_CSTATE_STATS: 82 case TEGRA_SIP_MCE_CMD_IS_SC7_ALLOWED: 83 case TEGRA_SIP_MCE_CMD_CC3_CTRL: 84 case TEGRA_SIP_MCE_CMD_ECHO_DATA: 85 case TEGRA_SIP_MCE_CMD_READ_VERSIONS: 86 case TEGRA_SIP_MCE_CMD_ENUM_FEATURES: 87 case TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE_TRBITS: 88 case TEGRA_SIP_MCE_CMD_ENUM_READ_MCA: 89 case TEGRA_SIP_MCE_CMD_ENUM_WRITE_MCA: 90 case TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE: 91 case TEGRA_SIP_MCE_CMD_ROC_CLEAN_CACHE: 92 case TEGRA_SIP_MCE_CMD_ENABLE_LATIC: 93 case TEGRA_SIP_MCE_CMD_UNCORE_PERFMON_REQ: 94 case TEGRA_SIP_MCE_CMD_MISC_CCPLEX: 95 96 /* clean up the high bits */ 97 smc_fid &= MCE_CMD_MASK; 98 99 /* execute the command and store the result */ 100 mce_ret = mce_command_handler(smc_fid, x1, x2, x3); 101 write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X0, mce_ret); 102 103 return 0; 104 105 case TEGRA_SIP_SYSTEM_SHUTDOWN_STATE: 106 107 /* clean up the high bits */ 108 x1 = (uint32_t)x1; 109 110 /* 111 * SC8 is a special Tegra186 system state where the CPUs and 112 * DRAM are powered down but the other subsystem is still 113 * alive. 114 */ 115 116 return 0; 117 118 case TEGRA_SIP_ENABLE_FAKE_SYSTEM_SUSPEND: 119 /* 120 * System suspend mode is set if the platform ATF is running is 121 * VDK and there is a debug SIP call. This mode ensures that the 122 * debug path is excercied, instead of regular code path to suit 123 * the pre-silicon platform needs. These include replacing the 124 * the call to WFI with calls to system suspend exit procedures. 125 */ 126 if (tegra_platform_is_virt_dev_kit()) { 127 128 tegra_fake_system_suspend = true; 129 return 0; 130 } 131 132 break; 133 134 default: 135 break; 136 } 137 138 return -ENOTSUP; 139 } 140